diff --git a/projects/common/ml605/data/sys_ddr3_mem_mig_saved.prj b/projects/common/ml605/data/sys_ddr3_mem_mig_saved.prj new file mode 100755 index 000000000..24ae44144 --- /dev/null +++ b/projects/common/ml605/data/sys_ddr3_mem_mig_saved.prj @@ -0,0 +1,203 @@ + + + DDR3_SDRAM + 1 + 0 + OFF + xc6vlx240t-ff1156/-1 + 3.8 + Differential + TRUE + HIGH + 0 + IODELAY_MIG + + DDR3_SDRAM/SODIMMs/MT4JSF6464HY-1G1 + 2500 + 64 + 1 + 1 + FALSE + + 13 + 10 + 3 + 26,36 + + + + Disabled + 1 + 36 + BANK_ROW_COLUMN + Normal + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/7 + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + AUTOMATIC + AUTOMATIC + AUTOMATIC + microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC + 4 + 0 + AUTOMATIC + 0 + 4 + 0 + AUTOMATIC + 32 + 0xc0000000 + 32 + 0xcfffffff + Auto + + + diff --git a/projects/common/ml605/data/system.ncf b/projects/common/ml605/data/system.ncf new file mode 100755 index 000000000..f45d26fc3 --- /dev/null +++ b/projects/common/ml605/data/system.ncf @@ -0,0 +1,70 @@ + +NET sys_rst LOC = H10 | IOSTANDARD = SSTL15 | TIG; +NET sys_clk_p LOC = J9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; +NET sys_clk_n LOC = H9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; +NET ddr3_a13 LOC = J15 | IOSTANDARD = SSTL15 | TIG; + +NET sys_clk_p TNM_NET = sys_clk_p; +TIMESPEC ts_sys_clk_p = PERIOD sys_clk_p 200 MHz; + +NET uart_tx LOC = J25 | IOSTANDARD = LVCMOS25; +NET uart_rx LOC = J24 | IOSTANDARD = LVCMOS25; + +NET phy_rstn LOC = AH13 | IOSTANDARD = LVCMOS25 | TIG; +NET phy_mdc LOC = AP14 | IOSTANDARD = LVCMOS25; +NET phy_mdio LOC = AN14 | IOSTANDARD = LVCMOS25; +NET phy_crs LOC = AL13 | IOSTANDARD = LVCMOS25; +NET phy_col LOC = AK13 | IOSTANDARD = LVCMOS25; +NET phy_tx_clk LOC = AD12 | IOSTANDARD = LVCMOS25; +NET phy_tx_en LOC = AJ10 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[0] LOC = AM11 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[1] LOC = AL11 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[2] LOC = AG10 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[3] LOC = AG11 | IOSTANDARD = LVCMOS25; +NET phy_rx_clk LOC = AP11 | IOSTANDARD = LVCMOS25; +NET phy_rx_dv LOC = AM13 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[0] LOC = AN13 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[1] LOC = AF14 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[2] LOC = AE14 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[3] LOC = AN12 | IOSTANDARD = LVCMOS25; +NET phy_rx_er LOC = AG12 | IOSTANDARD = LVCMOS25; + +NET iic_scl LOC = AF13 | IOSTANDARD = LVCMOS25; +NET iic_sda LOC = AG13 | IOSTANDARD = LVCMOS25; + +NET lcd[6] LOC = AK12 | IOSTANDARD = LVCMOS25; ## lcd_e +NET lcd[5] LOC = T28 | IOSTANDARD = LVCMOS25; ## lcd_rs +NET lcd[4] LOC = AC14 | IOSTANDARD = LVCMOS25; ## lcd_rw +NET lcd[3] LOC = AE12 | IOSTANDARD = LVCMOS25; ## lcd_db[7] +NET lcd[2] LOC = AJ11 | IOSTANDARD = LVCMOS25; ## lcd_db[6] +NET lcd[1] LOC = AK11 | IOSTANDARD = LVCMOS25; ## lcd_db[5] +NET lcd[0] LOC = AD14 | IOSTANDARD = LVCMOS25; ## lcd_db[4] + +NET sw[0] LOC = D22 | IOSTANDARD = LVCMOS15; +NET sw[1] LOC = C22 | IOSTANDARD = LVCMOS15; +NET sw[2] LOC = L21 | IOSTANDARD = LVCMOS15; +NET sw[3] LOC = L20 | IOSTANDARD = LVCMOS15; +NET sw[4] LOC = C18 | IOSTANDARD = LVCMOS15; +NET sw[5] LOC = B18 | IOSTANDARD = LVCMOS15; +NET sw[6] LOC = K22 | IOSTANDARD = LVCMOS15; +NET sw[7] LOC = K21 | IOSTANDARD = LVCMOS15; +NET sw[8] LOC = G26 | IOSTANDARD = LVCMOS15; +NET sw[9] LOC = A19 | IOSTANDARD = LVCMOS15; +NET sw[10] LOC = G17 | IOSTANDARD = LVCMOS15; +NET sw[11] LOC = A18 | IOSTANDARD = LVCMOS15; +NET sw[12] LOC = H17 | IOSTANDARD = LVCMOS15; + +NET led[0] LOC = AC22 | IOSTANDARD = LVCMOS25; +NET led[1] LOC = AC24 | IOSTANDARD = LVCMOS25; +NET led[2] LOC = AE22 | IOSTANDARD = LVCMOS25; +NET led[3] LOC = AE23 | IOSTANDARD = LVCMOS25; +NET led[4] LOC = AB23 | IOSTANDARD = LVCMOS25; +NET led[5] LOC = AG23 | IOSTANDARD = LVCMOS25; +NET led[6] LOC = AE24 | IOSTANDARD = LVCMOS25; +NET led[7] LOC = AD24 | IOSTANDARD = LVCMOS25; +NET led[8] LOC = AP24 | IOSTANDARD = LVCMOS25; +NET led[9] LOC = AE21 | IOSTANDARD = LVCMOS25; +NET led[10] LOC = AH27 | IOSTANDARD = LVCMOS25; +NET led[11] LOC = AH28 | IOSTANDARD = LVCMOS25; +NET led[12] LOC = AD21 | IOSTANDARD = LVCMOS25; + diff --git a/projects/common/ml605/data/system.ucf b/projects/common/ml605/data/system.ucf new file mode 100755 index 000000000..f45d26fc3 --- /dev/null +++ b/projects/common/ml605/data/system.ucf @@ -0,0 +1,70 @@ + +NET sys_rst LOC = H10 | IOSTANDARD = SSTL15 | TIG; +NET sys_clk_p LOC = J9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; +NET sys_clk_n LOC = H9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; +NET ddr3_a13 LOC = J15 | IOSTANDARD = SSTL15 | TIG; + +NET sys_clk_p TNM_NET = sys_clk_p; +TIMESPEC ts_sys_clk_p = PERIOD sys_clk_p 200 MHz; + +NET uart_tx LOC = J25 | IOSTANDARD = LVCMOS25; +NET uart_rx LOC = J24 | IOSTANDARD = LVCMOS25; + +NET phy_rstn LOC = AH13 | IOSTANDARD = LVCMOS25 | TIG; +NET phy_mdc LOC = AP14 | IOSTANDARD = LVCMOS25; +NET phy_mdio LOC = AN14 | IOSTANDARD = LVCMOS25; +NET phy_crs LOC = AL13 | IOSTANDARD = LVCMOS25; +NET phy_col LOC = AK13 | IOSTANDARD = LVCMOS25; +NET phy_tx_clk LOC = AD12 | IOSTANDARD = LVCMOS25; +NET phy_tx_en LOC = AJ10 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[0] LOC = AM11 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[1] LOC = AL11 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[2] LOC = AG10 | IOSTANDARD = LVCMOS25; +NET phy_tx_d[3] LOC = AG11 | IOSTANDARD = LVCMOS25; +NET phy_rx_clk LOC = AP11 | IOSTANDARD = LVCMOS25; +NET phy_rx_dv LOC = AM13 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[0] LOC = AN13 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[1] LOC = AF14 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[2] LOC = AE14 | IOSTANDARD = LVCMOS25; +NET phy_rx_d[3] LOC = AN12 | IOSTANDARD = LVCMOS25; +NET phy_rx_er LOC = AG12 | IOSTANDARD = LVCMOS25; + +NET iic_scl LOC = AF13 | IOSTANDARD = LVCMOS25; +NET iic_sda LOC = AG13 | IOSTANDARD = LVCMOS25; + +NET lcd[6] LOC = AK12 | IOSTANDARD = LVCMOS25; ## lcd_e +NET lcd[5] LOC = T28 | IOSTANDARD = LVCMOS25; ## lcd_rs +NET lcd[4] LOC = AC14 | IOSTANDARD = LVCMOS25; ## lcd_rw +NET lcd[3] LOC = AE12 | IOSTANDARD = LVCMOS25; ## lcd_db[7] +NET lcd[2] LOC = AJ11 | IOSTANDARD = LVCMOS25; ## lcd_db[6] +NET lcd[1] LOC = AK11 | IOSTANDARD = LVCMOS25; ## lcd_db[5] +NET lcd[0] LOC = AD14 | IOSTANDARD = LVCMOS25; ## lcd_db[4] + +NET sw[0] LOC = D22 | IOSTANDARD = LVCMOS15; +NET sw[1] LOC = C22 | IOSTANDARD = LVCMOS15; +NET sw[2] LOC = L21 | IOSTANDARD = LVCMOS15; +NET sw[3] LOC = L20 | IOSTANDARD = LVCMOS15; +NET sw[4] LOC = C18 | IOSTANDARD = LVCMOS15; +NET sw[5] LOC = B18 | IOSTANDARD = LVCMOS15; +NET sw[6] LOC = K22 | IOSTANDARD = LVCMOS15; +NET sw[7] LOC = K21 | IOSTANDARD = LVCMOS15; +NET sw[8] LOC = G26 | IOSTANDARD = LVCMOS15; +NET sw[9] LOC = A19 | IOSTANDARD = LVCMOS15; +NET sw[10] LOC = G17 | IOSTANDARD = LVCMOS15; +NET sw[11] LOC = A18 | IOSTANDARD = LVCMOS15; +NET sw[12] LOC = H17 | IOSTANDARD = LVCMOS15; + +NET led[0] LOC = AC22 | IOSTANDARD = LVCMOS25; +NET led[1] LOC = AC24 | IOSTANDARD = LVCMOS25; +NET led[2] LOC = AE22 | IOSTANDARD = LVCMOS25; +NET led[3] LOC = AE23 | IOSTANDARD = LVCMOS25; +NET led[4] LOC = AB23 | IOSTANDARD = LVCMOS25; +NET led[5] LOC = AG23 | IOSTANDARD = LVCMOS25; +NET led[6] LOC = AE24 | IOSTANDARD = LVCMOS25; +NET led[7] LOC = AD24 | IOSTANDARD = LVCMOS25; +NET led[8] LOC = AP24 | IOSTANDARD = LVCMOS25; +NET led[9] LOC = AE21 | IOSTANDARD = LVCMOS25; +NET led[10] LOC = AH27 | IOSTANDARD = LVCMOS25; +NET led[11] LOC = AH28 | IOSTANDARD = LVCMOS25; +NET led[12] LOC = AD21 | IOSTANDARD = LVCMOS25; + diff --git a/projects/common/ml605/pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.mpd b/projects/common/ml605/pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.mpd new file mode 100755 index 000000000..d82fb184c --- /dev/null +++ b/projects/common/ml605/pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.mpd @@ -0,0 +1,70 @@ +################################################################### +## +## Name : axi_dev +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN axi_dev + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = MIXED +OPTION IP_GROUP = MICROBLAZE:USER +OPTION DESC = axi_dev +OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT) + +## Bus Interfaces +BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_S_AXI_MIN_SIZE = 0x0000ffff, DT = std_logic_vector, BUS = S_AXI +PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI, MIN_SIZE = 0x100 +PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI +PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI + +## AXI Passthrough +PORT axil_aclk = "", DIR = O, SIGIS = CLK +PORT axil_aresetn = "", DIR = O, SIGIS = RST +PORT axil_awvalid = "", DIR = O +PORT axil_awaddr = "", DIR = O, VEC = [31:0] +PORT axil_awready = "", DIR = I +PORT axil_wvalid = "", DIR = O +PORT axil_wdata = "", DIR = O, VEC = [31:0] +PORT axil_wstrb = "", DIR = O, VEC = [3:0] +PORT axil_wready = "", DIR = I +PORT axil_bvalid = "", DIR = I +PORT axil_bresp = "", DIR = I, VEC = [1:0] +PORT axil_bready = "", DIR = O +PORT axil_arvalid = "", DIR = O +PORT axil_araddr = "", DIR = O, VEC = [31:0] +PORT axil_arready = "", DIR = I +PORT axil_rvalid = "", DIR = I +PORT axil_rdata = "", DIR = I, VEC = [31:0] +PORT axil_rresp = "", DIR = I, VEC = [1:0] +PORT axil_rready = "", DIR = O + +## AXI Interface +PORT s_axi_aclk = ACLK, DIR = I, SIGIS = CLK, BUS = S_AXI +PORT s_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI +PORT s_axi_awvalid = AWVALID, DIR = I, BUS = S_AXI +PORT s_axi_awaddr = AWADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_awready = AWREADY, DIR = O, BUS = S_AXI +PORT s_axi_wvalid = WVALID, DIR = I, BUS = S_AXI +PORT s_axi_wdata = WDATA, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_wstrb = WSTRB, DIR = I, VEC = [3:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_wready = WREADY, DIR = O, BUS = S_AXI +PORT s_axi_bvalid = BVALID, DIR = O, BUS = S_AXI +PORT s_axi_bresp = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI +PORT s_axi_bready = BREADY, DIR = I, BUS = S_AXI +PORT s_axi_arvalid = ARVALID, DIR = I, BUS = S_AXI +PORT s_axi_araddr = ARADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_arready = ARREADY, DIR = O, BUS = S_AXI +PORT s_axi_rvalid = RVALID, DIR = O, BUS = S_AXI +PORT s_axi_rdata = RDATA, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_rresp = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI +PORT s_axi_rready = RREADY, DIR = I, BUS = S_AXI + +END diff --git a/projects/common/ml605/pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.pao b/projects/common/ml605/pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.pao new file mode 100755 index 000000000..87ff793f1 --- /dev/null +++ b/projects/common/ml605/pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.pao @@ -0,0 +1,8 @@ +############################################################################## +## Filename: pcores/axi_dev_v1_00_a/data/axi_dev_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Fri Aug 26 11:12:50 2011 (by Create and Import Peripheral Wizard) +############################################################################## + +lib axi_dev_v1_00_a axi_dev verilog + diff --git a/projects/common/ml605/pcores/axi_dev_v1_00_a/hdl/verilog/axi_dev.v b/projects/common/ml605/pcores/axi_dev_v1_00_a/hdl/verilog/axi_dev.v new file mode 100755 index 000000000..aea263cd4 --- /dev/null +++ b/projects/common/ml605/pcores/axi_dev_v1_00_a/hdl/verilog/axi_dev.v @@ -0,0 +1,164 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dev ( + + // external interface + + axil_aclk, + axil_aresetn, + axil_awvalid, + axil_awaddr, + axil_awready, + axil_wvalid, + axil_wdata, + axil_wstrb, + axil_wready, + axil_bvalid, + axil_bresp, + axil_bready, + axil_arvalid, + axil_araddr, + axil_arready, + axil_rvalid, + axil_rdata, + axil_rresp, + axil_rready, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready); + + // parameters + + parameter C_S_AXI_MIN_SIZE = 32'hffff; + parameter C_BASEADDR = 32'hffffffff; + parameter C_HIGHADDR = 32'h00000000; + + // external interface + + output axil_aclk; + output axil_aresetn; + output axil_awvalid; + output [31:0] axil_awaddr; + input axil_awready; + output axil_wvalid; + output [31:0] axil_wdata; + output [ 3:0] axil_wstrb; + input axil_wready; + input axil_bvalid; + input [ 1:0] axil_bresp; + output axil_bready; + output axil_arvalid; + output [31:0] axil_araddr; + input axil_arready; + input axil_rvalid; + input [31:0] axil_rdata; + input [ 1:0] axil_rresp; + output axil_rready; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // assignments + + assign axil_aclk = s_axi_aclk; + assign axil_aresetn = s_axi_aresetn; + assign axil_awvalid = s_axi_awvalid; + assign axil_awaddr = s_axi_awaddr; + assign axil_wvalid = s_axi_wvalid; + assign axil_wdata = s_axi_wdata; + assign axil_wstrb = s_axi_wstrb; + assign axil_bready = s_axi_bready; + assign axil_arvalid = s_axi_arvalid; + assign axil_araddr = s_axi_araddr; + assign axil_rready = s_axi_rready; + + assign s_axi_awready = axil_awready; + assign s_axi_wready = axil_wready; + assign s_axi_bvalid = axil_bvalid; + assign s_axi_bresp = axil_bresp; + assign s_axi_arready = axil_arready; + assign s_axi_rvalid = axil_rvalid; + assign s_axi_rdata = axil_rdata; + assign s_axi_rresp = axil_rresp; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/common/ml605/pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.mpd b/projects/common/ml605/pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.mpd new file mode 100644 index 000000000..13d8ad886 --- /dev/null +++ b/projects/common/ml605/pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.mpd @@ -0,0 +1,174 @@ +################################################################### +## +## Name : axi_dma +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN axi_dma + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = MIXED +OPTION IP_GROUP = MICROBLAZE:USER +OPTION DESC = axi_dma +OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT) + +## Bus Interfaces +BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE +BUS_INTERFACE BUS = M_DEST_AXI, BUS_STD = AXI, BUS_TYPE = MASTER, ISVALID = (C_DMA_TYPE_DEST == 0) +BUS_INTERFACE BUS = M_SRC_AXI, BUS_STD = AXI, BUS_TYPE = MASTER, ISVALID = (C_DMA_TYPE_SRC == 0) + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_S_AXI_MIN_SIZE = 0x0000ffff, DT = std_logic_vector, BUS = S_AXI +PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI, MIN_SIZE = 0x100 +PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI +PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI + +PARAMETER C_M_DEST_AXI_PROTOCOL = AXI3, DT = STRING, BUS = M_DEST_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL +PARAMETER C_M_DEST_AXI_DATA_WIDTH = 64, DT = INTEGER, BUS = M_DEST_AXI, TYPE = NON_HDL +PARAMETER C_M_DEST_AXI_SUPPORTS_NARROW_BURST = 0, DT = INTEGER, TYPE = NON_HDL, BUS = M_DEST_AXI, ASSIGNMENT = CONSTANT +PARAMETER C_INTERCONNECT_M_DEST_AXI_WRITE_ISSUING = 8, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_DEST_AXI +PARAMETER C_M_DEST_AXI_SUPPORTS_READ = 0, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_DEST_AXI +PARAMETER C_M_DEST_AXI_SUPPORTS_WRITE = 1, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_DEST_AXI +PARAMETER C_M_DEST_AXI_THREAD_ID_WIDTH = 0, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_DEST_AXI +PARAMETER C_M_DEST_AXI_SUPPORTS_THREADS = 0, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_DEST_AXI + +PARAMETER C_M_SRC_AXI_PROTOCOL = AXI3, DT = STRING, BUS = M_SRC_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL +PARAMETER C_M_SRC_AXI_DATA_WIDTH = 64, DT = INTEGER, BUS = M_SRC_AXI, TYPE = NON_HDL +PARAMETER C_M_SRC_AXI_SUPPORTS_NARROW_BURST = 0, DT = INTEGER, TYPE = NON_HDL, BUS = M_SRC_AXI, ASSIGNMENT = CONSTANT +PARAMETER C_INTERCONNECT_M_SRC_AXI_READ_ISSUING = 8, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_SRC_AXI +PARAMETER C_M_SRC_AXI_SUPPORTS_READ = 1, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_SRC_AXI +PARAMETER C_M_SRC_AXI_SUPPORTS_WRITE = 0, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_SRC_AXI +PARAMETER C_M_SRC_AXI_THREAD_ID_WIDTH = 0, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_SRC_AXI +PARAMETER C_M_SRC_AXI_SUPPORTS_THREADS = 0, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_SRC_AXI + +## 0 = AXI MM, 1 = AXI STREAM, 2 = FIFO +PARAMETER C_DMA_TYPE_DEST = 0, DT = INTEGER, RANGE = (0,1,2), VALUES = (0 = Memory mapped AXI, 1 = Streaming AXI, 2 = FIFO), DESC = DMA data destination interface type +PARAMETER C_DMA_TYPE_SRC = 0, DT = INTEGER, RANGE = (0,1,2), VALUES = (0 = Memory mapped AXI, 1 = Streaming AXI, 2 = FIFO), DESC = DMA data source interface type +PARAMETER C_DMA_DATA_WIDTH_DEST = 64, DT = INTEGER, RANGE = (8,16,32,64,128,256,512), DESC = DMA data destination bus width +PARAMETER C_DMA_DATA_WIDTH_SRC = 64, DT = INTEGER, RANGE = (8,16,32,64,128,256,512), DESC = DMA data source bus width + +## AXI Passthrough +PORT axil_aclk = "", DIR = O, SIGIS = CLK +PORT axil_aresetn = "", DIR = O, SIGIS = RST +PORT axil_awvalid = "", DIR = O +PORT axil_awaddr = "", DIR = O, VEC = [31:0] +PORT axil_awready = "", DIR = I +PORT axil_wvalid = "", DIR = O +PORT axil_wdata = "", DIR = O, VEC = [31:0] +PORT axil_wstrb = "", DIR = O, VEC = [3:0] +PORT axil_wready = "", DIR = I +PORT axil_bvalid = "", DIR = I +PORT axil_bresp = "", DIR = I, VEC = [1:0] +PORT axil_bready = "", DIR = O +PORT axil_arvalid = "", DIR = O +PORT axil_araddr = "", DIR = O, VEC = [31:0] +PORT axil_arready = "", DIR = I +PORT axil_rvalid = "", DIR = I +PORT axil_rdata = "", DIR = I, VEC = [31:0] +PORT axil_rresp = "", DIR = I, VEC = [1:0] +PORT axil_rready = "", DIR = O + +## AXI Interface +PORT s_axi_aclk = ACLK, DIR = I, SIGIS = CLK, BUS = S_AXI +PORT s_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI +PORT s_axi_awvalid = AWVALID, DIR = I, BUS = S_AXI +PORT s_axi_awaddr = AWADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_awready = AWREADY, DIR = O, BUS = S_AXI +PORT s_axi_wvalid = WVALID, DIR = I, BUS = S_AXI +PORT s_axi_wdata = WDATA, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_wstrb = WSTRB, DIR = I, VEC = [3:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_wready = WREADY, DIR = O, BUS = S_AXI +PORT s_axi_bvalid = BVALID, DIR = O, BUS = S_AXI +PORT s_axi_bresp = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI +PORT s_axi_bready = BREADY, DIR = I, BUS = S_AXI +PORT s_axi_arvalid = ARVALID, DIR = I, BUS = S_AXI +PORT s_axi_araddr = ARADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_arready = ARREADY, DIR = O, BUS = S_AXI +PORT s_axi_rvalid = RVALID, DIR = O, BUS = S_AXI +PORT s_axi_rdata = RDATA, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI +PORT s_axi_rresp = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI +PORT s_axi_rready = RREADY, DIR = I, BUS = S_AXI + +## AXIM (dest) Passthrough +PORT axim_d_aclk = "", DIR = O, SIGIS = CLK +PORT axim_d_aresetn = "", DIR = O, SIGIS = RST +PORT axim_d_awaddr = "", DIR = I, VEC = [31:0], ENDIAN = LITTLE +PORT axim_d_awlen = "", DIR = I, VEC = [7:0] +PORT axim_d_awsize = "", DIR = I, VEC = [2:0] +PORT axim_d_awburst = "", DIR = I, VEC = [1:0] +PORT axim_d_awprot = "", DIR = I, VEC = [2:0] +PORT axim_d_awcache = "", DIR = I, VEC = [3:0] +PORT axim_d_awvalid = "", DIR = I +PORT axim_d_awready = "", DIR = O +PORT axim_d_wdata = "", DIR = I, VEC = [C_DMA_DATA_WIDTH_DEST-1:0], ENDIAN = LITTLE +PORT axim_d_wstrb = "", DIR = I, VEC = [7:0], ENDIAN = LITTLE +PORT axim_d_wready = "", DIR = O +PORT axim_d_wvalid = "", DIR = I +PORT axim_d_wlast = "", DIR = I +PORT axim_d_bready = "", DIR = I +PORT axim_d_bresp = "", DIR = O, VEC = [1:0] +PORT axim_d_bvalid = "", DIR = O + +## AXIM (dest) Interface +PORT m_dest_axi_aclk = ACLK, DIR = I, SIGIS = CLK, BUS = M_DEST_AXI +PORT m_dest_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = M_DEST_AXI +PORT m_dest_axi_awaddr = AWADDR, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = M_DEST_AXI +PORT m_dest_axi_awlen = AWLEN, DIR = O, VEC = [7:0], BUS = M_DEST_AXI +PORT m_dest_axi_awsize = AWSIZE, DIR = O, VEC = [2:0], BUS = M_DEST_AXI +PORT m_dest_axi_awburst = AWBURST, DIR = O, VEC = [1:0], BUS = M_DEST_AXI +PORT m_dest_axi_awprot = AWPROT, DIR = O, VEC = [2:0], BUS = M_DEST_AXI +PORT m_dest_axi_awcache = AWCACHE, DIR = O, VEC = [3:0], BUS = M_DEST_AXI +PORT m_dest_axi_awvalid = AWVALID, DIR = O, BUS = M_DEST_AXI +PORT m_dest_axi_awready = AWREADY, DIR = I, BUS = M_DEST_AXI +PORT m_dest_axi_wdata = WDATA, DIR = O, VEC = [C_DMA_DATA_WIDTH_DEST-1:0], ENDIAN = LITTLE, BUS = M_DEST_AXI +PORT m_dest_axi_wstrb = WSTRB, DIR = O, VEC = [7:0], ENDIAN = LITTLE, BUS = M_DEST_AXI +PORT m_dest_axi_wready = WREADY, DIR = I, BUS = M_DEST_AXI +PORT m_dest_axi_wvalid = WVALID, DIR = O, BUS = M_DEST_AXI +PORT m_dest_axi_wlast = WLAST, DIR = O, BUS = M_DEST_AXI +PORT m_dest_axi_bready = BREADY, DIR = O, BUS = M_DEST_AXI +PORT m_dest_axi_bresp = BRESP, DIR = I, VEC = [1:0], BUS = M_DEST_AXI +PORT m_dest_axi_bvalid = BVALID, DIR = I, BUS = M_DEST_AXI + +## AXIM (src) Passthrough +PORT axim_s_aclk = "", DIR = O, SIGIS = CLK +PORT axim_s_aresetn = "", DIR = O, SIGIS = RST +PORT axim_s_araddr = "", DIR = I, VEC = [31:0], ENDIAN = LITTLE +PORT axim_s_arlen = "", DIR = I, VEC = [7:0] +PORT axim_s_arsize = "", DIR = I, VEC = [2:0] +PORT axim_s_arburst = "", DIR = I, VEC = [1:0] +PORT axim_s_arprot = "", DIR = I, VEC = [2:0] +PORT axim_s_arcache = "", DIR = I, VEC = [3:0] +PORT axim_s_arready = "", DIR = O +PORT axim_s_arvalid = "", DIR = I +PORT axim_s_rresp = "", DIR = O, VEC = [1:0] +PORT axim_s_rdata = "", DIR = O, VEC = [C_DMA_DATA_WIDTH_SRC-1:0], ENDIAN = LITTLE +PORT axim_s_rready = "", DIR = I +PORT axim_s_rvalid = "", DIR = O + +## AXIM (src) Interface +PORT m_src_axi_aclk = ACLK, DIR = I, SIGIS = CLK, BUS = M_SRC_AXI +PORT m_src_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = M_SRC_AXI +PORT m_src_axi_araddr = ARADDR, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = M_SRC_AXI +PORT m_src_axi_arlen = ARLEN, DIR = O, VEC = [7:0], BUS = M_SRC_AXI +PORT m_src_axi_arsize = ARSIZE, DIR = O, VEC = [2:0], BUS = M_SRC_AXI +PORT m_src_axi_arburst = ARBURST, DIR = O, VEC = [1:0], BUS = M_SRC_AXI +PORT m_src_axi_arprot = ARPROT, DIR = O, VEC = [2:0], BUS = M_SRC_AXI +PORT m_src_axi_arcache = ARCACHE, DIR = O, VEC = [3:0], BUS = M_SRC_AXI +PORT m_src_axi_arready = ARREADY, DIR = I, BUS = M_SRC_AXI +PORT m_src_axi_arvalid = ARVALID, DIR = O, BUS = M_SRC_AXI +PORT m_src_axi_rresp = RRESP, DIR = I, VEC = [1:0], BUS = M_SRC_AXI +PORT m_src_axi_rdata = RDATA, DIR = I, VEC = [C_DMA_DATA_WIDTH_SRC-1:0], ENDIAN = LITTLE, BUS = M_SRC_AXI +PORT m_src_axi_rready = RREADY, DIR = O, BUS = M_SRC_AXI +PORT m_src_axi_rvalid = RVALID, DIR = I, BUS = M_SRC_AXI + +## Interrupt +PORT irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH + +## Interrupt Passthrough +PORT axim_irq = "", DIR = I + +END diff --git a/projects/common/ml605/pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.pao b/projects/common/ml605/pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.pao new file mode 100644 index 000000000..578b5b75c --- /dev/null +++ b/projects/common/ml605/pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.pao @@ -0,0 +1,8 @@ +############################################################################## +## Filename: pcores/axi_dma_v1_00_a/data/axi_dma_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Fri Aug 26 11:12:50 2011 (by Create and Import Peripheral Wizard) +############################################################################## + +lib axi_dma_v1_00_a axi_dma verilog + diff --git a/projects/common/ml605/pcores/axi_dma_v1_00_a/hdl/verilog/axi_dma.v b/projects/common/ml605/pcores/axi_dma_v1_00_a/hdl/verilog/axi_dma.v new file mode 100755 index 000000000..04b475d6e --- /dev/null +++ b/projects/common/ml605/pcores/axi_dma_v1_00_a/hdl/verilog/axi_dma.v @@ -0,0 +1,366 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dma ( + + // external interface + + axil_aclk, + axil_aresetn, + axil_awvalid, + axil_awaddr, + axil_awready, + axil_wvalid, + axil_wdata, + axil_wstrb, + axil_wready, + axil_bvalid, + axil_bresp, + axil_bready, + axil_arvalid, + axil_araddr, + axil_arready, + axil_rvalid, + axil_rdata, + axil_rresp, + axil_rready, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready, + + // AXIM (dest) interface + + axim_d_aclk, + axim_d_aresetn, + axim_d_awaddr, + axim_d_awlen, + axim_d_awsize, + axim_d_awburst, + axim_d_awprot, + axim_d_awcache, + axim_d_awvalid, + axim_d_awready, + axim_d_wdata, + axim_d_wstrb, + axim_d_wready, + axim_d_wvalid, + axim_d_wlast, + axim_d_bvalid, + axim_d_bresp, + axim_d_bready, + + m_dest_axi_aclk, + m_dest_axi_aresetn, + m_dest_axi_awaddr, + m_dest_axi_awlen, + m_dest_axi_awsize, + m_dest_axi_awburst, + m_dest_axi_awprot, + m_dest_axi_awcache, + m_dest_axi_awvalid, + m_dest_axi_awready, + m_dest_axi_wdata, + m_dest_axi_wstrb, + m_dest_axi_wready, + m_dest_axi_wvalid, + m_dest_axi_wlast, + m_dest_axi_bvalid, + m_dest_axi_bresp, + m_dest_axi_bready, + + // AXIM (src) interface + + axim_s_aclk, + axim_s_aresetn, + axim_s_arready, + axim_s_arvalid, + axim_s_araddr, + axim_s_arlen, + axim_s_arsize, + axim_s_arburst, + axim_s_arprot, + axim_s_arcache, + axim_s_rdata, + axim_s_rready, + axim_s_rvalid, + axim_s_rresp, + + m_src_axi_aclk, + m_src_axi_aresetn, + m_src_axi_arready, + m_src_axi_arvalid, + m_src_axi_araddr, + m_src_axi_arlen, + m_src_axi_arsize, + m_src_axi_arburst, + m_src_axi_arprot, + m_src_axi_arcache, + m_src_axi_rdata, + m_src_axi_rready, + m_src_axi_rvalid, + m_src_axi_rresp, + + // Interrupt + + irq, + axim_irq); + + // parameters + + parameter C_S_AXI_MIN_SIZE = 32'hffff; + parameter C_BASEADDR = 32'hffffffff; + parameter C_HIGHADDR = 32'h00000000; + parameter C_DMA_TYPE_DEST = 0; + parameter C_DMA_TYPE_SRC = 0; + parameter C_DMA_DATA_WIDTH_DEST = 64; + parameter C_DMA_DATA_WIDTH_SRC = 64; + + // external interface + + output axil_aclk; + output axil_aresetn; + output axil_awvalid; + output [31:0] axil_awaddr; + input axil_awready; + output axil_wvalid; + output [31:0] axil_wdata; + output [ 3:0] axil_wstrb; + input axil_wready; + input axil_bvalid; + input [ 1:0] axil_bresp; + output axil_bready; + output axil_arvalid; + output [31:0] axil_araddr; + input axil_arready; + input axil_rvalid; + input [31:0] axil_rdata; + input [ 1:0] axil_rresp; + output axil_rready; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // AXIM (dest) interface + + output axim_d_aclk; + output axim_d_aresetn; + input [31:0] axim_d_awaddr; + input [ 7:0] axim_d_awlen; + input [ 2:0] axim_d_awsize; + input [ 1:0] axim_d_awburst; + input [ 2:0] axim_d_awprot; + input [ 3:0] axim_d_awcache; + input axim_d_awvalid; + output axim_d_awready; + input [C_DMA_DATA_WIDTH_DEST-1:0] axim_d_wdata; + input [(C_DMA_DATA_WIDTH_DEST/8)-1:0] axim_d_wstrb; + output axim_d_wready; + input axim_d_wvalid; + input axim_d_wlast; + output axim_d_bvalid; + output [ 1:0] axim_d_bresp; + input axim_d_bready; + + input m_dest_axi_aclk; + input m_dest_axi_aresetn; + output [31:0] m_dest_axi_awaddr; + output [ 7:0] m_dest_axi_awlen; + output [ 2:0] m_dest_axi_awsize; + output [ 1:0] m_dest_axi_awburst; + output [ 2:0] m_dest_axi_awprot; + output [ 3:0] m_dest_axi_awcache; + output m_dest_axi_awvalid; + input m_dest_axi_awready; + output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata; + output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb; + input m_dest_axi_wready; + output m_dest_axi_wvalid; + output m_dest_axi_wlast; + input m_dest_axi_bvalid; + input [ 1:0] m_dest_axi_bresp; + output m_dest_axi_bready; + + // AXIM (src) interface + + output axim_s_aclk; + output axim_s_aresetn; + output axim_s_arready; + input axim_s_arvalid; + input [31:0] axim_s_araddr; + input [ 7:0] axim_s_arlen; + input [ 2:0] axim_s_arsize; + input [ 1:0] axim_s_arburst; + input [ 2:0] axim_s_arprot; + input [ 3:0] axim_s_arcache; + output [C_DMA_DATA_WIDTH_SRC-1:0] axim_s_rdata; + input axim_s_rready; + output axim_s_rvalid; + output [ 1:0] axim_s_rresp; + + input m_src_axi_aclk; + input m_src_axi_aresetn; + input m_src_axi_arready; + output m_src_axi_arvalid; + output [31:0] m_src_axi_araddr; + output [ 7:0] m_src_axi_arlen; + output [ 2:0] m_src_axi_arsize; + output [ 1:0] m_src_axi_arburst; + output [ 2:0] m_src_axi_arprot; + output [ 3:0] m_src_axi_arcache; + input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata; + output m_src_axi_rready; + input m_src_axi_rvalid; + input [ 1:0] m_src_axi_rresp; + + // Interrupt + + input axim_irq; + output irq; + + // assignments (axil) + + assign axil_aclk = s_axi_aclk; + assign axil_aresetn = s_axi_aresetn; + assign axil_awvalid = s_axi_awvalid; + assign axil_awaddr = s_axi_awaddr; + assign axil_wvalid = s_axi_wvalid; + assign axil_wdata = s_axi_wdata; + assign axil_wstrb = s_axi_wstrb; + assign axil_bready = s_axi_bready; + assign axil_arvalid = s_axi_arvalid; + assign axil_araddr = s_axi_araddr; + assign axil_rready = s_axi_rready; + + assign s_axi_awready = axil_awready; + assign s_axi_wready = axil_wready; + assign s_axi_bvalid = axil_bvalid; + assign s_axi_bresp = axil_bresp; + assign s_axi_arready = axil_arready; + assign s_axi_rvalid = axil_rvalid; + assign s_axi_rdata = axil_rdata; + assign s_axi_rresp = axil_rresp; + + // assignments (axim-dest) + + assign axim_d_aclk = m_dest_axi_aclk; + assign axim_d_aresetn = m_dest_axi_aresetn; + assign axim_d_awready = m_dest_axi_awready; + assign axim_d_wready = m_dest_axi_wready; + assign axim_d_bresp = m_dest_axi_bresp; + assign axim_d_bvalid = m_dest_axi_bvalid; + + assign m_dest_axi_awaddr = axim_d_awaddr; + assign m_dest_axi_awlen = axim_d_awlen; + assign m_dest_axi_awsize = axim_d_awsize; + assign m_dest_axi_awburst = axim_d_awburst; + assign m_dest_axi_awprot = axim_d_awprot; + assign m_dest_axi_awcache = axim_d_awcache; + assign m_dest_axi_awvalid = axim_d_awvalid; + assign m_dest_axi_wdata = axim_d_wdata; + assign m_dest_axi_wstrb = axim_d_wstrb; + assign m_dest_axi_wvalid = axim_d_wvalid; + assign m_dest_axi_wlast = axim_d_wlast; + assign m_dest_axi_bready = axim_d_bready; + + // assignments (axim-src) + + assign axim_s_aclk = m_src_axi_aclk; + assign axim_s_aresetn = m_src_axi_aresetn; + assign axim_s_arready = m_src_axi_arready; + assign axim_s_rresp = m_src_axi_rresp; + assign axim_s_rdata = m_src_axi_rdata; + assign axim_s_rvalid = m_src_axi_rvalid; + + assign m_src_axi_araddr = axim_s_araddr; + assign m_src_axi_arlen = axim_s_arlen; + assign m_src_axi_arsize = axim_s_arsize; + assign m_src_axi_arburst = axim_s_arburst; + assign m_src_axi_arprot = axim_s_arprot; + assign m_src_axi_arcache = axim_s_arcache; + assign m_src_axi_arvalid = axim_s_arvalid; + assign m_src_axi_rready = axim_s_rready; + + // assignments (irq) + + assign irq = axim_irq; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/common/ml605/system.mhs b/projects/common/ml605/system.mhs new file mode 100755 index 000000000..d9d56e612 --- /dev/null +++ b/projects/common/ml605/system.mhs @@ -0,0 +1,678 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.61xd +# Thu Aug 25 15:18:16 2011 +# Target Board: xilinx.com ml605 Rev D +# Family: virtex6 +# Device: xc6vlx240t +# Package: ff1156 +# Speed Grade: -1 +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT sys_rst = sys_rst, DIR = I, SIGIS = RST, RST_POLARITY = 1 + PORT sys_clk_p = sys_clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 + PORT sys_clk_n = sys_clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 + PORT ddr3_a13 = net_gnd, DIR = O + PORT ddr3_we_n = ddr3_we_n, DIR = O + PORT ddr3_ras_n = ddr3_ras_n, DIR = O + PORT ddr3_odt = ddr3_odt, DIR = O + PORT ddr3_dqs_n = ddr3_dqs_n, DIR = IO, VEC = [7:0] + PORT ddr3_dqs = ddr3_dqs, DIR = IO, VEC = [7:0] + PORT ddr3_dq = ddr3_dq, DIR = IO, VEC = [63:0] + PORT ddr3_dm = ddr3_dm, DIR = O, VEC = [7:0] + PORT ddr3_rst = ddr3_rst, DIR = O + PORT ddr3_cs_n = ddr3_cs_n, DIR = O + PORT ddr3_clk_n = ddr3_clk_n, DIR = O + PORT ddr3_clk = ddr3_clk, DIR = O + PORT ddr3_cke = ddr3_cke, DIR = O + PORT ddr3_cas_n = ddr3_cas_n, DIR = O + PORT ddr3_ba = ddr3_ba, DIR = O, VEC = [2:0] + PORT ddr3_addr = ddr3_addr, DIR = O, VEC = [12:0] + PORT uart_tx = uart_tx, DIR = O + PORT uart_rx = uart_rx, DIR = I + PORT phy_rstn = phy_rstn, DIR = O + PORT phy_mdc = phy_mdc, DIR = O + PORT phy_mdio = phy_mdio, DIR = IO + PORT phy_crs = phy_crs, DIR = I + PORT phy_col = phy_col, DIR = I + PORT phy_tx_clk = phy_tx_clk, DIR = I + PORT phy_tx_en = phy_tx_en, DIR = O + PORT phy_tx_d = phy_tx_d, DIR = O, VEC = [3:0] + PORT phy_rx_clk = phy_rx_clk, DIR = I + PORT phy_rx_dv = phy_rx_dv, DIR = I + PORT phy_rx_d = phy_rx_d, DIR = I, VEC = [3:0] + PORT phy_rx_er = phy_rx_er, DIR = I + PORT iic_scl = iic_scl, DIR = IO + PORT iic_sda = iic_sda, DIR = IO + PORT lcd = lcd, DIR = IO, VEC = [6:0] + PORT sw = sw, DIR = IO, VEC = [12:0] + PORT led = led, DIR = IO, VEC = [12:0] + PORT axi_gpio_fmc_i0 = axi_gpio_fmc_i0, DIR = I, VEC = [31:0] + PORT axi_gpio_fmc_o0 = axi_gpio_fmc_o0, DIR = O, VEC = [31:0] + PORT axi_gpio_fmc_t0 = axi_gpio_fmc_t0, DIR = O, VEC = [31:0] + PORT axi_gpio_fmc_i1 = axi_gpio_fmc_i1, DIR = I, VEC = [31:0] + PORT axi_gpio_fmc_o1 = axi_gpio_fmc_o1, DIR = O, VEC = [31:0] + PORT axi_gpio_fmc_t1 = axi_gpio_fmc_t1, DIR = O, VEC = [31:0] + PORT axi_spi_fmc_sel = axi_spi_fmc_sel, DIR = I + PORT axi_spi_fmc_csn_i = axi_spi_fmc_csn_i, DIR = I, VEC = [7:0] + PORT axi_spi_fmc_csn_o = axi_spi_fmc_csn_o, DIR = O, VEC = [7:0] + PORT axi_spi_fmc_csn_t = axi_spi_fmc_csn_t, DIR = O + PORT axi_spi_fmc_clk_i = axi_spi_fmc_clk_i, DIR = I + PORT axi_spi_fmc_clk_o = axi_spi_fmc_clk_o, DIR = O + PORT axi_spi_fmc_clk_t = axi_spi_fmc_clk_t, DIR = O + PORT axi_spi_fmc_mosi_i = axi_spi_fmc_mosi_i, DIR = I + PORT axi_spi_fmc_mosi_o = axi_spi_fmc_mosi_o, DIR = O + PORT axi_spi_fmc_mosi_t = axi_spi_fmc_mosi_t, DIR = O + PORT axi_spi_fmc_miso_i = axi_spi_fmc_miso_i, DIR = I + PORT axi_spi_fmc_miso_o = axi_spi_fmc_miso_o, DIR = O + PORT axi_spi_fmc_miso_t = axi_spi_fmc_miso_t, DIR = O + PORT axi_dma_tx_axil_aclk = axi_dma_tx_axil_aclk, DIR = O, SIGIS = CLK + PORT axi_dma_tx_axil_aresetn = axi_dma_tx_axil_aresetn, DIR = O, SIGIS = RST + PORT axi_dma_tx_axil_awvalid = axi_dma_tx_axil_awvalid, DIR = O + PORT axi_dma_tx_axil_awaddr = axi_dma_tx_axil_awaddr, DIR = O, VEC = [31:0] + PORT axi_dma_tx_axil_awready = axi_dma_tx_axil_awready, DIR = I + PORT axi_dma_tx_axil_wvalid = axi_dma_tx_axil_wvalid, DIR = O + PORT axi_dma_tx_axil_wdata = axi_dma_tx_axil_wdata, DIR = O, VEC = [31:0] + PORT axi_dma_tx_axil_wstrb = axi_dma_tx_axil_wstrb, DIR = O, VEC = [3:0] + PORT axi_dma_tx_axil_wready = axi_dma_tx_axil_wready, DIR = I + PORT axi_dma_tx_axil_bvalid = axi_dma_tx_axil_bvalid, DIR = I + PORT axi_dma_tx_axil_bresp = axi_dma_tx_axil_bresp, DIR = I, VEC = [1:0] + PORT axi_dma_tx_axil_bready = axi_dma_tx_axil_bready, DIR = O + PORT axi_dma_tx_axil_arvalid = axi_dma_tx_axil_arvalid, DIR = O + PORT axi_dma_tx_axil_araddr = axi_dma_tx_axil_araddr, DIR = O, VEC = [31:0] + PORT axi_dma_tx_axil_arready = axi_dma_tx_axil_arready, DIR = I + PORT axi_dma_tx_axil_rvalid = axi_dma_tx_axil_rvalid, DIR = I + PORT axi_dma_tx_axil_rdata = axi_dma_tx_axil_rdata, DIR = I, VEC = [31:0] + PORT axi_dma_tx_axil_rresp = axi_dma_tx_axil_rresp, DIR = I, VEC = [1:0] + PORT axi_dma_tx_axil_rready = axi_dma_tx_axil_rready, DIR = O + PORT axi_dma_tx_axim_s_aclk = axi_dma_tx_axim_s_aclk, DIR = O, SIGIS = CLK + PORT axi_dma_tx_axim_s_aresetn = axi_dma_tx_axim_s_aresetn, DIR = O, SIGIS = RST + PORT axi_dma_tx_axim_s_araddr = axi_dma_tx_axim_s_araddr, DIR = I, VEC = [31:0] + PORT axi_dma_tx_axim_s_arlen = axi_dma_tx_axim_s_arlen, DIR = I, VEC = [7:0] + PORT axi_dma_tx_axim_s_arsize = axi_dma_tx_axim_s_arsize, DIR = I, VEC = [2:0] + PORT axi_dma_tx_axim_s_arburst = axi_dma_tx_axim_s_arburst, DIR = I, VEC = [1:0] + PORT axi_dma_tx_axim_s_arprot = axi_dma_tx_axim_s_arprot, DIR = I, VEC = [2:0] + PORT axi_dma_tx_axim_s_arcache = axi_dma_tx_axim_s_arcache, DIR = I, VEC = [3:0] + PORT axi_dma_tx_axim_s_arready = axi_dma_tx_axim_s_arready, DIR = O + PORT axi_dma_tx_axim_s_arvalid = axi_dma_tx_axim_s_arvalid, DIR = I + PORT axi_dma_tx_axim_s_rresp = axi_dma_tx_axim_s_rresp, DIR = O, VEC = [1:0] + PORT axi_dma_tx_axim_s_rdata = axi_dma_tx_axim_s_rdata, DIR = O, VEC = [63:0] + PORT axi_dma_tx_axim_s_rready = axi_dma_tx_axim_s_rready, DIR = I + PORT axi_dma_tx_axim_s_rvalid = axi_dma_tx_axim_s_rvalid, DIR = O + PORT axi_dma_tx_axim_irq = axi_dma_tx_axim_irq, DIR = I + PORT axi_dma_rx_axil_aclk = axi_dma_rx_axil_aclk, DIR = O, SIGIS = CLK + PORT axi_dma_rx_axil_aresetn = axi_dma_rx_axil_aresetn, DIR = O, SIGIS = RST + PORT axi_dma_rx_axil_awvalid = axi_dma_rx_axil_awvalid, DIR = O + PORT axi_dma_rx_axil_awaddr = axi_dma_rx_axil_awaddr, DIR = O, VEC = [31:0] + PORT axi_dma_rx_axil_awready = axi_dma_rx_axil_awready, DIR = I + PORT axi_dma_rx_axil_wvalid = axi_dma_rx_axil_wvalid, DIR = O + PORT axi_dma_rx_axil_wdata = axi_dma_rx_axil_wdata, DIR = O, VEC = [31:0] + PORT axi_dma_rx_axil_wstrb = axi_dma_rx_axil_wstrb, DIR = O, VEC = [3:0] + PORT axi_dma_rx_axil_wready = axi_dma_rx_axil_wready, DIR = I + PORT axi_dma_rx_axil_bvalid = axi_dma_rx_axil_bvalid, DIR = I + PORT axi_dma_rx_axil_bresp = axi_dma_rx_axil_bresp, DIR = I, VEC = [1:0] + PORT axi_dma_rx_axil_bready = axi_dma_rx_axil_bready, DIR = O + PORT axi_dma_rx_axil_arvalid = axi_dma_rx_axil_arvalid, DIR = O + PORT axi_dma_rx_axil_araddr = axi_dma_rx_axil_araddr, DIR = O, VEC = [31:0] + PORT axi_dma_rx_axil_arready = axi_dma_rx_axil_arready, DIR = I + PORT axi_dma_rx_axil_rvalid = axi_dma_rx_axil_rvalid, DIR = I + PORT axi_dma_rx_axil_rdata = axi_dma_rx_axil_rdata, DIR = I, VEC = [31:0] + PORT axi_dma_rx_axil_rresp = axi_dma_rx_axil_rresp, DIR = I, VEC = [1:0] + PORT axi_dma_rx_axil_rready = axi_dma_rx_axil_rready, DIR = O + PORT axi_dma_rx_axim_d_aclk = axi_dma_rx_axim_d_aclk, DIR = O, SIGIS = CLK + PORT axi_dma_rx_axim_d_aresetn = axi_dma_rx_axim_d_aresetn, DIR = O, SIGIS = RST + PORT axi_dma_rx_axim_d_awaddr = axi_dma_rx_axim_d_awaddr, DIR = I, VEC = [31:0] + PORT axi_dma_rx_axim_d_awlen = axi_dma_rx_axim_d_awlen, DIR = I, VEC = [7:0] + PORT axi_dma_rx_axim_d_awsize = axi_dma_rx_axim_d_awsize, DIR = I, VEC = [2:0] + PORT axi_dma_rx_axim_d_awburst = axi_dma_rx_axim_d_awburst, DIR = I, VEC = [1:0] + PORT axi_dma_rx_axim_d_awprot = axi_dma_rx_axim_d_awprot, DIR = I, VEC = [2:0] + PORT axi_dma_rx_axim_d_awcache = axi_dma_rx_axim_d_awcache, DIR = I, VEC = [3:0] + PORT axi_dma_rx_axim_d_awvalid = axi_dma_rx_axim_d_awvalid, DIR = I + PORT axi_dma_rx_axim_d_awready = axi_dma_rx_axim_d_awready, DIR = O + PORT axi_dma_rx_axim_d_wdata = axi_dma_rx_axim_d_wdata, DIR = I, VEC = [63:0] + PORT axi_dma_rx_axim_d_wstrb = axi_dma_rx_axim_d_wstrb, DIR = I, VEC = [7:0] + PORT axi_dma_rx_axim_d_wready = axi_dma_rx_axim_d_wready, DIR = O + PORT axi_dma_rx_axim_d_wvalid = axi_dma_rx_axim_d_wvalid, DIR = I + PORT axi_dma_rx_axim_d_wlast = axi_dma_rx_axim_d_wlast, DIR = I + PORT axi_dma_rx_axim_d_bready = axi_dma_rx_axim_d_bready, DIR = I + PORT axi_dma_rx_axim_d_bresp = axi_dma_rx_axim_d_bresp, DIR = O, VEC = [1:0] + PORT axi_dma_rx_axim_d_bvalid = axi_dma_rx_axim_d_bvalid, DIR = O + PORT axi_dma_rx_axim_irq = axi_dma_rx_axim_irq, DIR = I + PORT axi_dev_tx_axil_aclk = axi_dev_tx_axil_aclk, DIR = O, SIGIS = CLK + PORT axi_dev_tx_axil_aresetn = axi_dev_tx_axil_aresetn, DIR = O, SIGIS = RST + PORT axi_dev_tx_axil_awvalid = axi_dev_tx_axil_awvalid, DIR = O + PORT axi_dev_tx_axil_awaddr = axi_dev_tx_axil_awaddr, DIR = O, VEC = [31:0] + PORT axi_dev_tx_axil_awready = axi_dev_tx_axil_awready, DIR = I + PORT axi_dev_tx_axil_wvalid = axi_dev_tx_axil_wvalid, DIR = O + PORT axi_dev_tx_axil_wdata = axi_dev_tx_axil_wdata, DIR = O, VEC = [31:0] + PORT axi_dev_tx_axil_wstrb = axi_dev_tx_axil_wstrb, DIR = O, VEC = [3:0] + PORT axi_dev_tx_axil_wready = axi_dev_tx_axil_wready, DIR = I + PORT axi_dev_tx_axil_bvalid = axi_dev_tx_axil_bvalid, DIR = I + PORT axi_dev_tx_axil_bresp = axi_dev_tx_axil_bresp, DIR = I, VEC = [1:0] + PORT axi_dev_tx_axil_bready = axi_dev_tx_axil_bready, DIR = O + PORT axi_dev_tx_axil_arvalid = axi_dev_tx_axil_arvalid, DIR = O + PORT axi_dev_tx_axil_araddr = axi_dev_tx_axil_araddr, DIR = O, VEC = [31:0] + PORT axi_dev_tx_axil_arready = axi_dev_tx_axil_arready, DIR = I + PORT axi_dev_tx_axil_rvalid = axi_dev_tx_axil_rvalid, DIR = I + PORT axi_dev_tx_axil_rdata = axi_dev_tx_axil_rdata, DIR = I, VEC = [31:0] + PORT axi_dev_tx_axil_rresp = axi_dev_tx_axil_rresp, DIR = I, VEC = [1:0] + PORT axi_dev_tx_axil_rready = axi_dev_tx_axil_rready, DIR = O + PORT axi_dev_rx_axil_aclk = axi_dev_rx_axil_aclk, DIR = O, SIGIS = CLK + PORT axi_dev_rx_axil_aresetn = axi_dev_rx_axil_aresetn, DIR = O, SIGIS = RST + PORT axi_dev_rx_axil_awvalid = axi_dev_rx_axil_awvalid, DIR = O + PORT axi_dev_rx_axil_awaddr = axi_dev_rx_axil_awaddr, DIR = O, VEC = [31:0] + PORT axi_dev_rx_axil_awready = axi_dev_rx_axil_awready, DIR = I + PORT axi_dev_rx_axil_wvalid = axi_dev_rx_axil_wvalid, DIR = O + PORT axi_dev_rx_axil_wdata = axi_dev_rx_axil_wdata, DIR = O, VEC = [31:0] + PORT axi_dev_rx_axil_wstrb = axi_dev_rx_axil_wstrb, DIR = O, VEC = [3:0] + PORT axi_dev_rx_axil_wready = axi_dev_rx_axil_wready, DIR = I + PORT axi_dev_rx_axil_bvalid = axi_dev_rx_axil_bvalid, DIR = I + PORT axi_dev_rx_axil_bresp = axi_dev_rx_axil_bresp, DIR = I, VEC = [1:0] + PORT axi_dev_rx_axil_bready = axi_dev_rx_axil_bready, DIR = O + PORT axi_dev_rx_axil_arvalid = axi_dev_rx_axil_arvalid, DIR = O + PORT axi_dev_rx_axil_araddr = axi_dev_rx_axil_araddr, DIR = O, VEC = [31:0] + PORT axi_dev_rx_axil_arready = axi_dev_rx_axil_arready, DIR = I + PORT axi_dev_rx_axil_rvalid = axi_dev_rx_axil_rvalid, DIR = I + PORT axi_dev_rx_axil_rdata = axi_dev_rx_axil_rdata, DIR = I, VEC = [31:0] + PORT axi_dev_rx_axil_rresp = axi_dev_rx_axil_rresp, DIR = I, VEC = [1:0] + PORT axi_dev_rx_axil_rready = axi_dev_rx_axil_rready, DIR = O + PORT sys_200m_clk = sys_200m_clk, DIR = O, SIGIS = CLK + +BEGIN clock_generator + PARAMETER INSTANCE = sys_clkgen + PARAMETER HW_VER = 4.03.a + PARAMETER C_CLKIN_FREQ = 200000000 + PARAMETER C_CLKOUT0_FREQ = 100000000 + PARAMETER C_CLKOUT0_GROUP = MMCM0 + PARAMETER C_CLKOUT1_FREQ = 200000000 + PARAMETER C_CLKOUT1_GROUP = MMCM0 + PARAMETER C_CLKOUT2_FREQ = 400000000 + PARAMETER C_CLKOUT2_GROUP = MMCM0 + PARAMETER C_CLKOUT3_FREQ = 400000000 + PARAMETER C_CLKOUT3_GROUP = MMCM0 + PARAMETER C_CLKOUT3_BUF = FALSE + PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE + PARAMETER C_CLKOUT4_FREQ = 30000000 + PORT RST = sys_rst + PORT CLKIN = sys_clk + PORT LOCKED = sys_clkgen_locked + PORT CLKOUT0 = sys_100m_clk + PORT CLKOUT1 = sys_200m_clk + PORT CLKOUT2 = sys_400m_clk + PORT CLKOUT3 = sys_400m_nobuf_clk + PORT PSCLK = sys_200m_clk + PORT PSEN = psen + PORT PSINCDEC = psincdec + PORT PSDONE = psdone +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = sys_rstgen + PARAMETER HW_VER = 3.00.a + PARAMETER C_EXT_RESET_HIGH = 1 + PORT Ext_Reset_In = sys_rst + PORT Dcm_locked = sys_clkgen_locked + PORT Slowest_sync_clk = sys_100m_clk + PORT MB_Reset = sys_mb_rst + PORT MB_Debug_Sys_Rst = sys_mdm_rst + PORT BUS_STRUCT_RESET = sys_lmb_rst + PORT Interconnect_aresetn = sys_interconnect_rstn +END + +BEGIN microblaze + PARAMETER INSTANCE = sys_cpu + PARAMETER HW_VER = 8.50.c + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_BARREL = 1 + PARAMETER C_USE_FPU = 0 + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_ICACHE_BASEADDR = 0xc0000000 + PARAMETER C_ICACHE_HIGHADDR = 0xdfffffff + PARAMETER C_USE_ICACHE = 1 + PARAMETER C_CACHE_BYTE_SIZE = 16384 + PARAMETER C_ICACHE_ALWAYS_USED = 1 + PARAMETER C_DCACHE_BASEADDR = 0xc0000000 + PARAMETER C_DCACHE_HIGHADDR = 0xdfffffff + PARAMETER C_USE_DCACHE = 1 + PARAMETER C_DCACHE_BYTE_SIZE = 16384 + PARAMETER C_DCACHE_ALWAYS_USED = 1 + PARAMETER C_PVR = 2 + PARAMETER C_USE_MMU = 3 + PARAMETER C_MMU_ZONES = 2 + PARAMETER C_ICACHE_LINE_LEN = 8 + PARAMETER C_ICACHE_STREAMS = 1 + PARAMETER C_ICACHE_VICTIMS = 8 + PARAMETER C_DIV_ZERO_EXCEPTION = 1 + PARAMETER C_M_AXI_I_BUS_EXCEPTION = 1 + PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1 + PARAMETER C_ILL_OPCODE_EXCEPTION = 1 + PARAMETER C_OPCODE_0x0_ILLEGAL = 1 + PARAMETER C_UNALIGNED_EXCEPTIONS = 1 + PARAMETER C_USE_HW_MUL = 2 + PARAMETER C_USE_DIV = 1 + BUS_INTERFACE M_AXI_DP = sys_cpu_interconnect + BUS_INTERFACE M_AXI_DC = sys_mem_interconnect + BUS_INTERFACE M_AXI_IC = sys_mem_interconnect + BUS_INTERFACE DEBUG = mdm_debug + BUS_INTERFACE DLMB = sys_dlmb + BUS_INTERFACE ILMB = sys_ilmb + PORT MB_RESET = sys_mb_rst + PORT CLK = sys_100m_clk + PORT INTERRUPT = axi_intc_m_irq +END + +BEGIN mdm + PARAMETER INSTANCE = sys_debug + PARAMETER HW_VER = 2.10.a + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_UART = 1 + PARAMETER C_BASEADDR = 0x41400000 + PARAMETER C_HIGHADDR = 0x4140ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + BUS_INTERFACE MBDEBUG_0 = mdm_debug + PORT Debug_SYS_Rst = sys_mdm_rst + PORT S_AXI_ACLK = sys_100m_clk +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = sys_ilmb + PARAMETER HW_VER = 2.00.b + PORT SYS_RST = sys_lmb_rst + PORT LMB_CLK = sys_100m_clk +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = sys_imem_ctrl + PARAMETER HW_VER = 3.10.c + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0001ffff + BUS_INTERFACE SLMB = sys_ilmb + BUS_INTERFACE BRAM_PORT = sys_ilmb_bram +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = sys_dlmb + PARAMETER HW_VER = 2.00.b + PORT SYS_RST = sys_lmb_rst + PORT LMB_CLK = sys_100m_clk +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = sys_dmem_ctrl + PARAMETER HW_VER = 3.10.c + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0001ffff + BUS_INTERFACE SLMB = sys_dlmb + BUS_INTERFACE BRAM_PORT = sys_dlmb_bram +END + +BEGIN bram_block + PARAMETER INSTANCE = sys_int_mem + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = sys_ilmb_bram + BUS_INTERFACE PORTB = sys_dlmb_bram +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = sys_cpu_interconnect + PARAMETER HW_VER = 1.06.a + PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 + PORT INTERCONNECT_ARESETN = sys_interconnect_rstn + PORT INTERCONNECT_ACLK = sys_100m_clk +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = sys_mem_interconnect + PARAMETER HW_VER = 1.06.a + PARAMETER C_INTERCONNECT_DATA_WIDTH = 256 + PORT interconnect_aclk = sys_200m_clk + PORT INTERCONNECT_ARESETN = sys_interconnect_rstn +END + +BEGIN axi_v6_ddrx + PARAMETER INSTANCE = sys_ddr3_mem + PARAMETER HW_VER = 1.06.a + PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1 + PARAMETER C_INTERCONNECT_S_AXI_MASTERS = sys_cpu.M_AXI_DC & sys_cpu.M_AXI_IC & axi_dma_tx.M_SRC_AXI & axi_dma_rx.M_DEST_AXI + PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y8 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8 + PARAMETER C_S_AXI_DATA_WIDTH = 256 + PARAMETER C_RD_WR_ARB_ALGORITHM = RD_PRI_REG + PARAMETER C_S_AXI_BASEADDR = 0xc0000000 + PARAMETER C_S_AXI_HIGHADDR = 0xdfffffff + BUS_INTERFACE S_AXI = sys_mem_interconnect + PORT ddr_we_n = ddr3_we_n + PORT ddr_ras_n = ddr3_ras_n + PORT ddr_odt = ddr3_odt + PORT ddr_dqs_n = ddr3_dqs_n + PORT ddr_dqs_p = ddr3_dqs + PORT ddr_dq = ddr3_dq + PORT ddr_dm = ddr3_dm + PORT ddr_reset_n = ddr3_rst + PORT ddr_cs_n = ddr3_cs_n + PORT ddr_ck_n = ddr3_clk_n + PORT ddr_ck_p = ddr3_clk + PORT ddr_cke = ddr3_cke + PORT ddr_cas_n = ddr3_cas_n + PORT ddr_ba = ddr3_ba + PORT ddr_addr = ddr3_addr + PORT clk_rd_base = sys_400m_nobuf_clk + PORT clk_mem = sys_400m_clk + PORT clk = sys_200m_clk + PORT clk_ref = sys_200m_clk + PORT PD_PSEN = psen + PORT PD_PSINCDEC = psincdec + PORT PD_PSDONE = psdone +END + +BEGIN axi_intc + PARAMETER INSTANCE = axi_intc_m + PARAMETER HW_VER = 1.04.a + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT Irq = axi_intc_m_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT Intr = axi_uart_m_irq & axi_ethernet_m_irq & axi_timer_m_irq & axi_iic_main_irq & axi_gpio_lcd_irq & axi_gpio_bd_irq & axi_gpio_fmc_irq & axi_spi_fmc_irq & axi_dma_tx_irq & axi_dma_rx_irq +END + +BEGIN axi_uartlite + PARAMETER INSTANCE = axi_uart_m + PARAMETER HW_VER = 1.02.a + PARAMETER C_BAUDRATE = 115200 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_ODD_PARITY = 1 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT Interrupt = axi_uart_m_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT TX = uart_tx + PORT RX = uart_rx +END + +BEGIN axi_ethernetlite + PARAMETER INSTANCE = axi_ethernet_m + PARAMETER HW_VER = 1.01.b + PARAMETER C_BASEADDR = 0x40e00000 + PARAMETER C_HIGHADDR = 0x40e0ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT IP2INTC_Irpt = axi_ethernet_m_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT PHY_rst_n = phy_rstn + PORT PHY_MDC = phy_mdc + PORT PHY_MDIO = phy_mdio + PORT PHY_crs = phy_crs + PORT PHY_col = phy_col + PORT PHY_tx_clk = phy_tx_clk + PORT PHY_tx_en = phy_tx_en + PORT PHY_tx_data = phy_tx_d + PORT PHY_rx_clk = phy_rx_clk + PORT PHY_dv = phy_rx_dv + PORT PHY_rx_data = phy_rx_d + PORT PHY_rx_er = phy_rx_er +END + +BEGIN axi_timer + PARAMETER INSTANCE = axi_timer_m + PARAMETER HW_VER = 1.03.a + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT Interrupt = axi_timer_m_irq + PORT S_AXI_ACLK = sys_100m_clk +END + +BEGIN axi_iic + PARAMETER INSTANCE = axi_iic_main + PARAMETER HW_VER = 1.02.a + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_SCL_INERTIAL_DELAY = 5 + PARAMETER C_SDA_INERTIAL_DELAY = 5 + PARAMETER C_BASEADDR = 0x40800000 + PARAMETER C_HIGHADDR = 0x4080ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT IIC2INTC_Irpt = axi_iic_main_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT Scl = iic_scl + PORT Sda = iic_sda +END + +BEGIN axi_gpio + PARAMETER INSTANCE = axi_gpio_lcd + PARAMETER HW_VER = 1.01.b + PARAMETER C_GPIO_WIDTH = 7 + PARAMETER C_INTERRUPT_PRESENT = 1 + PARAMETER C_BASEADDR = 0x40040000 + PARAMETER C_HIGHADDR = 0x4004ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT IP2INTC_Irpt = axi_gpio_lcd_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT GPIO_IO = lcd +END + +BEGIN axi_gpio + PARAMETER INSTANCE = axi_gpio_bd + PARAMETER HW_VER = 1.01.b + PARAMETER C_IS_DUAL = 1 + PARAMETER C_GPIO_WIDTH = 13 + PARAMETER C_GPIO2_WIDTH = 13 + PARAMETER C_INTERRUPT_PRESENT = 1 + PARAMETER C_BASEADDR = 0x40020000 + PARAMETER C_HIGHADDR = 0x4002ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT IP2INTC_Irpt = axi_gpio_bd_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT GPIO_IO = sw + PORT GPIO2_IO = led +END + +BEGIN axi_gpio + PARAMETER INSTANCE = axi_gpio_fmc + PARAMETER HW_VER = 1.01.b + PARAMETER C_INTERRUPT_PRESENT = 1 + PARAMETER C_IS_DUAL = 1 + PARAMETER C_GPIO_WIDTH = 32 + PARAMETER C_GPIO2_WIDTH = 32 + PARAMETER C_BASEADDR = 0x40000000 + PARAMETER C_HIGHADDR = 0x4000ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT IP2INTC_Irpt = axi_gpio_fmc_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT GPIO_IO_I = axi_gpio_fmc_i0 + PORT GPIO_IO_O = axi_gpio_fmc_o0 + PORT GPIO_IO_T = axi_gpio_fmc_t0 + PORT GPIO2_IO_I = axi_gpio_fmc_i1 + PORT GPIO2_IO_O = axi_gpio_fmc_o1 + PORT GPIO2_IO_T = axi_gpio_fmc_t1 +END + +BEGIN axi_spi + PARAMETER INSTANCE = axi_spi_fmc + PARAMETER HW_VER = 1.02.a + PARAMETER C_NUM_SS_BITS = 8 + PARAMETER C_SCK_RATIO = 8 + PARAMETER C_BASEADDR = 0x40a00000 + PARAMETER C_HIGHADDR = 0x40a0ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT IP2INTC_Irpt = axi_spi_fmc_irq + PORT S_AXI_ACLK = sys_100m_clk + PORT SPISEL = axi_spi_fmc_sel + PORT SS_I = axi_spi_fmc_csn_i + PORT SS_O = axi_spi_fmc_csn_o + PORT SS_T = axi_spi_fmc_csn_t + PORT SCK_I = axi_spi_fmc_clk_i + PORT SCK_O = axi_spi_fmc_clk_o + PORT SCK_T = axi_spi_fmc_clk_t + PORT MOSI_I = axi_spi_fmc_mosi_i + PORT MOSI_O = axi_spi_fmc_mosi_o + PORT MOSI_T = axi_spi_fmc_mosi_t + PORT MISO_I = axi_spi_fmc_miso_i + PORT MISO_O = axi_spi_fmc_miso_o + PORT MISO_T = axi_spi_fmc_miso_t +END + +BEGIN axi_dma + PARAMETER INSTANCE = axi_dma_tx + PARAMETER HW_VER = 1.00.a + PARAMETER C_DMA_TYPE_DEST = 2 + PARAMETER C_BASEADDR = 0x7e240000 + PARAMETER C_HIGHADDR = 0x7e24ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + BUS_INTERFACE M_SRC_AXI = sys_mem_interconnect + PORT irq = axi_dma_tx_irq + PORT s_axi_aclk = sys_100m_clk + PORT m_dest_axi_aclk = sys_100m_clk + PORT m_src_axi_aclk = sys_100m_clk + PORT axil_aclk = axi_dma_tx_axil_aclk + PORT axil_aresetn = axi_dma_tx_axil_aresetn + PORT axil_awvalid = axi_dma_tx_axil_awvalid + PORT axil_awaddr = axi_dma_tx_axil_awaddr + PORT axil_awready = axi_dma_tx_axil_awready + PORT axil_wvalid = axi_dma_tx_axil_wvalid + PORT axil_wdata = axi_dma_tx_axil_wdata + PORT axil_wstrb = axi_dma_tx_axil_wstrb + PORT axil_wready = axi_dma_tx_axil_wready + PORT axil_bvalid = axi_dma_tx_axil_bvalid + PORT axil_bresp = axi_dma_tx_axil_bresp + PORT axil_bready = axi_dma_tx_axil_bready + PORT axil_arvalid = axi_dma_tx_axil_arvalid + PORT axil_araddr = axi_dma_tx_axil_araddr + PORT axil_arready = axi_dma_tx_axil_arready + PORT axil_rvalid = axi_dma_tx_axil_rvalid + PORT axil_rdata = axi_dma_tx_axil_rdata + PORT axil_rresp = axi_dma_tx_axil_rresp + PORT axil_rready = axi_dma_tx_axil_rready + PORT axim_s_aclk = axi_dma_tx_axim_s_aclk + PORT axim_s_aresetn = axi_dma_tx_axim_s_aresetn + PORT axim_s_araddr = axi_dma_tx_axim_s_araddr + PORT axim_s_arlen = axi_dma_tx_axim_s_arlen + PORT axim_s_arsize = axi_dma_tx_axim_s_arsize + PORT axim_s_arburst = axi_dma_tx_axim_s_arburst + PORT axim_s_arprot = axi_dma_tx_axim_s_arprot + PORT axim_s_arcache = axi_dma_tx_axim_s_arcache + PORT axim_s_arready = axi_dma_tx_axim_s_arready + PORT axim_s_arvalid = axi_dma_tx_axim_s_arvalid + PORT axim_s_rresp = axi_dma_tx_axim_s_rresp + PORT axim_s_rdata = axi_dma_tx_axim_s_rdata + PORT axim_s_rready = axi_dma_tx_axim_s_rready + PORT axim_s_rvalid = axi_dma_tx_axim_s_rvalid + PORT axim_irq = axi_dma_tx_axim_irq +END + +BEGIN axi_dma + PARAMETER INSTANCE = axi_dma_rx + PARAMETER HW_VER = 1.00.a + PARAMETER C_DMA_TYPE_SRC = 2 + PARAMETER C_BASEADDR = 0x7e220000 + PARAMETER C_HIGHADDR = 0x7e22ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + BUS_INTERFACE M_DEST_AXI = sys_mem_interconnect + PORT irq = axi_dma_rx_irq + PORT s_axi_aclk = sys_100m_clk + PORT m_dest_axi_aclk = sys_100m_clk + PORT m_src_axi_aclk = sys_100m_clk + PORT axil_aclk = axi_dma_rx_axil_aclk + PORT axil_aresetn = axi_dma_rx_axil_aresetn + PORT axil_awvalid = axi_dma_rx_axil_awvalid + PORT axil_awaddr = axi_dma_rx_axil_awaddr + PORT axil_awready = axi_dma_rx_axil_awready + PORT axil_wvalid = axi_dma_rx_axil_wvalid + PORT axil_wdata = axi_dma_rx_axil_wdata + PORT axil_wstrb = axi_dma_rx_axil_wstrb + PORT axil_wready = axi_dma_rx_axil_wready + PORT axil_bvalid = axi_dma_rx_axil_bvalid + PORT axil_bresp = axi_dma_rx_axil_bresp + PORT axil_bready = axi_dma_rx_axil_bready + PORT axil_arvalid = axi_dma_rx_axil_arvalid + PORT axil_araddr = axi_dma_rx_axil_araddr + PORT axil_arready = axi_dma_rx_axil_arready + PORT axil_rvalid = axi_dma_rx_axil_rvalid + PORT axil_rdata = axi_dma_rx_axil_rdata + PORT axil_rresp = axi_dma_rx_axil_rresp + PORT axil_rready = axi_dma_rx_axil_rready + PORT axim_d_aclk = axi_dma_rx_axim_d_aclk + PORT axim_d_aresetn = axi_dma_rx_axim_d_aresetn + PORT axim_d_awaddr = axi_dma_rx_axim_d_awaddr + PORT axim_d_awlen = axi_dma_rx_axim_d_awlen + PORT axim_d_awsize = axi_dma_rx_axim_d_awsize + PORT axim_d_awburst = axi_dma_rx_axim_d_awburst + PORT axim_d_awprot = axi_dma_rx_axim_d_awprot + PORT axim_d_awcache = axi_dma_rx_axim_d_awcache + PORT axim_d_awvalid = axi_dma_rx_axim_d_awvalid + PORT axim_d_awready = axi_dma_rx_axim_d_awready + PORT axim_d_wdata = axi_dma_rx_axim_d_wdata + PORT axim_d_wstrb = axi_dma_rx_axim_d_wstrb + PORT axim_d_wready = axi_dma_rx_axim_d_wready + PORT axim_d_wvalid = axi_dma_rx_axim_d_wvalid + PORT axim_d_wlast = axi_dma_rx_axim_d_wlast + PORT axim_d_bready = axi_dma_rx_axim_d_bready + PORT axim_d_bresp = axi_dma_rx_axim_d_bresp + PORT axim_d_bvalid = axi_dma_rx_axim_d_bvalid + PORT axim_irq = axi_dma_rx_axim_irq +END + +BEGIN axi_dev + PARAMETER INSTANCE = axi_dev_tx + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0x7c800000 + PARAMETER C_HIGHADDR = 0x7c80ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT s_axi_aclk = sys_100m_clk + PORT axil_aclk = axi_dev_tx_axil_aclk + PORT axil_aresetn = axi_dev_tx_axil_aresetn + PORT axil_awvalid = axi_dev_tx_axil_awvalid + PORT axil_awaddr = axi_dev_tx_axil_awaddr + PORT axil_awready = axi_dev_tx_axil_awready + PORT axil_wvalid = axi_dev_tx_axil_wvalid + PORT axil_wdata = axi_dev_tx_axil_wdata + PORT axil_wstrb = axi_dev_tx_axil_wstrb + PORT axil_wready = axi_dev_tx_axil_wready + PORT axil_bvalid = axi_dev_tx_axil_bvalid + PORT axil_bresp = axi_dev_tx_axil_bresp + PORT axil_bready = axi_dev_tx_axil_bready + PORT axil_arvalid = axi_dev_tx_axil_arvalid + PORT axil_araddr = axi_dev_tx_axil_araddr + PORT axil_arready = axi_dev_tx_axil_arready + PORT axil_rvalid = axi_dev_tx_axil_rvalid + PORT axil_rdata = axi_dev_tx_axil_rdata + PORT axil_rresp = axi_dev_tx_axil_rresp + PORT axil_rready = axi_dev_tx_axil_rready +END + +BEGIN axi_dev + PARAMETER INSTANCE = axi_dev_rx + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0x7e200000 + PARAMETER C_HIGHADDR = 0x7e20ffff + BUS_INTERFACE S_AXI = sys_cpu_interconnect + PORT s_axi_aclk = sys_100m_clk + PORT axil_aclk = axi_dev_rx_axil_aclk + PORT axil_aresetn = axi_dev_rx_axil_aresetn + PORT axil_awvalid = axi_dev_rx_axil_awvalid + PORT axil_awaddr = axi_dev_rx_axil_awaddr + PORT axil_awready = axi_dev_rx_axil_awready + PORT axil_wvalid = axi_dev_rx_axil_wvalid + PORT axil_wdata = axi_dev_rx_axil_wdata + PORT axil_wstrb = axi_dev_rx_axil_wstrb + PORT axil_wready = axi_dev_rx_axil_wready + PORT axil_bvalid = axi_dev_rx_axil_bvalid + PORT axil_bresp = axi_dev_rx_axil_bresp + PORT axil_bready = axi_dev_rx_axil_bready + PORT axil_arvalid = axi_dev_rx_axil_arvalid + PORT axil_araddr = axi_dev_rx_axil_araddr + PORT axil_arready = axi_dev_rx_axil_arready + PORT axil_rvalid = axi_dev_rx_axil_rvalid + PORT axil_rdata = axi_dev_rx_axil_rdata + PORT axil_rresp = axi_dev_rx_axil_rresp + PORT axil_rready = axi_dev_rx_axil_rready +END + diff --git a/projects/common/ml605/system.xmp b/projects/common/ml605/system.xmp new file mode 100755 index 000000000..2ecc29aee --- /dev/null +++ b/projects/common/ml605/system.xmp @@ -0,0 +1,33 @@ +#Please do not modify this file by hand +XmpVersion: 14.7 +VerMgmt: 14.7 +IntStyle: default +Flow: ise +MHS File: system.mhs +Architecture: virtex6 +Device: xc6vlx240t +Package: ff1156 +SpeedGrade: -1 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +GenSimTB: 0 +SdkExportBmmBit: 1 +SdkExportDir: SDK/SDK_Export +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: verilog +SimModel: BEHAVIORAL +ExternalMemSim: 0 +UcfFile: data/system.ucf +EnableParTimingError: 1 +ShowLicenseDialog: 1 +BInfo: ML605 +ICacheAddr: sys_ddr3_mem,C_S_AXI_BASEADDR +ICacheAddr: sys_ddr3_mem,C_S_AXI_CTRL_BASEADDR +DCacheAddr: sys_ddr3_mem,C_S_AXI_BASEADDR +DCacheAddr: sys_ddr3_mem,C_S_AXI_CTRL_BASEADDR +Processor: sys_cpu +ElfImp: +ElfSim: