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axi_dac_interpolate: Reduce AXI address width 

The axi_dac_interpolate does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-10 19:30:19 +02:00
parent b24f93a8bd
commit 53c8ece8f8
2 changed files with 19 additions and 24 deletions
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13
library/axi_dac_interpolate/axi_dac_interpolate.v
View File

@ -57,7 +57,7 @@ module axi_dac_interpolate(
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 6:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
@ -68,7 +68,7 @@ module axi_dac_interpolate(
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 6:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
@ -80,14 +80,14 @@ module axi_dac_interpolate(
wire up_clk;
wire up_rstn;
wire [13:0] up_waddr;
wire [ 4:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [13:0] up_raddr;
wire [ 4:0] up_raddr;
wire [31:0] interpolation_ratio_a;
wire [31:0] interpolation_ratio_b;
@ -153,7 +153,10 @@ module axi_dac_interpolate(
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi i_up_axi (
up_axi #(
.AXI_ADDRESS_WIDTH(7),
.ADDRESS_WIDTH(5)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

30
library/axi_dac_interpolate/axi_dac_interpolate_reg.v
View File

@ -52,19 +52,14 @@ module axi_dac_interpolate_reg(
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [ 4:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// internal registers
reg [31:0] up_version = 32'h00020000;
@ -76,9 +71,6 @@ module axi_dac_interpolate_reg(
reg [ 2:0] up_filter_mask_b = 3'h0;
reg [31:0] up_flags = 32'h0;
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
@ -89,23 +81,23 @@ module axi_dac_interpolate_reg(
up_filter_mask_b <= 'd0;
up_flags <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_interpolation_ratio_a <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_filter_mask_a <= up_wdata[2:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_interpolation_ratio_b <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_filter_mask_b <= up_wdata[2:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
up_flags <= up_wdata;
end
end
@ -118,8 +110,8 @@ module axi_dac_interpolate_reg(
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch;