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arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits 

This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
main
Adrian Costina 2017-07-28 10:10:27 +01:00
parent 289b170dfd
commit 53ca4f6ac9
1 changed files with 5 additions and 3 deletions
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8
projects/arradio/common/arradio_qsys.tcl
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@ -88,7 +88,7 @@ add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
add_instance axi_adc_dma axi_dmac
set_instance_parameter_value axi_adc_dma {ID} {0}
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128}
set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@ -152,6 +152,8 @@ ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
# mem interconnects
ad_dma_interconnect axi_adc_dma.m_dest_axi 0
ad_dma_interconnect axi_dac_dma.m_src_axi 1
set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 128 64}
ad_dma_interconnect axi_adc_dma.m_dest_axi 1
ad_dma_interconnect axi_dac_dma.m_src_axi 2