docs/regmap: Added ADI regmap_*.txt files (#1008)
PopPaul2021
GitHub
parent
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commit
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TITLE
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ADC Common (axi_ad*)
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ADC_COMMON
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0010
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REG_RSTN
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ADC Interface Control & Status
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ENDREG
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FIELD
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[2] 0x0
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CE_N
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RW
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Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of
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the module to control clock enables
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ENDFIELD
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FIELD
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[1] 0x0
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MMCM_RSTN
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RW
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MMCM reset only (required for DRP access).
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Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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FIELD
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[0] 0x0
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RSTN
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RW
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Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0011
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REG_CNTRL
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ADC Interface Control & Status
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ENDREG
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FIELD
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[16] 0x0
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SDR_DDR_N
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RW
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Interface type (1 represents SDR, 0 represents DDR)
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ENDFIELD
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FIELD
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[15] 0x0
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SYMB_OP
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RW
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Select symbol data format mode (0x1)
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ENDFIELD
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FIELD
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[14] 0x0
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SYMB_8_16B
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RW
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Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
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ENDFIELD
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FIELD
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[12:8] 0x0
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NUM_LANES[4:0]
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RW
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Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane).
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For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.
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ENDFIELD
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FIELD
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FIELD
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[3] 0x0
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SYNC
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RW
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Initialize synchronization between multiple ADCs
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ENDFIELD
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FIELD
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[2] 0x0
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R1_MODE
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RW
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Select number of RF channels 1 (0x1) or 2 (0x0).
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ENDFIELD
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FIELD
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[1] 0x0
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DDR_EDGESEL
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RW
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Select rising edge (0x0) or falling edge (0x1) for the first part
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of a sample (if applicable) followed by the successive edges for
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the remaining parts. This only controls how the sample is delineated
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from the incoming data post DDR registers.
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ENDFIELD
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FIELD
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[0] 0x0
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PIN_MODE
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RW
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Select interface pin mode to be clock multiplexed (0x1) or pin
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multiplexed (0x0). In clock multiplexed mode, samples are received
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on alternative clock edges. In pin multiplexed mode, samples are
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interleaved or grouped on the pins at the same clock edge.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0012
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REG_CNTRL_2
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ADC Interface Control & Status
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ENDREG
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FIELD
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[1] 0x0
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EXT_SYNC_ARM
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RW
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Setting this bit will arm the trigger mechanism sensitive to an external sync signal.
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Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances.
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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This bit self clears.
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ENDFIELD
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FIELD
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[2] 0x0
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EXT_SYNC_DISARM
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RW
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Setting this bit will disarm the trigger mechanism sensitive to an external sync signal.
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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This bit self clears.
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ENDFIELD
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FIELD
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[8] 0x0
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MANUAL_SYNC_REQUEST
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RW
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Setting this bit will issue an external sync event if it is hooked up inside the fabric.
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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This bit self clears.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0013
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REG_CNTRL_3
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ADC Interface Control & Status
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ENDREG
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FIELD
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[8] 0x0
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CRC_EN
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RW
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Setting this bit will enable the CRC generation.
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ENDFIELD
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FIELD
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[7:0] 0x00
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CUSTOM_CONTROL
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RW
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Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode
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, bit 1 - enables alternate bit polarity decode).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0015
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REG_CLK_FREQ
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ADC Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x0000
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CLK_FREQ[31:0]
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RO
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Interface clock frequency. This is relative to the processor clock and in many cases is
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100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
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clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
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is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
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the same as the interface clock- software must consider device specific implementation
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parameters to calculate the final sampling clock.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0016
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REG_CLK_RATIO
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ADC Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x0000
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CLK_RATIO[31:0]
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RO
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Interface clock ratio - as a factor actual received clock. This is implementation specific
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and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0017
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REG_STATUS
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ADC Interface Control & Status
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ENDREG
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FIELD
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[3] 0x0
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PN_ERR
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RO
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If set, indicates pn error in one or more channels.
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ENDFIELD
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FIELD
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[2] 0x0
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PN_OOS
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RO
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If set, indicates pn oos in one or more channels.
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ENDFIELD
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FIELD
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[1] 0x0
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OVER_RANGE
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RO
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If set, indicates over range in one or more channels.
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ENDFIELD
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FIELD
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[0] 0x0
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STATUS
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RO
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Interface status, if set indicates no errors. If not set, there
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are errors, software may try resetting the cores.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0018
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REG_DELAY_CNTRL
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ADC Interface Control & Status(''Deprecated from version 9'')
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ENDREG
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FIELD
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[17] 0x0
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DELAY_SEL
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RW
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Delay select, a 0x0 to 0x1 transition in this register initiates
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a delay access controlled by the registers below.
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ENDFIELD
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FIELD
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[16] 0x0
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DELAY_RWN
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RW
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Delay read (0x1) or write (0x0), the delay is accessed directly
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(no increment or decrement) with an address corresponding to each pin,
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and data corresponding to the total delay.
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ENDFIELD
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FIELD
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[15:8] 0x00
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DELAY_ADDRESS[7:0]
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RW
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Delay address, the range depends on the interface pins, data pins
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are usually at the lower range.
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ENDFIELD
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FIELD
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[4:0] 0x0
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DELAY_WDATA[4:0]
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RW
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Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0019
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REG_DELAY_STATUS
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ADC Interface Control & Status(''Deprecated from version 9'')
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ENDREG
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FIELD
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[9] 0x0
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DELAY_LOCKED
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RO
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Indicates delay locked (0x1) state. If this bit is read 0x0, delay control
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has failed to calibrate the elements.
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ENDFIELD
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FIELD
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[8] 0x0
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DELAY_STATUS
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RO
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If set, indicates busy status (access pending). The read data may not be
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valid if this bit is set.
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ENDFIELD
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FIELD
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[4:0] 0x0
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DELAY_RDATA[4:0]
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RO
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Delay read data, current delay value in the elements
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001A
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REG_SYNC_STATUS
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ADC Synchronization Status register
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ENDREG
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FIELD
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[0] 0x0
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ADC_SYNC
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RO
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ADC synchronization status. Will be set to 1 after the synchronization has been completed
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or while waiting for the synchronization signal in JESD204 systems.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001C
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REG_DRP_CNTRL
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ADC Interface Control & Status
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ENDREG
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FIELD
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[28] 0x0
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DRP_RWN
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RW
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DRP read (0x1) or write (0x0) select (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[27:16] 0x00
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DRP_ADDRESS[11:0]
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RW
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DRP address, designs that contain more than one DRP accessible primitives
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have selects based on the most significant bits (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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RESERVED[15:0]
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RO
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Reserved for backward compatibility.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001D
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REG_DRP_STATUS
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ADC Interface Control & Status
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ENDREG
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FIELD
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[17] 0x0
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DRP_LOCKED
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RO
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If set indicates that the DRP has been locked.
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ENDFIELD
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FIELD
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[16] 0x0
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DRP_STATUS
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RO
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If set indicates busy (access pending). The read data may not be valid if
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this bit is set (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x00
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RESERVED[15:0]
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RO
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Reserved for backward compatibility.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001E
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REG_DRP_WDATA
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ADC DRP Write Data
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ENDREG
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FIELD
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[15:0] 0x00
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DRP_WDATA[15:0]
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RW
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DRP write data (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001F
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REG_DRP_RDATA
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ADC DRP Read Data
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ENDREG
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FIELD
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[15:0] 0x00
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DRP_RDATA[15:0]
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RO
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DRP read data (does not include GTX lanes).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0022
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REG_UI_STATUS
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User Interface Status
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ENDREG
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FIELD
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[2] 0x0
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UI_OVF
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RW1C
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User Interface overflow. If set, indicates an overflow occurred during data transfer at
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the user interface (FIFO interface). Software must write a 0x1 to clear this register
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bit.
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ENDFIELD
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FIELD
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[1] 0x0
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UI_UNF
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RW1C
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User Interface underflow. If set, indicates an underflow occurred during data transfer at
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the user interface (FIFO interface). Software must write a 0x1 to clear this register
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bit.
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ENDFIELD
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FIELD
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[0] 0x0
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UI_RESERVED
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RW1C
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Reserved for backward compatibility.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0028
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REG_USR_CNTRL_1
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ADC Interface Control & Status
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ENDREG
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FIELD
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[7:0] 0x00
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USR_CHANMAX[7:0]
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RW
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This indicates the maximum number of inputs for the channel data multiplexers. User may add
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different processing modules post data capture as another input to this common multiplexer.
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NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0029
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REG_ADC_START_CODE
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ADC Synchronization start word
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ENDREG
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FIELD
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[31:0] 0x00000000
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ADC_START_CODE[31:0]
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RW
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This sets the startcode that is used by the ADCs for synchronization
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NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x002E
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REG_ADC_GPIO_IN
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ADC GPIO inputs
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ENDREG
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FIELD
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[31:0] 0x00000000
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ADC_GPIO_IN[31:0]
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RO
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This reads auxiliary GPI pins of the ADC core
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ENDFIELD
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REG
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0x002F
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REG_ADC_GPIO_OUT
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ADC GPIO outputs
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ENDREG
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FIELD
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[31:0] 0x00000000
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ADC_GPIO_OUT[31:0]
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RW
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This controls auxiliary GPO pins of the ADC core
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NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
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ENDFIELD
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REG
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0x0030
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REG_PPS_COUNTER
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PPS Counter register
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ENDREG
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FIELD
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[31:0] 0x00000000
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PPS_COUNTER[31:0]
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RO
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Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
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ENDFIELD
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REG
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0x0031
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REG_PPS_STATUS
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PPS Status register
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ENDREG
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FIELD
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[0] 0x0
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PPS_STATUS
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RO
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If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
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ENDFIELD
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############################################################################################
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############################################################################################
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TITLE
|
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ADC Channel (axi_ad*)
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ADC_CHANNEL
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0100
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REG_CHAN_CNTRL
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ADC Interface Control & Status
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ENDREG
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FIELD
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[11] 0x0
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ADC_LB_OWR
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RW
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If set, forces ADC_DATA_SEL to 1, enabling data loopback
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ENDFIELD
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FIELD
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[10] 0x0
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ADC_PN_SEL_OWR
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RW
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If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361)
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If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
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ENDFIELD
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FIELD
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[9] 0x0
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IQCOR_ENB
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RW
|
||||
if set, enables IQ correction or scale correction.
|
||||
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[8] 0x0
|
||||
DCFILT_ENB
|
||||
RW
|
||||
if set, enables DC filter (to disable DC offset, set offset value to 0x0).
|
||||
NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[6] 0x0
|
||||
FORMAT_SIGNEXT
|
||||
RW
|
||||
if set, enables sign extension (applicable only in 2's complement mode). The data is
|
||||
always sign extended to the nearest byte boundary.
|
||||
NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[5] 0x0
|
||||
FORMAT_TYPE
|
||||
RW
|
||||
Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming
|
||||
data type and is required by the post processing modules for any data conversion.
|
||||
NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4] 0x0
|
||||
FORMAT_ENABLE
|
||||
RW
|
||||
Enable data format conversion (see register bits above).
|
||||
NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
RESERVED
|
||||
RO
|
||||
Reserved for backward compatibility.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
RESERVED
|
||||
RO
|
||||
Reserved for backward compatibility.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
ADC_PN_TYPE_OWR
|
||||
RW
|
||||
If set, forces ADC_PN_SEL to 0x1, modified pn23
|
||||
If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
ENABLE
|
||||
RW
|
||||
If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals
|
||||
to the respective channel processing module. If a channel is part of a complex
|
||||
signal (I/Q), even channel is the master and the odd channel is the slave.
|
||||
Though a single control is used, both must be individually selected.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0101
|
||||
REG_CHAN_STATUS
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[12] 0x0
|
||||
CRC_ERR
|
||||
RW1C
|
||||
CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[11:4] 0x00
|
||||
STATUS_HEADER
|
||||
RO
|
||||
The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
PN_ERR
|
||||
RW1C
|
||||
PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared
|
||||
if OOS is set and is only indicates errors when OOS is cleared.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
PN_OOS
|
||||
RW1C
|
||||
PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns
|
||||
mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match
|
||||
the expected pattern.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
OVER_RANGE
|
||||
RW1C
|
||||
If set, indicates over range. Note that over range is independent of the data path,
|
||||
it indicates an over range over a data transfer period. Software must first clear
|
||||
this bit before initiating a transfer and monitor afterwards.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0104
|
||||
REG_CHAN_CNTRL_1
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
DCFILT_OFFSET[15:0]
|
||||
RW
|
||||
DC removal (if equipped) offset. This is a 2's complement number added to the incoming
|
||||
data to remove a known DC offset.
|
||||
NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DCFILT_COEFF[15:0]
|
||||
RW
|
||||
DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and
|
||||
fractional bits).
|
||||
NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0105
|
||||
REG_CHAN_CNTRL_2
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
IQCOR_COEFF_1[15:0]
|
||||
RW
|
||||
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value
|
||||
and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used,
|
||||
this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits).
|
||||
If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel
|
||||
with the format 1.1.14 (sign, integer and fractional bits).
|
||||
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
IQCOR_COEFF_2[15:0]
|
||||
RW
|
||||
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value
|
||||
and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient
|
||||
and the format is 1.1.14 (sign, integer and fractional bits).
|
||||
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0106
|
||||
REG_CHAN_CNTRL_3
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[19:16] 0x0
|
||||
ADC_PN_SEL[3:0]
|
||||
RW
|
||||
Selects the PN monitor sequence type (available only if ADC supports it). \\
|
||||
- 0x0: pn9a (device specific, modified pn9) \\
|
||||
- 0x1: pn23a (device specific, modified pn23) \\
|
||||
- 0x4: pn7 (standard O.150) \\
|
||||
- 0x5: pn15 (standard O.150) \\
|
||||
- 0x6: pn23 (standard O.150) \\
|
||||
- 0x7: pn31 (standard O.150) \\
|
||||
- 0x9: pnX (device specific, e.g. ad9361) \\
|
||||
- 0x0A: Nibble ramp (Device specific e.g. adrv9001) \\
|
||||
- 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \\
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3:0] 0x0
|
||||
ADC_DATA_SEL[3:0]
|
||||
RW
|
||||
Selects the data source to DMA.
|
||||
0x0: input data (ADC)
|
||||
0x1: loopback data (DAC)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0108
|
||||
REG_CHAN_USR_CNTRL_1
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[25] 0x0
|
||||
USR_DATATYPE_BE
|
||||
RO
|
||||
The user data type format- if set, indicates big endian (default is little endian).
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[24] 0x0
|
||||
USR_DATATYPE_SIGNED
|
||||
RO
|
||||
The user data type format- if set, indicates signed (2's complement) data (default is unsigned).
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x00
|
||||
USR_DATATYPE_SHIFT[7:0]
|
||||
RO
|
||||
The user data type format- the amount of right shift for actual samples within the total number
|
||||
of bits.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00
|
||||
USR_DATATYPE_TOTAL_BITS[7:0]
|
||||
RO
|
||||
The user data type format- number of total bits used for a sample. The total number of bits must
|
||||
be an integer multiple of 8 (byte aligned).
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
USR_DATATYPE_BITS[7:0]
|
||||
RO
|
||||
The user data type format- number of bits in a sample. This indicates the actual sample data bits.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0109
|
||||
REG_CHAN_USR_CNTRL_2
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
USR_DECIMATION_M[15:0]
|
||||
RW
|
||||
This holds the user decimation M value of the channel that is currently being selected on
|
||||
the multiplexer above. The total decimation factor is of the form M/N.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
USR_DECIMATION_N[15:0]
|
||||
RW
|
||||
This holds the user decimation N value of the channel that is currently being selected on
|
||||
the multiplexer above. The total decimation factor is of the form M/N.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0110
|
||||
REG_*
|
||||
Channel 1, similar to register 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x0120
|
||||
REG_*
|
||||
Channel 2, similar to register 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x01F0
|
||||
REG_*
|
||||
Channel 15, similar to register 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
TITLE
|
||||
Clock Generator (axi_clkgen)
|
||||
AXI_CLKGEN
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
REG_RSTN
|
||||
Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
MMCM_RSTN
|
||||
RW
|
||||
MMCM reset (required for DRP access).
|
||||
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RSTN
|
||||
RW
|
||||
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
REG_CLK_SEL
|
||||
Clock Select
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
CLK_SEL
|
||||
RW
|
||||
Select betwen CLKIN1 (0x0) or CLKIN2 (0x1) input clock for the MMCM
|
||||
ENDFIELD
|
||||
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0017
|
||||
REG_MMCM_STATUS
|
||||
MMCM Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
MMCM_LOCKED
|
||||
RO
|
||||
LOCKED status of the MMCM
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001c
|
||||
REG_DRP_CNTRL
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[28] 0x0
|
||||
DRP_RWN
|
||||
RW
|
||||
DRP read (0x1) or write (0x0) select (does not include GTX lanes).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[27:16] 0x000
|
||||
DRP_ADDRESS[11:0]
|
||||
RW
|
||||
DRP address, designs that contain more than one DRP accessible primitives
|
||||
have selects based on the most significant bits (does not include GTX lanes).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DRP_WDATA[15:0]
|
||||
RW
|
||||
DRP write data (does not include GTX lanes).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001d
|
||||
REG_DRP_STATUS
|
||||
MMCM Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[17] 0x0
|
||||
MMCM_LOCKED
|
||||
RO
|
||||
LOCKED status of the MMCM
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[16] 0x0
|
||||
DRP_STATUS
|
||||
RO
|
||||
If set indicates busy (access pending). The read data may not be valid if
|
||||
this bit is set (does not include GTX lanes).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DRP_RDATA
|
||||
RO
|
||||
DRP read data (does not include GTX lanes).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
#############################################################################################
|
||||
|
||||
REG
|
||||
0x0050
|
||||
REG_FPGA_VOLTAGE
|
||||
FPGA device voltage information
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0
|
||||
FPGA_VOLTAGE
|
||||
RO
|
||||
The voltage of the FPGA device in mv
|
||||
ENDFIELD
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
|
||||
|
||||
TITLE
|
||||
Clock Monitor (axi_clock_monitor)
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0000
|
||||
PCORE_VERSION
|
||||
PCORE Version Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000001
|
||||
PCORE_VERSION
|
||||
RO
|
||||
PCORE Version number
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0001
|
||||
ID
|
||||
ID Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
ID
|
||||
RW
|
||||
Instance identifier number
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0003
|
||||
NUM_OF_CLOCKS
|
||||
Number of Clocks Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000008
|
||||
NUM_OF_CLOCKS
|
||||
RW
|
||||
Number of clock inputs
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0004
|
||||
OUT_RESET
|
||||
Reset Control Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
0x0
|
||||
reset
|
||||
RW
|
||||
Control the out reset signal
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
CLOCK_0
|
||||
Measured clock_0
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_0
|
||||
RO
|
||||
Measured frequency of clock_0
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
CLOCK_1
|
||||
Measured clock_1
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_1
|
||||
RO
|
||||
Measured frequency of clock_1
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0012
|
||||
CLOCK_2
|
||||
Measured clock_2
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_2
|
||||
RO
|
||||
Measured frequency of clock_2
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0013
|
||||
CLOCK_3
|
||||
Measured clock_3
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_3
|
||||
RO
|
||||
Measured frequency of clock_3
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0014
|
||||
CLOCK_4
|
||||
Measured clock_4
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_4
|
||||
RO
|
||||
Measured frequency of clock_4
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0015
|
||||
CLOCK_5
|
||||
Measured clock_5
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_5
|
||||
RO
|
||||
Measured frequency of clock_5
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0016
|
||||
CLOCK_6
|
||||
Measured clock_6
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_6
|
||||
RO
|
||||
Measured frequency of clock_6
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0017
|
||||
CLOCK_7
|
||||
Measured clock_7
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_7
|
||||
RO
|
||||
Measured frequency of clock_7
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
CLOCK_8
|
||||
Measured clock_8
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_8
|
||||
RO
|
||||
Measured frequency of clock_8
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0019
|
||||
CLOCK_9
|
||||
Measured clock_9
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_9
|
||||
RO
|
||||
Measured frequency of clock_9
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001A
|
||||
CLOCK_10
|
||||
Measured clock_10
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_10
|
||||
RO
|
||||
Measured frequency of clock_10
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001B
|
||||
CLOCK_11
|
||||
Measured clock_11
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_11
|
||||
RO
|
||||
Measured frequency of clock_11
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001C
|
||||
CLOCK_12
|
||||
Measured clock_12
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_12
|
||||
RO
|
||||
Measured frequency of clock_12
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001D
|
||||
CLOCK_13
|
||||
Measured clock_13
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_13
|
||||
RO
|
||||
Measured frequency of clock_13
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001E
|
||||
CLOCK_14
|
||||
Measured clock_14
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_14
|
||||
RO
|
||||
Measured frequency of clock_14
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001F
|
||||
CLOCK_15
|
||||
Measured clock_15
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
clock_15
|
||||
RO
|
||||
Measured frequency of clock_15
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
|
||||
TITLE
|
||||
Base (common to all cores)
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0000
|
||||
REG_VERSION
|
||||
Version and Scratch Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
VERSION[31:0]
|
||||
RO
|
||||
Version number. Unique to all cores.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0001
|
||||
REG_ID
|
||||
Version and Scratch Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
ID[31:0]
|
||||
RO
|
||||
Instance identifier number.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0002
|
||||
REG_SCRATCH
|
||||
Version and Scratch Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH[31:0]
|
||||
RW
|
||||
Scratch register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0003
|
||||
REG_CONFIG
|
||||
Version and Scratch Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
IQCORRECTION_DISABLE
|
||||
RO
|
||||
If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
DCFILTER_DISABLE
|
||||
RO
|
||||
If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
DATAFORMAT_DISABLE
|
||||
RO
|
||||
If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
USERPORTS_DISABLE
|
||||
RO
|
||||
If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4] 0x0
|
||||
MODE_1R1T
|
||||
RO
|
||||
If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[5] 0x0
|
||||
DELAY_CONTROL_DISABLE
|
||||
RO
|
||||
If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[6] 0x0
|
||||
DDS_DISABLE
|
||||
RO
|
||||
If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7] 0x0
|
||||
CMOS_OR_LVDS_N
|
||||
RO
|
||||
CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[8] 0x0
|
||||
PPS_RECEIVER_ENABLE
|
||||
RO
|
||||
If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9] 0x0
|
||||
SCALECORRECTION_ONLY
|
||||
RO
|
||||
If set, indicates that the IQ Correction module implements only scale correction.
|
||||
IQ correction must be enabled. (as a result of a configuration of the IP instance)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12] 0x0
|
||||
EXT_SYNC
|
||||
RO
|
||||
If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
|
||||
ENDFIELD
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0004
|
||||
REG_PPS_IRQ_MASK
|
||||
PPS Interrupt mask
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
PPS_IRQ_MASK
|
||||
RW
|
||||
Mask bit for the 1PPS receiver interrupt
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0007
|
||||
REG_FPGA_INFO
|
||||
FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_intel_device_info_enc.tcl |Intel encoded values]]
|
||||
[[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:24] 0x0
|
||||
FPGA_TECHNOLOGY
|
||||
RO
|
||||
Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x0
|
||||
FPGA_FAMILY
|
||||
RO
|
||||
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x0
|
||||
SPEED_GRADE
|
||||
RO
|
||||
Encoded value describing the FPGA's speed-grade
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x0
|
||||
DEV_PACKAGE
|
||||
RO
|
||||
Encoded value describing the device package. The package might affect high-speed interfaces
|
||||
ENDFIELD
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
|
@ -0,0 +1,800 @@
|
|||
TITLE
|
||||
DAC Common (axi_ad)
|
||||
DAC_COMMON
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
REG_RSTN
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
CE_N
|
||||
RW
|
||||
Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of
|
||||
the module to control clock enables
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
MMCM_RSTN
|
||||
RW
|
||||
MMCM reset only (required for DRP access).
|
||||
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RSTN
|
||||
RW
|
||||
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
REG_CNTRL_1
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
SYNC
|
||||
RW
|
||||
Setting this bit synchronizes channels within a DAC, and across multiple instances.
|
||||
This bit self clears.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
EXT_SYNC_ARM
|
||||
RW
|
||||
Setting this bit will arm the trigger mechanism sensitive to an external sync signal.
|
||||
Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances.
|
||||
This bit has an effect only the EXT_SYNC synthesis parameter is set.
|
||||
This bit self clears.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
EXT_SYNC_DISARM
|
||||
RW
|
||||
Setting this bit will disarm the trigger mechanism sensitive to an external sync signal.
|
||||
This bit has an effect only the EXT_SYNC synthesis parameter is set.
|
||||
This bit self clears.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[8] 0x0
|
||||
MANUAL_SYNC_REQUEST
|
||||
RW
|
||||
Setting this bit will issue an external sync event if it is hooked up inside the fabric.
|
||||
This bit has an effect only the EXT_SYNC synthesis parameter is set.
|
||||
This bit self clears.
|
||||
ENDFIELD
|
||||
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0012
|
||||
REG_CNTRL_2
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[16] 0x0
|
||||
SDR_DDR_N
|
||||
RW
|
||||
Interface type (1 represents SDR, 0 represents DDR)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15] 0x0
|
||||
SYMB_OP
|
||||
RW
|
||||
Select data symbol format mode (0x1)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[14] 0x0
|
||||
SYMB_8_16B
|
||||
RW
|
||||
Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12:8] 0x0
|
||||
NUM_LANES[4:0]
|
||||
RW
|
||||
Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7] 0x0
|
||||
PAR_TYPE
|
||||
RW
|
||||
Select parity even (0x0) or odd (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[6] 0x0
|
||||
PAR_ENB
|
||||
RW
|
||||
Select parity (0x1) or frame (0x0) mode.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[5] 0x0
|
||||
R1_MODE
|
||||
RW
|
||||
Select number of RF channels 1 (0x1) or 2 (0x0).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4] 0x0
|
||||
DATA_FORMAT
|
||||
RW
|
||||
Select data format 2's complement (0x0) or offset binary (0x1).
|
||||
NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3:0] 0x00
|
||||
RESERVED[3:0]
|
||||
NA
|
||||
Reserved
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0013
|
||||
REG_RATECNTRL
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
RATE[7:0]
|
||||
RW
|
||||
The effective dac rate (the maximum possible rate is dependent on the interface clock).
|
||||
The samples are generated at 1/RATE of the interface clock.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0014
|
||||
REG_FRAME
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
FRAME
|
||||
RW
|
||||
The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1
|
||||
DCI clock period) pulse on the interface. This bit self clears.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0015
|
||||
REG_STATUS1
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CLK_FREQ[31:0]
|
||||
RO
|
||||
Interface clock frequency. This is relative to the processor clock and in many cases is
|
||||
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
||||
clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
|
||||
is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
|
||||
the same as the interface clock- software must consider device specific implementation
|
||||
parameters to calculate the final sampling clock.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0016
|
||||
REG_STATUS2
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CLK_RATIO[31:0]
|
||||
RO
|
||||
Interface clock ratio - as a factor actual received clock. This is implementation specific
|
||||
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0017
|
||||
REG_STATUS3
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
STATUS
|
||||
RO
|
||||
Interface status, if set indicates no errors. If not set, there
|
||||
are errors, software may try resetting the cores.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
REG_DAC_CLKSEL
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
DAC_CLKSEL
|
||||
RW
|
||||
Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001A
|
||||
REG_SYNC_STATUS
|
||||
DAC Synchronization Status register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
DAC_SYNC_STATUS
|
||||
RO
|
||||
DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal
|
||||
This bit has an effect only the EXT_SYNC synthesis parameter is set.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001C
|
||||
REG_DRP_CNTRL
|
||||
DRP Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[28] 0x0
|
||||
DRP_RWN
|
||||
RW
|
||||
DRP read (0x1) or write (0x0) select (does not include GTX lanes).
|
||||
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[27:16] 0x00
|
||||
DRP_ADDRESS[11:0]
|
||||
RW
|
||||
DRP address, designs that contain more than one DRP accessible primitives
|
||||
have selects based on the most significant bits (does not include GTX lanes).
|
||||
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
RESERVED[15:0]
|
||||
RO
|
||||
Reserved for backwards compatibility
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001D
|
||||
REG_DRP_STATUS
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[17] 0x0
|
||||
DRP_LOCKED
|
||||
RO
|
||||
If set indicates the MMCM/PLL is locked
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[16] 0x0
|
||||
DRP_STATUS
|
||||
RO
|
||||
If set indicates busy (access pending). The read data may not be valid if
|
||||
this bit is set (does not include GTX lanes).
|
||||
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
RESERVED[15:0]
|
||||
RO
|
||||
Reserved for backwards compatibility
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001E
|
||||
REG_DRP_WDATA
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DRP_WDATA[15:0]
|
||||
RW
|
||||
DRP write data (does not include GTX lanes).
|
||||
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001F
|
||||
REG_DRP_RDATA
|
||||
DAC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DRP_RDATA
|
||||
RO
|
||||
DRP read data (does not include GTX lanes).
|
||||
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0022
|
||||
REG_UI_STATUS
|
||||
User Interface Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
UI_OVF
|
||||
RW1C
|
||||
User Interface overflow. If set, indicates an overflow occurred during data transfer at
|
||||
the user interface (FIFO interface). Software must write a 0x1 to clear this register
|
||||
bit.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
UI_UNF
|
||||
RW1C
|
||||
User Interface underflow. If set, indicates an underflow occurred during data transfer at
|
||||
the user interface (FIFO interface). Software must write a 0x1 to clear this register
|
||||
bit.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0028
|
||||
REG_USR_CNTRL_1
|
||||
DAC User Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
USR_CHANMAX[7:0]
|
||||
RW
|
||||
This indicates the maximum number of inputs for the channel data multiplexers. User may add
|
||||
different processing modules as inputs to the dac.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002E
|
||||
REG_DAC_GPIO_IN
|
||||
DAC GPIO inputs
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
DAC_GPIO_IN[31:0]
|
||||
RO
|
||||
This reads auxiliary GPI pins of the DAC core
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002F
|
||||
REG_DAC_GPIO_OUT
|
||||
DAC GPIO outputs
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
DAC_GPIO_OUT[31:0]
|
||||
RW
|
||||
This controls auxiliary GPO pins of the DAC core
|
||||
NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
TITLE
|
||||
DAC Channel (axi_ad*)
|
||||
DAC_CHANNEL
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0100
|
||||
REG_CHAN_CNTRL_1
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DDS_SCALE_1[15:0]
|
||||
RW
|
||||
The DDS scale for tone 1. Defines the amplitude of the tone. The format is
|
||||
1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on
|
||||
16-bits, note that if you do use both channels and set both scale to 0x4000,
|
||||
it is over-range. The final output is (channel_1_fullscale * scale_1) +
|
||||
(channel_2 * scale_2).
|
||||
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0101
|
||||
REG_CHAN_CNTRL_2
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
DDS_INIT_1[15:0]
|
||||
RW
|
||||
The DDS phase initialization for tone 1. Defines the initial phase offset of
|
||||
the tone.
|
||||
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DDS_INCR_1[15:0]
|
||||
RW
|
||||
Defines the resolution of the phase accumulator. Its value can be defined by
|
||||
<m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated
|
||||
output frequency, and f_if is the frequency of the digital interface, and
|
||||
clock_ratio is the ratio between the sampling clock and the interface clock.
|
||||
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0102
|
||||
REG_CHAN_CNTRL_3
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DDS_SCALE_2[15:0]
|
||||
RW
|
||||
The DDS scale for tone 1. Defines the amplitude of the tone. The format is
|
||||
1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on
|
||||
16-bits, note that if you do use both channels and set both scale to 0x4000,
|
||||
it is over-range. The final output is (channel_1_fullscale * scale_1) +
|
||||
(channel_2 * scale_2).
|
||||
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0103
|
||||
REG_CHAN_CNTRL_4
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
DDS_INIT_2[15:0]
|
||||
RW
|
||||
The DDS phase initialization for tone 1. Defines the initial phase offset of
|
||||
the tone.
|
||||
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DDS_INCR_2[15:0]
|
||||
RW
|
||||
Defines the resolution of the phase accumulator. Its value can be defined by
|
||||
<m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated
|
||||
output frequency, and f_if is the frequency of the digital interface, and
|
||||
clock_ratio is the ratio between the sampling clock and the interface clock.
|
||||
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0104
|
||||
REG_CHAN_CNTRL_5
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
DDS_PATT_2[15:0]
|
||||
RW
|
||||
The DDS data pattern for this channel.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
DDS_PATT_1[15:0]
|
||||
RW
|
||||
The DDS data pattern for this channel.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0105
|
||||
REG_CHAN_CNTRL_6
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
IQCOR_ENB
|
||||
RW
|
||||
if set, enables IQ correction.
|
||||
NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
DAC_LB_OWR
|
||||
RW
|
||||
If set, forces DAC_DDS_SEL to 0x8, loopback
|
||||
If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
DAC_PN_OWR
|
||||
RW
|
||||
IF set, forces DAC_DDS_SEL to 0x09, device specific pnX
|
||||
If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0106
|
||||
REG_CHAN_CNTRL_7
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3:0] 0x00
|
||||
DAC_DDS_SEL[3:0]
|
||||
RW
|
||||
Select internal data sources (available only if the DAC supports it). \\
|
||||
- 0x00: internal tone (DDS) \\
|
||||
- 0x01: pattern (SED) \\
|
||||
- 0x02: input data (DMA) \\
|
||||
- 0x03: 0x00 \\
|
||||
- 0x04: inverted pn7 \\
|
||||
- 0x05: inverted pn15 \\
|
||||
- 0x06: pn7 (standard O.150) \\
|
||||
- 0x07: pn15 (standard O.150) \\
|
||||
- 0x08: loopback data (ADC) \\
|
||||
- 0x09: pnX (Device specific e.g. ad9361) \\
|
||||
- 0x0A: Nibble ramp (Device specific e.g. adrv9001) \\
|
||||
- 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \\
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0107
|
||||
REG_CHAN_CNTRL_8
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
IQCOR_COEFF_1[15:0]
|
||||
RW
|
||||
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value
|
||||
and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used,
|
||||
this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits).
|
||||
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
IQCOR_COEFF_2[15:0]
|
||||
RW
|
||||
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value
|
||||
and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient
|
||||
and the format is 1.1.14 (sign, integer and fractional bits).
|
||||
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0108
|
||||
REG_USR_CNTRL_3
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[25] 0x0
|
||||
USR_DATATYPE_BE
|
||||
RW
|
||||
The user data type format- if set, indicates big endian (default is little endian).
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[24] 0x0
|
||||
USR_DATATYPE_SIGNED
|
||||
RW
|
||||
The user data type format- if set, indicates signed (2's complement) data (default is unsigned).
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x00
|
||||
USR_DATATYPE_SHIFT[7:0]
|
||||
RW
|
||||
The user data type format- the amount of right shift for actual samples within the total number
|
||||
of bits.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00
|
||||
USR_DATATYPE_TOTAL_BITS[7:0]
|
||||
RW
|
||||
The user data type format- number of total bits used for a sample. The total number of bits must
|
||||
be an integer multiple of 8 (byte aligned).
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
USR_DATATYPE_BITS[7:0]
|
||||
RW
|
||||
The user data type format- number of bits in a sample. This indicates the actual sample data bits.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0109
|
||||
REG_USR_CNTRL_4
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
USR_INTERPOLATION_M[15:0]
|
||||
RW
|
||||
This holds the user interpolation M value of the channel that is currently being selected on
|
||||
the multiplexer above. The total interpolation factor is of the form M/N.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
USR_INTERPOLATION_N[15:0]
|
||||
RW
|
||||
This holds the user interpolation N value of the channel that is currently being selected on
|
||||
the multiplexer above. The total interpolation factor is of the form M/N.
|
||||
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x010A
|
||||
REG_USR_CNTRL_5
|
||||
DAC Channel Control & Status (channel - 0)
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
DAC_IQ_MODE[0]
|
||||
RW
|
||||
Enable complex mode. In this mode the driven data to the DAC must be a sequence
|
||||
of I and Q sample pairs.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
DAC_IQ_SWAP[1]
|
||||
RW
|
||||
Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0110
|
||||
REG_*
|
||||
Channel 1, similar to registers 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x0120
|
||||
REG_*
|
||||
Channel 2, similar to registers 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x01F0
|
||||
REG_*
|
||||
Channel 15, similar to registers 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
|
@ -0,0 +1,561 @@
|
|||
TITLE
|
||||
DMA Controller (axi_dmac)
|
||||
DMAC
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x000
|
||||
VERSION
|
||||
Version of the peripheral. Follows semantic versioning. Current version 4.03.61.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x04
|
||||
VERSION_MAJOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x03
|
||||
VERSION_MINOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x61
|
||||
VERSION_PATCH
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001
|
||||
PERIPHERAL_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''ID''
|
||||
PERIPHERAL_ID
|
||||
RO
|
||||
Value of the ID configuration parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002
|
||||
SCRATCH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register useful for debug.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x003
|
||||
IDENTIFICATION
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x444D4143
|
||||
IDENTIFICATION
|
||||
RO
|
||||
Peripheral identification ('D', 'M', 'A', 'C').
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x004
|
||||
INTERFACE_DESCRIPTION
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3:0] log2(''DMA_DATA_WIDTH_DEST''/8)
|
||||
BYTES_PER_BEAT_DEST_LOG2
|
||||
R
|
||||
Width of data bus on destination interface. Log2 of interface data widths in bytes.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[5:4] ''DMA_TYPE_DEST''
|
||||
DMA_TYPE_DEST
|
||||
R
|
||||
Value of ''DMA_TYPE_DEST'' parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO )
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[11:8] log2(''DMA_DATA_WIDTH_SRC''/8)
|
||||
BYTES_PER_BEAT_SRC_LOG2
|
||||
R
|
||||
Width of data bus on source interface. Log2 of interface data widths in bytes.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[13:12] ''DMA_TYPE_SRC''
|
||||
DMA_TYPE_SRC
|
||||
R
|
||||
Value of ''DMA_TYPE_SRC'' parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO )
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[19:16] ''BYTES_PER_BURST_WIDTH''
|
||||
BYTES_PER_BURST_WIDTH
|
||||
R
|
||||
Value of ''BYTES_PER_BURST_WIDTH'' interface parameter. Log2 of the real ''MAX_BYTES_PER_BURST''.
|
||||
The starting address of the transfer must be aligned with ''MAX_BYTES_PER_BURST'' to avoid crossing
|
||||
the 4kB address boundary.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x020
|
||||
IRQ_MASK
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x1
|
||||
TRANSFER_COMPLETED
|
||||
RW
|
||||
Masks the TRANSFER_COMPLETED IRQ.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
TRANSFER_QUEUED
|
||||
RW
|
||||
Masks the TRANSFER_QUEUED IRQ.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x021
|
||||
IRQ_PENDING
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TRANSFER_COMPLETED
|
||||
RW1C
|
||||
This bit will be asserted if a transfer has been completed and the
|
||||
TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been
|
||||
transferred or an error occurred during the transfer.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
TRANSFER_QUEUED
|
||||
RW1C
|
||||
This bit will be asserted if a transfer has been queued and it is possible to queue
|
||||
the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in the
|
||||
IRQ_MASK register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x022
|
||||
IRQ_SOURCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TRANSFER_COMPLETED
|
||||
RO
|
||||
This bit will be asserted if a transfer has been completed. Either if all bytes have been
|
||||
transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
TRANSFER_QUEUED
|
||||
RO
|
||||
This bit will be asserted if a transfer has been queued and it is possible to queue
|
||||
the next transfer. Cleared together with the corresponding IRQ_PENDING bit.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x100
|
||||
CONTROL
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
PAUSE
|
||||
RW
|
||||
When set to 1 the currently active transfer is paused. It will be resumed once the bit is
|
||||
cleared again.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
ENABLE
|
||||
RW
|
||||
When set to 1 the DMA channel is enabled.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x101
|
||||
TRANSFER_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1:0] 0x00
|
||||
TRANSFER_ID
|
||||
RO
|
||||
This register contains the ID of the next transfer. The ID is generated by the DMAC and after the
|
||||
transfer has been started can be used to check if the transfer has finished by checking the
|
||||
corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if
|
||||
TRANSFER_SUBMIT is 0.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x102
|
||||
TRANSFER_SUBMIT
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x00
|
||||
TRANSFER_SUBMIT
|
||||
RW
|
||||
Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once
|
||||
the transfer has been queued or the DMA channel is disabled.
|
||||
|
||||
Writing a 0 to this register has no effect.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x103
|
||||
FLAGS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] ''CYCLIC''
|
||||
CYCLIC
|
||||
RW
|
||||
Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode
|
||||
the controller will re-start a transfer again once it has finished. In cyclic
|
||||
mode no end-of-transfer interrupts will be generated.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x1
|
||||
TLAST
|
||||
RW
|
||||
When setting this bit for a MM to AXIS transfer the TLAST signal
|
||||
will be asserted during the last beat of the transfer.
|
||||
For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored.
|
||||
After its occurrence all descriptors are ignored until this bit is set.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
PARTIAL_REPORTING_EN
|
||||
RW
|
||||
When setting this bit the length of partial transfers caused eventually by TLAST will be recorded.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x104
|
||||
DEST_ADDRESS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
DEST_ADDRESS
|
||||
RW
|
||||
This register contains the destination address of the transfer. The address needs to be aligned
|
||||
to the bus width.
|
||||
|
||||
This register is only valid if the DMA channel has been configured for write to memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x105
|
||||
SRC_ADDRESS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SRC_ADDRESS
|
||||
RW
|
||||
This register contains the source address of the transfer. The address needs to be aligned
|
||||
to the bus width.
|
||||
|
||||
This register is only valid if the DMA channel has been configured for read from memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x106
|
||||
X_LENGTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] {log2(max(\n''DMA_DATA_WIDTH_SRC'',\n''DMA_DATA_WIDTH_DEST''\n)/8){1'b1}}
|
||||
X_LENGTH
|
||||
RW
|
||||
Number of bytes to transfer - 1.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x107
|
||||
Y_LENGTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
Y_LENGTH
|
||||
RW
|
||||
Number of rows to transfer - 1.
|
||||
|
||||
Note, this field is only valid if the DMA channel has been configured with 2D transfer support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x108
|
||||
DEST_STRIDE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
DEST_STRIDE
|
||||
RW
|
||||
The number of bytes between the start of one row and the next row for the
|
||||
destination address. Needs to be aligned to the bus width.
|
||||
|
||||
Note, this field is only valid if the DMA channel has been configured with 2D
|
||||
transfer support and write to memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x109
|
||||
SRC_STRIDE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
SRC_STRIDE
|
||||
RW
|
||||
The number of bytes between the start of one row and the next row for the source
|
||||
address. Needs to be aligned to the bus width.
|
||||
|
||||
Note, this field is only valid if the DMA channel has been configured with 2D
|
||||
transfer and read from memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
||||
REG
|
||||
0x10a
|
||||
TRANSFER_DONE
|
||||
If bit x is set in this register the transfer with ID x has been completed. The bit will automatically
|
||||
be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
TRANSFER_0_DONE
|
||||
RO
|
||||
If this bit is set the transfer with ID 0 has been completed.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TRANSFER_1_DONE
|
||||
RO
|
||||
If this bit is set the transfer with ID 1 has been completed.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
TRANSFER_2_DONE
|
||||
RO
|
||||
If this bit is set the transfer with ID 2 has been completed.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
TRANSFER_3_DONE
|
||||
RO
|
||||
If this bit is set the transfer with ID 3 has been completed.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[31] 0x0
|
||||
PARTIAL_TRANSFER_DONE
|
||||
RO
|
||||
If this bit is set at least one partial transfer was transferred.
|
||||
This field will reset when the ENABLE control bit is reset or when
|
||||
all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and
|
||||
PARTIAL_TRANSFER_ID registers.
|
||||
ENDFIELD
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10b
|
||||
ACTIVE_TRANSFER_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
ACTIVE_TRANSFER_ID
|
||||
RO
|
||||
ID of the currently active transfer. When no transfer is active this register will be equal to
|
||||
the TRANSFER_ID register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10c
|
||||
STATUS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
RESERVED
|
||||
RO
|
||||
This register is reserved for future usage. Reading it will always return 0.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10d
|
||||
CURRENT_DEST_ADDRESS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
CURRENT_DEST_ADDRESS
|
||||
RO
|
||||
Address to which the next data sample is written to.
|
||||
|
||||
This register is only valid if the DMA channel has been configured for write to memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10e
|
||||
CURRENT_SRC_ADDRESS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
CURRENT_SRC_ADDRESS
|
||||
RO
|
||||
Address form which the next data sample is read.
|
||||
|
||||
This register is only valid if the DMA channel has been configured for read from memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x112
|
||||
TRANSFER_PROGRESS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TRANSFER_PROGRESS
|
||||
RO
|
||||
This field presents the number of bytes transferred to the destination for the current transfer.
|
||||
This register will be cleared once the transfer completes.
|
||||
This should be used for debugging purposes only.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x113
|
||||
PARTIAL_TRANSFER_LENGTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x000000
|
||||
PARTIAL_LENGTH
|
||||
RO
|
||||
Length of the partial transfer in bytes. Represents the number of bytes received
|
||||
until the moment of TLAST assertion. This will be smaller than the programmed length
|
||||
from the X_LENGTH and Y_LENGTH registers.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x114
|
||||
PARTIAL_TRANSFER_ID
|
||||
Must be read after the PARTIAL_TRANSFER_LENGTH registers.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1:0] 0x0
|
||||
PARTIAL_TRANSFER_ID
|
||||
RO
|
||||
ID of the transfer that was partial.
|
||||
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,577 @@
|
|||
TITLE
|
||||
Fan Controller (axi_fan_control)
|
||||
AXI_FAN_CONTROL
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00
|
||||
VERSION
|
||||
Version of the peripheral. Follows semantic versioning. Current version 1.00.a.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0001
|
||||
VERSION_MAJOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00
|
||||
VERSION_MINOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x61
|
||||
VERSION_PATCH
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x01
|
||||
PERIPHERAL_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''ID''
|
||||
PERIPHERAL_ID
|
||||
RO
|
||||
Value of the ID configuration parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x02
|
||||
SCRATCH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register useful for debug.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x03
|
||||
IDENTIFICATION
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x46414E43
|
||||
IDENTIFICATION
|
||||
RO
|
||||
Peripheral identification ('F', 'A', 'N', 'C').
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10
|
||||
IRQ_MASK
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3] 0x1
|
||||
NEW_TACHO_MEASUREMENT
|
||||
RW
|
||||
Masks the TACHO_MEASUREMENT_DONE IRQ.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x1
|
||||
TEMP_INCREASE
|
||||
RW
|
||||
Masks the TEMP_INCREASE IRQ.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x1
|
||||
TACHO_ERR
|
||||
RW
|
||||
Masks the TACHO_ERR IRQ.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
PWM_CHANGED
|
||||
RW
|
||||
Masks the PWM_CHANGED IRQ.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x11
|
||||
IRQ_PENDING
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
NEW_TACHO_MEASUREMENT
|
||||
RW1C
|
||||
This bit will be asserted when the hardware has written a new value to the
|
||||
TACHO_MEASUREMENT register if the NEW_TACHO_MEASUREMENT bit in the IRQ_MASK
|
||||
register is not set.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
TEMP_INCREASE
|
||||
RW1C
|
||||
This bit will be asserted whenever the HW decides to increase the PWM
|
||||
duty-cycle, indicating a rise in temperature, and if the TEMP_INCREASE bit in
|
||||
the IRQ_MASK register is not set.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TACHO_ERR
|
||||
RW1C
|
||||
This bit will be asserted when a fault related to the tacho signal is detected.
|
||||
This can either mean that the tacho has not toggled in 5 seconds or that the
|
||||
period of the tacho signal is no longer whithin the defined valid interval.
|
||||
Also, the TACHO_ERR bit in the IRQ_MASK register must not be set.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
PWM_CHANGED
|
||||
RW1C
|
||||
This bit will be asserted when a 5 second delay expires after the PWM width was
|
||||
changed. The delay is used to allow the fan rotation speed to stabilize. Also,
|
||||
the PWM_CHANGED bit in the IRQ_MASK register must not be set.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x12
|
||||
IRQ_SOURCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
NEW_TACHO_MEASUREMENT
|
||||
RO
|
||||
This bit will be asserted when the hardware has written a new value to the
|
||||
TACHO_MEASUREMENT register.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
TEMP_INCREASE
|
||||
RO
|
||||
This bit will be asserted whenever the hardware decides to increase the PWM
|
||||
duty-cycle indicating a rise in temperature.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TACHO_ERR
|
||||
RO
|
||||
This bit will be asserted when a fault related to the tacho signal is detected.
|
||||
This can either mean that the tacho has not toggled in 5 seconds or that the
|
||||
period of the tacho signal is no longer whithin the defined valid interval.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
PWM_CHANGED
|
||||
RO
|
||||
This bit will be asserted when a 5 second delay expires after the PWM width was
|
||||
changed. The delay is used to allow the fan rotation speed to stabilize.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x20
|
||||
REG_RSTN
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RSTN
|
||||
RW
|
||||
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x21
|
||||
PWM_WIDTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''PWM_PERIOD''
|
||||
PWM_WIDTH
|
||||
RW
|
||||
This register contains the width of the PWM output signal. By default its
|
||||
value is established by the hardware after reading the temperature. By writing
|
||||
to this register the software can change the value however this is only possible
|
||||
if the requested value is greater than the value selected by the hardware and
|
||||
not exceeding the PWM period.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x22
|
||||
TACHO_PERIOD
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
TACHO_PERIOD
|
||||
RW
|
||||
After using the PWM_WIDTH register to request a different duty-cycle, the
|
||||
software can use this register to define the target period of the tacho signal.
|
||||
This is used together with the TACHO_TOLERANCE register to define an interval
|
||||
for the tacho signal. This register must be written before the TACHO_TOLERANCE
|
||||
register. The hardware will then use this interval to monitor the tacho signal
|
||||
coming from the fan.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x23
|
||||
TACHO_TOLERANCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
TACHO_TOLERANCE
|
||||
RW
|
||||
This register is used together with the TACHO_PERIOD register to define an
|
||||
interval for the fan's tacho signal. Writing to this register enables the
|
||||
hardware to start monitoring the tacho signal and so it must be written after
|
||||
the TACHO_PERIOD register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x24
|
||||
TEMP_DATA_SOURCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''INTERNAL_SYSMONE''
|
||||
TEMP_DATA_SOURCE
|
||||
RO
|
||||
This register copies the value from the INTERNAL_SYSMONE register and is used to inform
|
||||
the software what the source of the temperature information is.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x30
|
||||
PWM_PERIOD
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x4E20
|
||||
PWM_PERIOD
|
||||
RO
|
||||
This register contains the period for the PWM output signal. Derived from the
|
||||
PWM_FREQUENCY_HZ parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x31
|
||||
TACHO_MEASUREMENT
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
TACHO_MEASUREMENT
|
||||
RO
|
||||
This register contains the measurement results of the tacho signal period
|
||||
performed by the hardware.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x32
|
||||
TEMPERATURE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
TEMPERATURE
|
||||
RO
|
||||
This register contains the latest temperature reading from the SYSMONE
|
||||
primitive.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x40
|
||||
TEMP_00_H
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_00_H''
|
||||
TEMP_00_H
|
||||
RW
|
||||
Temperature threshold below which PWM should be 0%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x41
|
||||
TEMP_25_L
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_25_L''
|
||||
TEMP_25_L
|
||||
RW
|
||||
Temperature threshold above which PWM should be 25%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x42
|
||||
TEMP_25_H
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_25_H''
|
||||
TEMP_25_H
|
||||
RW
|
||||
Temperature threshold below which PWM should be 25%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x43
|
||||
TEMP_50_L
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_50_L''
|
||||
TEMP_50_L
|
||||
RW
|
||||
Temperature threshold above which PWM should be 50%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x44
|
||||
TEMP_50_H
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_50_H''
|
||||
TEMP_50_H
|
||||
RW
|
||||
Temperature threshold below which PWM should be 50%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x45
|
||||
TEMP_75_L
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_75_L''
|
||||
TEMP_75_L
|
||||
RW
|
||||
Temperature threshold above which PWM should be 75%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x46
|
||||
TEMP_75_H
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_75_H''
|
||||
TEMP_75_H
|
||||
RW
|
||||
Temperature threshold below which PWM should be 75%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x47
|
||||
TEMP_100_L
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TEMP_100_L''
|
||||
TEMP_100_L
|
||||
RW
|
||||
Temperature threshold above which PWM should be 100%
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x50
|
||||
TACHO_25
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T25''
|
||||
TACHO_25
|
||||
RW
|
||||
Nominal tacho period at 25% PWM
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x51
|
||||
TACHO_50
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T50''
|
||||
TACHO_50
|
||||
RW
|
||||
Nominal tacho period at 50% PWM
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x52
|
||||
TACHO_75
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T75''
|
||||
TACHO_75
|
||||
RW
|
||||
Nominal tacho period at 75% PWM
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x53
|
||||
TACHO_100
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T100''
|
||||
TACHO_100
|
||||
RW
|
||||
Nominal tacho period at 100% PWM
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x54
|
||||
TACHO_25_TOL
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T25'' \\ ''*TACHO_TOL_PERCENT'' \\ ''/100''
|
||||
TACHO_25_TOL
|
||||
RW
|
||||
Tolerance for the 25% PWM tacho period
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x55
|
||||
TACHO_50_TOL
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T50'' \\ ''*TACHO_TOL_PERCENT'' \\ ''/100''
|
||||
TACHO_50_TOL
|
||||
RW
|
||||
Tolerance for the 50% PWM tacho period
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x56
|
||||
TACHO_75_TOL
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T75'' \\ ''*TACHO_TOL_PERCENT'' \\ ''/100''
|
||||
TACHO_75_TOL
|
||||
RW
|
||||
Tolerance for the 75% PWM tacho period
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x57
|
||||
TACHO_100_TOL
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''TACHO_T100'' \\ ''*TACHO_TOL_PERCENT'' \\ ''/100''
|
||||
TACHO_100_TOL
|
||||
RW
|
||||
Tolerance for the 100% PWM tacho period
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
TITLE
|
||||
General Purpose Registers (axi_gpreg)
|
||||
AXI_GPREG
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0100
|
||||
REG_IO_ENB
|
||||
IO control register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IO_ENB
|
||||
RW
|
||||
IO control register (use as tri-state control, logic depends on the buffer type).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0101
|
||||
REG_IO_OUT
|
||||
IO output register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IO_ENB
|
||||
RW
|
||||
IO output register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
||||
REG
|
||||
0x0102
|
||||
REG_IO_IN
|
||||
IO input register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IO_IN
|
||||
RO
|
||||
IO input register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0110
|
||||
REG_*
|
||||
Channel 1, similar to register 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x0120
|
||||
REG_*
|
||||
Channel 2, similar to register 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x01f0
|
||||
REG_*
|
||||
Channel 15, similar to register 0x100 to 0x10f.
|
||||
ENDREG
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0200
|
||||
REG_CM_RESET
|
||||
Reset register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
CM_RESET_N
|
||||
RW
|
||||
Reset register (write a 0x01 to bring core out of reset).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0202
|
||||
REG_CM_COUNT
|
||||
Clock count register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CM_CLK_COUNT
|
||||
RO
|
||||
Interface clock frequency. This is relative to the processor clock and in many cases is
|
||||
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
||||
clock the minimum is 1.523kHz and maximum is 6.554THz.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0210
|
||||
REG_*
|
||||
Channel 1, similar to register 0x200 to 0x20f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x0220
|
||||
REG_*
|
||||
Channel 2, similar to register 0x200 to 0x20f.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x02f0
|
||||
REG_*
|
||||
Channel 15, similar to register 0x200 to 0x20f.
|
||||
ENDREG
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,611 @@
|
|||
TITLE
|
||||
HDMI Transmit (axi_hdmi_tx)
|
||||
HDMI_TX
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
REG_RSTN
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RSTN
|
||||
RW
|
||||
Reset, a common reset is used for all the interface modules,
|
||||
The default is reset (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
REG_CNTRL1
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
SS_BYPASS
|
||||
RW
|
||||
If set (0x1) bypasses the chroma sub-sampler. This is primarily intended to be used to send
|
||||
the test-pattern directly to the HDMI transmitter without modifying it.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
RESERVED
|
||||
RO
|
||||
Reserved
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
CSC_BYPASS
|
||||
RW
|
||||
If set (0x1) bypasses color space conversion (if equipped). And depending on its value, the
|
||||
default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0012
|
||||
REG_CNTRL2
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1:0] 0x0
|
||||
SOURCE_SEL
|
||||
RW
|
||||
Select the HDMI data source- register constant (0x3), incr-pattern (0x2),
|
||||
input (0x1) or disabled (0x0).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0013
|
||||
REG_CNTRL3
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
CONST_RGB[23:0]
|
||||
RW
|
||||
This is the RGB value transmitted, if the source is constant (see above).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0015
|
||||
REG_CLK_FREQ
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CLK_FREQ[31:0]
|
||||
RO
|
||||
Interface clock frequency. This is relative to the processor clock and in many cases is
|
||||
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
||||
clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
|
||||
is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
|
||||
the same as the interface clock- software must consider device specific implementation
|
||||
parameters to calculate the final sampling clock.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0016
|
||||
REG_CLK_RATIO
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CLK_RATIO[31:0]
|
||||
RO
|
||||
Interface clock ratio - as a factor actual received clock. This is implementation specific
|
||||
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0017
|
||||
REG_STATUS
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
STATUS
|
||||
RO
|
||||
Interface status, if set indicates no errors. If not set, there
|
||||
are errors, software may try resetting the cores.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
REG_VDMA_STATUS
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
VDMA_OVF
|
||||
RW1C
|
||||
If set, indicates vdma overflow.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
VDMA_UNF
|
||||
RW1C
|
||||
If set, indicates vdma underflow.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0019
|
||||
REG_TPM_STATUS
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
HDMI_TPM_OOS
|
||||
RW1C
|
||||
If set, indicates TPM OOS at the HDMI interface.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
VDMA_TPM_OOS
|
||||
RW1C
|
||||
If set, indicates TPM OOS at the VDMA interface.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001a
|
||||
REG_CLIPP_MAX
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:16] 0xF0
|
||||
R_MAX/Cr_MAX
|
||||
RW
|
||||
Defines the maximum value for clipping the red or red-difference chroma component.
|
||||
Default value are 0xf0 for red-difference chroma and 0xfe for red.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[16:8] 0xEB
|
||||
G_MAX/Y_MAX
|
||||
RW
|
||||
Defines the maximum value for clipping the green or luma component.
|
||||
Default values are 0xeb for luma and and 0xfe for green.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0xF0
|
||||
B_MAX/Cb_MAX
|
||||
RW
|
||||
Defines the maximum value for clipping the blue or blue-difference chroma component.
|
||||
Default value are 0xf0 for blue-difference chroma and 0xfe for blue.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001b
|
||||
REG_CLIPP_MIN
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:16] 0x10
|
||||
R_MIN/Cr_MIN
|
||||
RW
|
||||
Defines the minimum value for clipping the red or red-difference chroma component.
|
||||
Default value are 0x10 for red-difference chroma and 0x01 for red.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[16:8] 0x10
|
||||
G_MIN/Y_MIN
|
||||
RW
|
||||
Defines the minimum value for clipping the green or luma component.
|
||||
Default values are 0x10 for luma and and 0x01 for green.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x10
|
||||
B_MIN/Cb_MIN
|
||||
RW
|
||||
Defines the minimum value for clipping the blue or blue-difference chroma component.
|
||||
Default value are 0x10 for blue-difference chroma and 0x01 for blue.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0100
|
||||
REG_HSYNC_1
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
H_LINE_ACTIVE[15:0]
|
||||
RW
|
||||
This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
H_LINE_WIDTH[15:0]
|
||||
RW
|
||||
This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0101
|
||||
REG_HSYNC_2
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
H_SYNC_WIDTH[15:0]
|
||||
RW
|
||||
This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0102
|
||||
REG_HSYNC_3
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
H_ENABLE_MAX[15:0]
|
||||
RW
|
||||
This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active
|
||||
pixel width. e.g. 2112 (192 + 1920) (1080p)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
H_ENABLE_MIN[15:0]
|
||||
RW
|
||||
This is the horizontal data enable minimum. It is the sum of horizontal back porch (number
|
||||
of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync
|
||||
width. e.g. 192 (44 + 148) (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0110
|
||||
REG_VSYNC_1
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
V_FRAME_ACTIVE[15:0]
|
||||
RW
|
||||
This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
V_FRAME_WIDTH[15:0]
|
||||
RW
|
||||
This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0111
|
||||
REG_VSYNC_2
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
V_SYNC_WIDTH[15:0]
|
||||
RW
|
||||
This is the vertical sync width (no. of lines). e.g. 5 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0112
|
||||
REG_VSYNC_3
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
V_ENABLE_MAX[15:0]
|
||||
RW
|
||||
This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active
|
||||
pixel height. e.g. 1121 (41 + 1080) (1080p)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
V_ENABLE_MIN[15:0]
|
||||
RW
|
||||
This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines
|
||||
between the falling edge of VSYNC to the rising edge of DE) and the sync width.
|
||||
e.g. 41 (36 + 5) (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
TITLE
|
||||
HDMI Receive (axi_hdmi_rx)
|
||||
hdmi_rx
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
REG_RSTN
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RSTN
|
||||
RW
|
||||
Reset, a common reset is used for all the interface modules,
|
||||
The default is reset (0x0), software must write 0x1 to bring up the core.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
REG_CNTRL
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
EDGE_SEL
|
||||
RW
|
||||
If set (0x1), incoming data is registered on the falling edge of the clock first. The
|
||||
default uses rising edge.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
BGR
|
||||
RW
|
||||
If set (0x1), output BGR. The default is RGB.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
PACKED
|
||||
RW
|
||||
If set (0x1) pack 24bit RGB data on 32bit dwords. The default pads the MSB to zeros.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
CSC_BYPASS
|
||||
RW
|
||||
If set (0x1) bypasses color space conversion (if equipped).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0015
|
||||
REG_CLK_FREQ
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CLK_FREQ[31:0]
|
||||
RO
|
||||
Interface clock frequency. This is relative to the processor clock and in many cases is
|
||||
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
||||
clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
|
||||
is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
|
||||
the same as the interface clock- software must consider device specific implementation
|
||||
parameters to calculate the final sampling clock.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0016
|
||||
REG_CLK_RATIO
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
CLK_RATIO[31:0]
|
||||
RO
|
||||
Interface clock ratio - as a factor actual received clock. This is implementation specific
|
||||
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
REG_VDMA_STATUS
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
VDMA_OVF
|
||||
RW1C
|
||||
If set, indicates vdma overflow.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
VDMA_UNF
|
||||
RW1C
|
||||
If set, indicates vdma underflow.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0019
|
||||
REG_TPM_STATUS1
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
HDMI_TPM_OOS
|
||||
RW1C
|
||||
If set, indicates TPM OOS at the HDMI interface.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0020
|
||||
REG_TPM_STATUS2
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
VS_OOS
|
||||
RW1C
|
||||
If set, indicates VSYNC OOS - the core is unabled to detect/track VSYNC. Consecutive frames have different number of lines.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
HS_OOS
|
||||
RW1C
|
||||
If set, indicates HSYNC OOS - the core is unabled to detect/track HSYNC. Consecutive lines have different lengths.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
VS_MISMATCH
|
||||
RW1C
|
||||
If set, indicates received (detected) & programmed VSYNC (number of lines) mismatch. Incoming frames are stable but not the expected resolution.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
HS_MISMATCH
|
||||
RW1C
|
||||
If set, indicates received (detected) & programmed HSYNC (number of pixels) mismatch. Incoming frames are stable but not the expected resolution.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0100
|
||||
REG_HVCOUNTS1
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
VS_COUNT[15:0]
|
||||
RW
|
||||
This is the expected active horizontal pixel lines (active resolution length). e.g. 1080 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
HS_COUNT[15:0]
|
||||
RW
|
||||
This is the expected horizontal pixel count (no. of pixel clocks per line). e.g. 1920 (1080p)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0101
|
||||
REG_HVCOUNTS2
|
||||
HDMI Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
VS_COUNT[15:0]
|
||||
RO
|
||||
This is the detected horizontal active pixel lines (active resolution length).
|
||||
This field is valid only if VS_OOS is zero.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
HS_COUNT[15:0]
|
||||
RO
|
||||
This is the detected horizontal pixel count (no. of pixel clocks per line).
|
||||
This field is valid only if HS_OOS is zero.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
TITLE
|
||||
IO Delay Control (axi_ad*)
|
||||
IO_DELAY_CNTRL
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00
|
||||
REG_DELAY_CONTROL_0
|
||||
Delay Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
DELAY_CONTROL_IO_0
|
||||
RW
|
||||
Tap value for input/output delay primitive of the first interface line. If the delay controller is
|
||||
not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF.
|
||||
Otherwise will be the last set up value.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x01
|
||||
REG_DELAY_CONTROL_1
|
||||
Delay Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
DELAY_CONTROL_IO_1
|
||||
RW
|
||||
Tap value for input/output delay primitive of the second interface line. If the delay controller is
|
||||
not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF.
|
||||
Otherwise will be the last set up value.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x02
|
||||
REG_*
|
||||
Tap value for input/output delay primitive of the third interface line.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x03
|
||||
REG_*
|
||||
Tap value for input/output delay primitive of the fourth interface line.
|
||||
ENDREG
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0F
|
||||
REG_DELAY_CONTROL_F
|
||||
Delay Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
DELAY_CONTROL_IO_F
|
||||
RW
|
||||
Tap value for input/output delay primitive of the last interface line. In general the data and frame
|
||||
lines are controlled with delay primitives, the number of registers of a controller is device
|
||||
specific.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
|
@ -0,0 +1,991 @@
|
|||
TITLE
|
||||
JESD204 RX (axi_jesd204_rx)
|
||||
JESD_RX
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00
|
||||
VERSION
|
||||
Version of the peripheral. Follows semantic versioning. Current version 1.03.a.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0001
|
||||
VERSION_MAJOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x03
|
||||
VERSION_MINOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x61
|
||||
VERSION_PATCH
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x01
|
||||
PERIPHERAL_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
PERIPHERAL_ID
|
||||
RO
|
||||
Value of the ID configuration parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x02
|
||||
SCRATCH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register useful for debug.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x03
|
||||
IDENTIFICATION
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x32303452
|
||||
IDENTIFICATION
|
||||
RO
|
||||
Peripheral identification ('2', '0', '4', 'R').
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x04
|
||||
SYNTH_NUM_LANES
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
SYNTH_NUM_LANES
|
||||
RO
|
||||
Number of supported lanes.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x05
|
||||
SYNTH_DATA_PATH_WIDTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00000002
|
||||
TPL_DATA_PATH_WIDTH
|
||||
RO
|
||||
Data path width in octets at Transport Layer interface. Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00000002
|
||||
SYNTH_DATA_PATH_WIDTH
|
||||
RO
|
||||
Log2 of internal data path width in octets. Represents the datapath width towards the physical interface.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x06
|
||||
SYNTH_REG_1
|
||||
Core description register.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:19] 0x0000
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[18] 0
|
||||
ENABLE_CHAR_REPLACE
|
||||
RO
|
||||
This bit reflects the presence of character replacement monitoring logic for cases when scrambling is disabled.
|
||||
Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[17] 0
|
||||
ENABLE_FRAME_ALIGN_ERR_RESET
|
||||
RO
|
||||
If this bit is set in case of frame misalignment is detected the core resets itself.
|
||||
No software intervention is required.
|
||||
If the bit is not set and misalignment is detected the software must restart the link.
|
||||
Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[16] 1
|
||||
ENABLE_FRAME_ALIGN_CHECK
|
||||
RO
|
||||
This bit reflects the presence of frame alignment monitor.
|
||||
Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12] ASYNC_CLK
|
||||
ASYNC_CLK
|
||||
RO
|
||||
This bit is set if link clock and device clock are connected to different sources.
|
||||
This is useful for supporting modes where datapath width is not integer multiple of F.
|
||||
Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:8] 0x??
|
||||
DECODER
|
||||
RO
|
||||
Decoder presence: 01 - 8B10B decoder \\ 10 - 64B66B decoder
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x??
|
||||
NUM_LINKS
|
||||
RO
|
||||
Maximum supported links. Valid for 8B/10B encoder.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10
|
||||
SYNTH_ELASTIC_BUFFER_SIZE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000100
|
||||
SYNTH_ELASTIC_BUFFER_SIZE
|
||||
RO
|
||||
Elastic buffer size in octets.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x20
|
||||
IRQ_ENABLE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_ENABLE
|
||||
RW
|
||||
Interrupt enable.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x21
|
||||
IRQ_PENDING
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_PENDING
|
||||
RW1C-V
|
||||
Pending and enabled interrupts.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x22
|
||||
IRQ_SOURCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_SOURCE
|
||||
RW1C-V
|
||||
Pending interrupts.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x30
|
||||
LINK_DISABLE
|
||||
JESD204B link disable.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:1] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
LINK_DISABLE
|
||||
RW
|
||||
0 = Enable link, 1 = Disable link.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x31
|
||||
LINK_STATE
|
||||
JESD204B link state.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x?
|
||||
EXTERNAL_RESET
|
||||
RO
|
||||
0 = External reset de-asserted, 1 = External reset asserted.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
LINK_STATE
|
||||
RO
|
||||
0 = Link enabled, 1 = Link disabled.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x32
|
||||
LINK_CLK_FREQ
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[20:0] 0x?????????
|
||||
LINK_CLK_FREQ
|
||||
RO-V
|
||||
Ratio of the link_clk frequency relative to the s_axi_aclk. Format is 16.16.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x33
|
||||
DEVICE_CLK_FREQ
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[20:0] 0x?????????
|
||||
DEVICE_CLK_FREQ
|
||||
RO-V
|
||||
Ratio of the device_clk frequency relative to the s_axi_aclk. Format is 16.16.
|
||||
Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x40
|
||||
SYSREF_CONF
|
||||
SYSREF configuration
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
SYSREF_ONESHOT
|
||||
RW
|
||||
In oneshot mode only the first occurrence of the SYSREF signal is used for alignment.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
SYSREF_DISABLE
|
||||
RW
|
||||
Enable/Disable SYSREF handling.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x41
|
||||
SYSREF_LMFC_OFFSET
|
||||
SYSREF LMFC offset
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:10] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:0] 0x00
|
||||
SYSREF_LMFC_OFFSET
|
||||
RW
|
||||
Offset between SYSREF event and internal LMFC event in octets.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x42
|
||||
SYSREF_STATUS
|
||||
SYSREF status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
SYSREF_ALIGNMENT_ERROR
|
||||
RW1C-V
|
||||
Indicates that an external SYSREF event has been observed that was unaligned to a previously
|
||||
observed event.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
SYSREF_DETECTED
|
||||
RW1C-V
|
||||
Indicates that an external SYSREF event has been observed.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x80
|
||||
LANES_DISABLE
|
||||
Enabled/Disabled lanes.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[n] 0x0
|
||||
LANE_DISABLEn
|
||||
RW
|
||||
Enable/Disable n-th lane (0 = enabled, 1 = disabled).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x84
|
||||
LINK_CONF0
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:19] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[18:16] 0x00
|
||||
OCTETS_PER_FRAME
|
||||
RW
|
||||
Number of octets per frame - 1 (F).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:10] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:0] 0x03
|
||||
OCTETS_PER_MULTIFRAME
|
||||
RW
|
||||
Number of octets per multi-frame - 1 (K x F).
|
||||
In 64B/66B mode represents the number of octets per extended multiblock.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x85
|
||||
LINK_CONF1
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
CHAR_REPLACEMENT_DISABLE
|
||||
RW
|
||||
Enable/Disable user data alignment character replacement (0 = enabled, 1 = disabled).
|
||||
Valid for 8B/10B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
DESCRAMBLER_DISABLE
|
||||
RW
|
||||
Enable/Disable user data descrambling (0 = enabled, 1 = disabled).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x86
|
||||
MULTI_LINK_DISABLE
|
||||
Enable/Disable links in case of a multi-link architecture.
|
||||
Valid for 8B/10B encoder.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[n] 0x0
|
||||
LINK_DISABLEn
|
||||
RW
|
||||
Enable/Disable n-th link (0 = enabled, 1 = disabled).
|
||||
ENDFIELD
|
||||
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x87
|
||||
LINK_CONF4
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:8] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
TPL_BEATS_PER_MULTIFRAME
|
||||
RW
|
||||
Number of beats per multi-frame - 1 (K x F / TPL_DATA_PATH_WIDTH) at interface to Transport Layer.
|
||||
In 64B/66B mode represents the number of octets per extended multiblock.
|
||||
Available starting from version 1.07.a;
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x90
|
||||
LINK_CONF2
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:17] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[16] 0x0
|
||||
BUFFER_EARLY_RELEASE
|
||||
RW
|
||||
Elastic buffer release point.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:10] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:0] 0x0
|
||||
BUFFER_DEALY
|
||||
RW
|
||||
Buffer release opportunity offset from LMFC.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x91
|
||||
LINK_CONF3
|
||||
JESD204B error statistics configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:15] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[14] 0x0
|
||||
MASK_INVALID_HEADER
|
||||
RW
|
||||
If set, invalid header errors are not counted;
|
||||
Valid for 64B/66B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[13] 0x0
|
||||
MASK_UNEXPECTED_EOMB
|
||||
RW
|
||||
If set, unexpected end of multiblock errors are not counted;
|
||||
Valid for 64B/66B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12] 0x0
|
||||
MASK_UNEXPECTED_EOEMB
|
||||
RW
|
||||
If set, unexpected end of extended multiblock errors are not counted;
|
||||
Valid for 64B/66B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[11] 0x0
|
||||
MASK_CRC_MISMATCH
|
||||
RW
|
||||
If set, CRC mismatch errors are not counted.
|
||||
Valid for 64B/66B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[10] 0x0
|
||||
MASK_UNEXPECTEDK
|
||||
RW
|
||||
If set, unexpected k errors are not counted.
|
||||
Valid for 8B/10B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9] 0x0
|
||||
MASK_NOTINTABLE
|
||||
RW
|
||||
If set, not in table errors are not counted.
|
||||
Valid for 8B/10B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[8] 0x0
|
||||
MASK_DISPERR
|
||||
RW
|
||||
If set, disparity errors are not counted.
|
||||
Valid for 8B/10B encoder.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:1] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RESET_COUNTER
|
||||
RW
|
||||
If set, resets the error counter
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xa0
|
||||
LINK_STATUS
|
||||
JESD204B link status.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1:0] 0x00
|
||||
STATUS_STATE
|
||||
RO-V
|
||||
8B/10B : State of the [[#b10b_link_state_machine|8B/10B link state machine]]. (0 = RESET, 1 = WAIT_FOR_PHY, 2 = CGS, 3 = SYNCHRONIZED) \\
|
||||
64B/66B : State of the [[#b66b_link_state_machine|64B/66B link state machine]]. (0 = RESET, 1 = WAIT_BS, 2 = BLOCK_SYNC, 3 = DATA)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc0 + 0x08*n
|
||||
LANEn_STATUS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:11] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[10:8] 0x0
|
||||
EMB_STATE
|
||||
RO
|
||||
State of Extended multiblock alignment: \\
|
||||
|
||||
001 - EMB_INIT \\
|
||||
010 - EMB_HUNT \\
|
||||
100 - EMB_LOCK \\
|
||||
|
||||
Valid for 64b66b encoder.
|
||||
ENDFIELD
|
||||
|
||||
|
||||
FIELD
|
||||
[7:6] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[5] 0x0
|
||||
ILAS_READY
|
||||
RO-V
|
||||
ILAS configuration data received.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4] 0x0
|
||||
IFS_READY
|
||||
RO-V
|
||||
Frame synchronization state.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3:2] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1:0] 0x0
|
||||
CGS_STATE
|
||||
RO-V
|
||||
State of the lane code group synchronization. (0 = INIT, 1 = CHECK, 2 = DATA)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc1 + 0x08*n
|
||||
LANEn_LATENCY
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:14] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[13:0] 0x0
|
||||
LATENCY
|
||||
RO-V
|
||||
For 8b10b mode: represents the lane latency in octets;
|
||||
For 64b66b mode: represents the delay from the received EOEMB indicator to the next (SYSREF aligned) LEMC edge in octets.
|
||||
In other words, this amount of data is stored in the elastic buffer before it gets released on the LEMC edge. Must be greater than 64.
|
||||
Its max value is KxF octets. Where LEMC period = KxF/8 link clock periods.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc2 + 0x08*n
|
||||
LANEn_ERROR_STATISTICS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0
|
||||
ERROR_REGISTER
|
||||
RO
|
||||
This register shows the number of total errors for this lane. Errors counted depend on the configuration
|
||||
in LINK_CONF3. It must always be manually reset.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc3 + 0x08*n
|
||||
LANEn_LANE_FRAME_ALIGN_ERR_CNT
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0] 0x0
|
||||
ERROR_REGISTER
|
||||
RO
|
||||
This register shows the number of frame alignment errors for this lane. It resets with a link restart.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc4 + 0x08*n
|
||||
LANEn_ILAS0
|
||||
Received ILAS config data for the n-th lane.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:28] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[27:24] 0x0
|
||||
BID
|
||||
RO
|
||||
BID (Bank ID) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x00
|
||||
DID
|
||||
RO
|
||||
DID (Device ID) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc5 + 0x08*n
|
||||
LANEn_ILAS1
|
||||
Received ILAS config data for the n-th lane.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:29] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[28:24] 0x00
|
||||
K
|
||||
RO
|
||||
K (Frames per multi-frame) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x00
|
||||
F
|
||||
RO
|
||||
F (Octets per frame) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15] 0x0
|
||||
SCR
|
||||
RO
|
||||
SCR (Scrambling enabled) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[14:13] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12:8] 0x00
|
||||
L
|
||||
RO
|
||||
L (Number of lanes) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:5] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
LID
|
||||
RO
|
||||
LID (Lane ID) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc6 + 0x08*n
|
||||
LANEn_ILAS2
|
||||
Received ILAS config data for the n-th lane.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:29] 0x0
|
||||
JESDV
|
||||
RO
|
||||
JESDV (JESD204 version) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[28:24] 0x00
|
||||
S
|
||||
RO
|
||||
S (Samples per frame) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:21] 0x0
|
||||
SUBCLASSV
|
||||
RO
|
||||
SUBCLASSV (JESD204B subclass) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[20:16] 0x00
|
||||
NP
|
||||
RO
|
||||
N' (Total number of bits per sample) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:14] 0x0
|
||||
CS
|
||||
RO
|
||||
CS (Control bits per sample) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[13] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12:8] 0x00
|
||||
N
|
||||
RO
|
||||
N (Converter resolution) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
M
|
||||
RO
|
||||
M (Number of converters) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc7 + 0x08*n
|
||||
LANEn_ILAS3
|
||||
Received ILAS config data for the n-th lane.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:24] 0x00
|
||||
FCHK
|
||||
RO
|
||||
FCHK (Checksum) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:8] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7] 0x0
|
||||
HD
|
||||
RO
|
||||
HD (High-density) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[6:5] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
CF
|
||||
RO
|
||||
CF (control words per frame) field of the ILAS config sequence
|
||||
ENDFIELD
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
TITLE
|
||||
JESD TPL (up_tpl_common)
|
||||
JESD_TPL
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00080
|
||||
REG_TPL_CNTRL
|
||||
JESD, TPL Control
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3:0]
|
||||
PROFILE_SEL
|
||||
RW
|
||||
Selects one of the available deframer/framers from the transport layer.
|
||||
Valid only if ''PROFILE_NUM'' > 1.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00081
|
||||
REG_TPL_STATUS
|
||||
JESD, TPL Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[3:0]
|
||||
PROFILE_NUM
|
||||
RO
|
||||
Number of supported framer/deframer profiles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00090
|
||||
REG_TPL_DESCRIPTOR_1
|
||||
JESD, TPL descriptor for profile 0
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:24]
|
||||
JESD_F
|
||||
RO
|
||||
Octets per Frame per Lane.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16]
|
||||
JESD_S
|
||||
RO
|
||||
Samples per Converter per Frame.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8]
|
||||
JESD_L
|
||||
RO
|
||||
Lane Count.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
JESD_M
|
||||
RO
|
||||
Converter Count.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00091
|
||||
REG_TPL_DESCRIPTOR_2
|
||||
JESD, TPL descriptor for profile 0
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
JESD_N
|
||||
RO
|
||||
Converter Resolution.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8]
|
||||
JESD_NP
|
||||
RO
|
||||
Total Number of Bits per Sample.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00092
|
||||
REG_*
|
||||
Profile 1, similar to registers 0x00010 to 0x00011.
|
||||
ENDREG
|
||||
|
||||
REG
|
||||
0x00094
|
||||
REG_*
|
||||
Profile 2, similar to registers 0x00010 to 0x00011.
|
||||
ENDREG
|
||||
|
|
@ -0,0 +1,818 @@
|
|||
TITLE
|
||||
JESD204 TX (axi_jesd204_tx)
|
||||
JESD_TX
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00
|
||||
VERSION
|
||||
Version of the peripheral. Follows semantic versioning. Current version 1.03.a.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0001
|
||||
VERSION_MAJOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x03
|
||||
VERSION_MINOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x61
|
||||
VERSION_PATCH
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x01
|
||||
PERIPHERAL_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
PERIPHERAL_ID
|
||||
RO
|
||||
Value of the ID configuration parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x02
|
||||
SCRATCH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register useful for debug.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x03
|
||||
IDENTIFICATION
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x32303454
|
||||
IDENTIFICATION
|
||||
RO
|
||||
Peripheral identification ('2', '0', '4', 'T').
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x04
|
||||
SYNTH_NUM_LANES
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
SYNTH_NUM_LANES
|
||||
RO
|
||||
Number of supported lanes.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x05
|
||||
SYNTH_DATA_PATH_WIDTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0000
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00000002
|
||||
TPL_DATA_PATH_WIDTH
|
||||
RO
|
||||
Data path width in octets at Transport Layer interface. Available starting from version 1.06.a;
|
||||
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00000002
|
||||
SYNTH_DATA_PATH_WIDTH
|
||||
RO
|
||||
Log2 of internal data path width in octets. Represents the datapath width towards the physical interface.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x06
|
||||
SYNTH_REG_1
|
||||
Core description register.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:19] 0x0000
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[18] 0
|
||||
ENABLE_CHAR_REPLACE
|
||||
RO
|
||||
This bit reflects the presence of character replacement insertion logic for cases when scrambling is disabled.
|
||||
Available starting from version 1.06.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12] ASYNC_CLK
|
||||
ASYNC_CLK
|
||||
RO
|
||||
This bit is set if link clock and device clock are connected to different sources.
|
||||
This is useful for supporting modes where datapath width is not integer multiple of F.
|
||||
Available starting from version 1.06.a;
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:8] 0x??
|
||||
ENCODER
|
||||
RO
|
||||
Encoder presence: 01 - 8B10B encoder \\ 10 - 64B66B encoder
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x??
|
||||
NUM_LINKS
|
||||
RO
|
||||
Maximum supported links. Valid for 8B/10B link.
|
||||
ENDFIELD
|
||||
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x20
|
||||
IRQ_ENABLE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_ENABLE
|
||||
RW
|
||||
Interrupt enable.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x21
|
||||
IRQ_PENDING
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_PENDING
|
||||
RW1C-V
|
||||
Pending and enabled interrupts.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x22
|
||||
IRQ_SOURCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_SOURCE
|
||||
RW1C-V
|
||||
Pending interrupts.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x30
|
||||
LINK_DISABLE
|
||||
JESD204B link disable.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:1] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
LINK_DISABLE
|
||||
RW
|
||||
0 = Enable link, 1 = Disable link.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x31
|
||||
LINK_STATE
|
||||
JESD204B link state.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x?
|
||||
EXTERNAL_RESET
|
||||
RO
|
||||
0 = External reset de-asserted, 1 = External reset asserted.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x1
|
||||
LINK_STATE
|
||||
RO
|
||||
0 = Link enabled, 1 = Link disabled.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x32
|
||||
LINK_CLK_FREQ
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x?????????
|
||||
LINK_CLK_FREQ
|
||||
RO-V
|
||||
Ratio of the link_clk frequency relative to the s_axi_aclk. Format is 16.16.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x33
|
||||
DEVICE_CLK_FREQ
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[20:0] 0x?????????
|
||||
DEVICE_CLK_FREQ
|
||||
RO-V
|
||||
Ratio of the device_clk frequency relative to the s_axi_aclk. Format is 16.16.
|
||||
Available starting from version 1.06.a;
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x40
|
||||
SYSREF_CONF
|
||||
SYSREF configuration
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
SYSREF_ONESHOT
|
||||
RW
|
||||
In oneshot mode only the first occurrence of the SYSREF signal is used for alignment.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
SYSREF_DISABLE
|
||||
RW
|
||||
Enable/Disable SYSREF handling.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x41
|
||||
SYSREF_LMFC_OFFSET
|
||||
SYSREF LMFC offset
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:10] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:0] 0x00
|
||||
SYSREF_LMFC_OFFSET
|
||||
RW
|
||||
Offset between SYSREF event and internal LMFC event in octets.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x42
|
||||
SYSREF_STATUS
|
||||
SYSREF status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
SYSREF_ALIGNMENT_ERROR
|
||||
RW1C-V
|
||||
Indicates that an external SYSREF event has been observed that was unaligned to a previously
|
||||
observed event.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
SYSREF_DETECTED
|
||||
RW1C-V
|
||||
Indicates that an external SYSREF event has been observed.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x80
|
||||
LANES_DISABLE
|
||||
Enabled/Disabled lanes.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[n] 0x0
|
||||
LANE_DISABLEn
|
||||
RW
|
||||
Enable/Disable n-th lane (0 = enabled, 1 = disabled).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x84
|
||||
LINK_CONF0
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:19] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[18:16] 0x00
|
||||
OCTETS_PER_FRAME
|
||||
RW
|
||||
Number of octets per frame - 1 (F).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:10] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[9:0] 0x03
|
||||
OCTETS_PER_MULTIFRAME
|
||||
RW
|
||||
Number of octets per multi-frame - 1 (K x F).
|
||||
In 64B/66B mode represents the number of octets per extended multiblock.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x85
|
||||
LINK_CONF1
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:2] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
CHAR_REPLACEMENT_DISABLE
|
||||
RW
|
||||
Enable/Disable user data alignment character replacement (0 = enabled, 1 = disabled).
|
||||
Valid for 8B/10B link.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
SCRAMBLER_DISABLE
|
||||
RW
|
||||
Enable/Disable user data descrambling (0 = enabled, 1 = disabled).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x86
|
||||
MULTI_LINK_DISABLE
|
||||
Enable/Disable links in case of a multi-link architecture.
|
||||
Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[n] 0x0
|
||||
LINK_DISABLEn
|
||||
RW
|
||||
Enable/Disable n-th link (0 = enabled, 1 = disabled).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x87
|
||||
LINK_CONF4
|
||||
JESD204B link configuration.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:8] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
TPL_BEATS_PER_MULTIFRAME
|
||||
RW
|
||||
Number of beats per multi-frame - 1 (K x F / TPL_DATA_PATH_WIDTH) at interface to Transport Layer.
|
||||
In 64B/66B mode represents the number of octets per extended multiblock.
|
||||
Available starting from version 1.06.a;
|
||||
ENDFIELD
|
||||
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x90
|
||||
LINK_CONF2
|
||||
JESD204B link configuration. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:3] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
SKIP_ILAS
|
||||
RW
|
||||
Skip ILAS sequence during link startup.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
CONTINUOUS_ILAS
|
||||
RW
|
||||
Continuously transmit ILAS sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
CONTINUOUS_CGS
|
||||
RW
|
||||
Continuously transmit CGS sequence.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x91
|
||||
LINK_CONF3
|
||||
JESD204B link configuration. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:8] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x03
|
||||
MFRAMES_PER_ILAS
|
||||
RW
|
||||
Number of multi-frames in the ILAS sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x92
|
||||
MANUAL_SYNC_REQUEST
|
||||
Manual synchronization request. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:1] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
MANUAL_SYNC_REQUEST
|
||||
W1S
|
||||
Trigger manual synchronization request.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xa0
|
||||
LINK_STATUS
|
||||
JESD204B link status.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:12] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[11:4] 0x??
|
||||
STATUS_SYNC
|
||||
RO-V
|
||||
Raw state of the external SYNC~ signals. Valid for 8B/10B link.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3:2] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1:0] 0x00
|
||||
STATUS_STATE
|
||||
RO-V
|
||||
State of the 8B/10B link state machine. (0 = WAIT, 1 = CGS, 2 = ILAS, 3 = DATA);
|
||||
State of the 64B/66B link state machine. (0 = RESET, 3 = DATA)
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc4 + 0x08*n
|
||||
LANEn_ILAS0
|
||||
ILAS config data for the n-th lane. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:28] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[27:24] 0x0
|
||||
BID
|
||||
RW
|
||||
BID (Bank ID) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x00
|
||||
DID
|
||||
RW
|
||||
DID (Device ID) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0] 0x0000
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc5 + 0x08*n
|
||||
LANEn_ILAS1
|
||||
ILAS config data for the n-th lane. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:29] 0x00
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[28:24] 0x00
|
||||
K
|
||||
RW
|
||||
K (Frames per multi-frame) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16] 0x00
|
||||
F
|
||||
RW
|
||||
F (Octets per frame) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15] 0x0
|
||||
SCR
|
||||
RW
|
||||
SCR (Scrambling enabled) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[14:13] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12:8] 0x00
|
||||
L
|
||||
RW
|
||||
L (Number of lanes) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:5] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
LID
|
||||
RW
|
||||
LID (Lane ID) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc6 + 0x08*n
|
||||
LANEn_ILAS2
|
||||
ILAS config data for the n-th lane. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:29] 0x0
|
||||
JESDV
|
||||
RW
|
||||
JESDV (JESD204 version) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[28:24] 0x00
|
||||
S
|
||||
RW
|
||||
S (Samples per frame) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:21] 0x0
|
||||
SUBCLASSV
|
||||
RW
|
||||
SUBCLASSV (JESD204B subclass) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[20:16] 0x00
|
||||
NP
|
||||
RW
|
||||
N' (Total number of bits per sample) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:14] 0x0
|
||||
CS
|
||||
RW
|
||||
CS (Control bits per sample) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[13] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[12:8] 0x00
|
||||
N
|
||||
RW
|
||||
N (Converter resolution) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
M
|
||||
RW
|
||||
M (Number of converters) field of the ILAS config sequence - 1.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0xc7 + 0x08*n
|
||||
LANEn_ILAS3
|
||||
ILAS config data for the n-th lane. Valid for 8B/10B link.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:24] 0x00
|
||||
FCHK
|
||||
RW
|
||||
FCHK (Checksum) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:8] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7] 0x0
|
||||
HD
|
||||
RW
|
||||
HD (High-density) field of the ILAS config sequence.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[6:5] 0x0
|
||||
Reserved
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4:0] 0x00
|
||||
CF
|
||||
RO
|
||||
CF (control words per frame) field of the ILAS config sequence
|
||||
ENDFIELD
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
TITLE
|
||||
PWM Generator (axi_pwm_gen)
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0000
|
||||
REG_VERSION
|
||||
Version and Scratch Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00010100
|
||||
VERSION[31:0]
|
||||
RO
|
||||
Version number. Unique to all cores.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0001
|
||||
REG_ID
|
||||
Core ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
ID[31:0]
|
||||
RO
|
||||
Instance identifier number.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0002
|
||||
REG_SCRATCH
|
||||
Version and Scratch Registers
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH[31:0]
|
||||
RW
|
||||
Scratch register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0003
|
||||
REG_CORE_MAGIC
|
||||
Identification number
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x504C5347
|
||||
CORE_MAGIC[31:0]
|
||||
RW
|
||||
Identification number.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0004
|
||||
REG_RSTN
|
||||
Reset and load values
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
LOAD_CONFIG
|
||||
WO
|
||||
Loads the new values written in the config registers.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
RESET
|
||||
RW
|
||||
Reset, default is (0x0).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0005
|
||||
REG_NB_PULSES
|
||||
Number of pulses
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
NB_PULSES
|
||||
RO
|
||||
Number of configurable pulses.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
REG_PULSE_0_PERIOD
|
||||
Pulse 0 period
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_0_PERIOD[31:0]
|
||||
RW
|
||||
Pulse 0 duration, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
REG_PULSE_0_WIDTH
|
||||
Pulse 0 width
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_0_WIDTH[31:0]
|
||||
RW
|
||||
Pulse 0 width (high time), defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0012
|
||||
REG_PULSE_0_OFFSET
|
||||
Pulse 0 offset
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_0_OFFSET[31:0]
|
||||
RW
|
||||
Pulse 0 offset, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0013
|
||||
REG_PULSE_1_PERIOD
|
||||
Pulse 1 period
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_1_PERIOD[31:0]
|
||||
RW
|
||||
Pulse 1 duration, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0014
|
||||
REG_PULSE_1_WIDTH
|
||||
Pulse 1 width
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_1_WIDTH[31:0]
|
||||
RW
|
||||
Pulse 1 width (high time), defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0015
|
||||
REG_PULSE_1_OFFSET
|
||||
Pulse 1 offset
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_1_OFFSET[31:0]
|
||||
RW
|
||||
Pulse 1 offset, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0016
|
||||
REG_PULSE_2_PERIOD
|
||||
Pulse 2 period
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_2_PERIOD[31:0]
|
||||
RW
|
||||
Pulse 2 duration, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0017
|
||||
REG_PULSE_2_WIDTH
|
||||
Pulse 2 width
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_2_WIDTH[31:0]
|
||||
RW
|
||||
Pulse 2 width (high time) defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
REG_PULSE_2_OFFSET
|
||||
Pulse 2 offset
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_2_OFFSET[31:0]
|
||||
RW
|
||||
Pulse 2 offset, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0019
|
||||
REG_PULSE_3_PERIOD
|
||||
Pulse 3 period
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_3_PERIOD[31:0]
|
||||
RW
|
||||
Pulse 3 duration, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001a
|
||||
REG_PULSE_3_WIDTH
|
||||
Pulse 3 width
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_3_WIDTH[31:0]
|
||||
RW
|
||||
Pulse 3 width (high time) defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001b
|
||||
REG_PULSE_3_OFFSET
|
||||
Pulse 3 offset
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x0000
|
||||
PULSE_3_OFFSET[31:0]
|
||||
RW
|
||||
Pulse 3 offset, defined in number of clock cycles.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
TITLE
|
||||
SPI Engine (axi_spi_engine)
|
||||
axi_spi_engine
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00
|
||||
VERSION
|
||||
Version of the peripheral. Follows semantic versioning. Current version 1.00.71.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x01
|
||||
VERSION_MAJOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00
|
||||
VERSION_MINOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x71
|
||||
VERSION_PATCH
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x01
|
||||
PERIPHERAL_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''ID''
|
||||
PERIPHERAL_ID
|
||||
RO
|
||||
Value of the ID configuration parameter.
|
||||
In case of multiple instances, each instance will have a unique ID.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x02
|
||||
SCRATCH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register useful for debug.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x03
|
||||
DATA_WIDTH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000008
|
||||
DATA_WIDTH
|
||||
RO
|
||||
Data width of the SDI/SDO parallel interface.
|
||||
It is equal with the maximum supported transfer length in bits.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x10
|
||||
ENABLE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000001
|
||||
ENABLE
|
||||
RW
|
||||
Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset.
|
||||
For proper operation, the bit needs to be set to 0.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x20
|
||||
IRQ_MASK
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x00
|
||||
CMD_ALMOST_EMPTY
|
||||
RW
|
||||
If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x00
|
||||
SDO_ALMOST_EMPTY
|
||||
RW
|
||||
If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x00
|
||||
SDI_ALMOST_FULL
|
||||
RW
|
||||
If set to 0 the SDI_ALMOST_FULL interrupt is masked.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3] 0x00
|
||||
SYNC_EVENT
|
||||
RW
|
||||
If set to 0 the SYNC_EVENT interrupt is masked.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x21
|
||||
IRQ_PENDING
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_PENDING
|
||||
RW1C
|
||||
Pending IRQs with mask.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x22
|
||||
IRQ_SOURCE
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
IRQ_SOURCE
|
||||
RO
|
||||
Pending IRQs without mask.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x30
|
||||
SYNC_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SYNC_ID
|
||||
RO
|
||||
Last synchronization event ID received from the SPI engine control interface.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x34
|
||||
CMD_FIFO_ROOM
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
CMD_FIFO_ROOM
|
||||
RO
|
||||
Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register
|
||||
depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x35
|
||||
SDO_FIFO_ROOM
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
SDO_FIFO_ROOM
|
||||
RO
|
||||
Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM
|
||||
register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x36
|
||||
SDI_FIFO_LEVEL
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SDI_FIFO_LEVEL
|
||||
RO
|
||||
Number of valid entries in the serial-data-in FIFO.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x38
|
||||
CMD_FIFO
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x?????????
|
||||
CMD_FIFO
|
||||
WO
|
||||
Command FIFO register. Writing to this register inserts an entry into the command FIFO.
|
||||
Writing to this register when the command FIFO is full has no effect and the written entry
|
||||
is discarded. Reading from this register always returns 0x00000000.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x39
|
||||
SDO_FIFO
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x?????????
|
||||
SDO_FIFO
|
||||
WO
|
||||
SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO.
|
||||
Writing to this register when the SDO FIFO is full has no effect and the written entry is
|
||||
discarded. Reading from this register always returns 0x00000000.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x3a
|
||||
SDI_FIFO
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x?????????
|
||||
SDI_FIFO
|
||||
RO
|
||||
SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO.
|
||||
Reading this register when the SDI FIFO is empty will return undefined data.
|
||||
Writing to it has no effect.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x3c
|
||||
SDI_FIFO_PEEK
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x?????????
|
||||
SDI_FIFO_PEEK
|
||||
RO
|
||||
SDI FIFO peek register.
|
||||
Reading from this register returns the first entry from the SDI FIFO, but without removing
|
||||
it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined
|
||||
data. Writing to it has no effect.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x40
|
||||
OFFLOAD0_EN
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
OFFLOAD0_EN
|
||||
RW
|
||||
Set this bit to enable the offload module.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x41
|
||||
OFFLOAD0_STATUS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
OFFLOAD0_STATUS
|
||||
RO
|
||||
Offload status register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x42
|
||||
OFFLOAD0_MEM_RESET
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
OFFLOAD0_MEM_RESET
|
||||
WO
|
||||
Reset the memory of the offload module.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x44
|
||||
OFFLOAD0_CDM_FIFO
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
OFFLOAD0_CDM_FIFO
|
||||
WO
|
||||
Offload command FIFO register. Writing to this register inserts an entry into the command FIFO
|
||||
of the offload module. Writing to this register when the command FIFO is full has no effect
|
||||
and the written entry is discarded. Reading from this register always returns 0x00000000.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x45
|
||||
OFFLOAD0_SDO_FIFO
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x????????
|
||||
OFFLOAD0_SDO_FIFO
|
||||
WO
|
||||
Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO.
|
||||
Writing to this register when the SDO FIFO is full has no effect and the written entry is
|
||||
discarded. Reading from this register always returns 0x00000000.
|
||||
ENDFIELD
|
||||
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
|
||||
TITLE
|
||||
System ID (axi_system_id)
|
||||
AXI_SYSTEM_ID
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x00
|
||||
VERSION
|
||||
Version of the peripheral. Follows semantic versioning. Current version 1.00.a.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:16] 0x0001
|
||||
VERSION_MAJOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8] 0x00
|
||||
VERSION_MINOR
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0] 0x61
|
||||
VERSION_PATCH
|
||||
RO
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x01
|
||||
PERIPHERAL_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''ID''
|
||||
PERIPHERAL_ID
|
||||
RO
|
||||
Value of the ID configuration parameter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x02
|
||||
SCRATCH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register useful for debug.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x03
|
||||
IDENTIFICATION
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x53594944
|
||||
IDENTIFICATION
|
||||
RO
|
||||
Peripheral identification ('S', 'Y', 'I', 'D').
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x200
|
||||
SYSROM_START
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''N/A''
|
||||
SYSROM_START
|
||||
RO
|
||||
Start of register space for System ROM. Initialized at synthesis.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x400
|
||||
PRROM_START
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] ''N/A''
|
||||
SYSROM_START
|
||||
RO
|
||||
Start of register space for partial reconfiguration block ROM. Initialized at synthesis.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
TITLE
|
||||
Transceiver TDD Control (axi_ad*)
|
||||
TDD_CNTRL
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
REG_TDD_CONTROL_0
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[5] 0x0
|
||||
TDD_GATED_TX_DMAPATH
|
||||
RW
|
||||
If this bit is set, the core requests data from the TX DMA, just when the data path is active.
|
||||
Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to
|
||||
facilitate debug. This bit must be SET to preserve data integrity.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4] 0x0
|
||||
TDD_GATED_RX_DMAPATH
|
||||
RW
|
||||
If this bit is set, the core provides data for the RX DMA, just when the data path is active.
|
||||
Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to
|
||||
facilitate debug. This bit must be SET to preserve data integrity.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3] 0x0
|
||||
TDD_TXONLY
|
||||
RW
|
||||
If this bit is set- the TDD controller ignores all the TX_* timing registers
|
||||
below and assumes continuous receive operation within a frame.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2] 0x0
|
||||
TDD_RXONLY
|
||||
RW
|
||||
If this bit is set- the TDD controller ignores all the RX_* timing registers
|
||||
below and assumes continuous transmit operation within a frame.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TDD_SECONDARY
|
||||
RW
|
||||
Enable the secondary transmit/receive on the active frame. If this bit is clear -
|
||||
the controller only uses the _1 timing registers below. If this bit is set -
|
||||
the controller uses the _1 and _2 timing registers below.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
TDD_ENABLE
|
||||
RW
|
||||
If set, enables the TDD controller- software must set this bit after programming
|
||||
all the registers that controls the tdd timing. Any device settings needs to be
|
||||
done (for example bring the AD9361 to the alert state) prior to to setting this
|
||||
bit. The controller keeps the frame counters in reset if this bit is reset.
|
||||
A 0 to 1 transition in this bit starts the frame counter and tdd mode of operation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
REG_TDD_CONTROL_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0] 0x00
|
||||
TDD_BURST_COUNT
|
||||
RW
|
||||
If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode
|
||||
as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller
|
||||
operates for the set number of frames and stops.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0012
|
||||
REG_TDD_CONTROL_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_COUNTER_INIT
|
||||
RW
|
||||
The controller sets the frame counter to this value when starting TDD operation.
|
||||
This is the starting offset value for the TDD frame counter.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0013
|
||||
REG_TDD_FRAME_LENGTH
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_FRAME_LENGTH
|
||||
RW
|
||||
The frame length is the terminal count for the 10ms counter running at the digital
|
||||
interface clock- as an example for a 245.76MHz clock it is 0x258000.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0014
|
||||
REG_TDD_SYNC_TERMINAL_TYPE
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
TDD_SYNC_TERMINAL_TYPE
|
||||
RW
|
||||
Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
REG_TDD_STATUS
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0] 0x0
|
||||
TDD_RXTX_VCO_OVERLAP
|
||||
RO
|
||||
This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[1] 0x0
|
||||
TDD_RXTX_RF_OVERLAP
|
||||
RO
|
||||
This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0020
|
||||
REG_TDD_VCO_RX_ON_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_RX_ON_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time.
|
||||
The controller enables the receive VCO, when the frame count reaches this value.
|
||||
The VCO may have to be enabled before data can be received. The user needs to make sure,
|
||||
that the RF device is in a state, from where this operation is valid.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0021
|
||||
REG_TDD_VCO_RX_OFF_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_RX_OFF_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the RX VCO powers down at the first
|
||||
time. The controller disables the receive VCO, when the frame count reaches this value.
|
||||
The user needs to make sure, that the RF device is in a state, from where this operation
|
||||
is valid.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0022
|
||||
REG_TDD_VCO_TX_ON_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_TX_ON_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time.
|
||||
The controller enables the transmit VCO, when the frame count reaches this value. The user
|
||||
needs to make sure, that the RF device is in a state, from where this operation is valid.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0023
|
||||
REG_TDD_VCO_TX_OFF_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_TX_OFF_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the TX VCO powers down at the first
|
||||
time. The controller disables the transmit VCO when the frame count reaches this value.
|
||||
The user needs to make sure, that the RF device is in a state, from where this operation
|
||||
is valid.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0024
|
||||
REG_TDD_RX_ON_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_ON_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the RX data path is activated at the
|
||||
first time. The controller enables the receive chain when the frame count reaches this value.
|
||||
The user needs to make sure, that the RF device is in a state, from where this operation is valid.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0025
|
||||
REG_TDD_RX_OFF_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_OFF_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the RX data path is deactivated the
|
||||
first time. The controller disables the receive chain when the frame
|
||||
count reaches this value. The user needs to make sure, that the RF device is in
|
||||
a state, from where this operation is valid.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0026
|
||||
REG_TDD_TX_ON_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_ON_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the TX data path is activated at the
|
||||
first time. The controller enables the transmit chain, when the frame
|
||||
count reaches this value. This register and the TX_DP_ON register controls
|
||||
the delay between the data path being activated and the time to actually push the
|
||||
transmit data through the transmit chain in the device.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0027
|
||||
REG_TDD_TX_OFF_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_OFF_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the TX data path is deactivated at the
|
||||
first time. The controller disables the transmit chain, when the frame
|
||||
count reaches this value. This register and the TX_DP_OFF register controls the
|
||||
delay between the data path being deactivated and the time to actually stop
|
||||
transmitting data through the transmit chain in the device.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0028
|
||||
REG_TDD_RX_DP_ON_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_DP_ON_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the controller starts to accept data from
|
||||
the digital interface for receive.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0029
|
||||
REG_TDD_RX_DP_OFF_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_DP_OFF_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the controller stops to accept data from
|
||||
the digital interface for receive.
|
||||
ENDFIELD
|
||||
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002A
|
||||
REG_TDD_TX_DP_ON_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_DP_ON_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the controller starts to request data from the system
|
||||
memory for transmit. The data rate is controlled by the TDD controller.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002B
|
||||
REG_TDD_TX_DP_OFF_1
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_DP_OFF_1
|
||||
RW
|
||||
Defines the offset (from frame count equal zero), when the controller stop requesting data from the system
|
||||
memory for transmit.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0030
|
||||
REG_TDD_VCO_RX_ON_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_RX_ON_2
|
||||
RW
|
||||
The secondary pointer for VCO_RX_ON.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0031
|
||||
REG_TDD_VCO_RX_OFF_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_RX_OFF_2
|
||||
RW
|
||||
The secondary pointer for VCO_RX_OFF.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0032
|
||||
REG_TDD_VCO_TX_ON_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_TX_ON_2
|
||||
RW
|
||||
The secondary pointer for VCO_TX_ON.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0033
|
||||
REG_TDD_VCO_TX_OFF_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_VCO_TX_OFF_2
|
||||
RW
|
||||
The secondary pointer for VCO_TX_OFF.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0034
|
||||
REG_TDD_RX_ON_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_ON_2
|
||||
RW
|
||||
The secondary pointer for RX_ON.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0035
|
||||
REG_TDD_RX_OFF_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_OFF_2
|
||||
RW
|
||||
The secondary pointer for RX_OFF.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0036
|
||||
REG_TDD_TX_ON_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_ON_2
|
||||
RW
|
||||
The secondary pointer for TX_ON.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0037
|
||||
REG_TDD_TX_OFF_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_OFF_2
|
||||
RW
|
||||
The secondary pointer for TX_OFF.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0038
|
||||
REG_TDD_RX_DP_ON_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_DP_ON_2
|
||||
RW
|
||||
The secondary pointer for RX_DP_ON.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0039
|
||||
REG_TDD_RX_DP_OFF_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_RX_DP_OFF_2
|
||||
RW
|
||||
The secondary pointer for RX_DP_OFF.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x003A
|
||||
REG_TDD_TX_DP_ON_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_DP_ON_2
|
||||
RW
|
||||
The secondary pointer for TX_DP_ON.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x003B
|
||||
REG_TDD_TX_DP_OFF_2
|
||||
TDD Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[23:0] 0x000000
|
||||
TDD_TX_DP_OFF_2
|
||||
RW
|
||||
The secondary pointer for TX_DP_OFF.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
|
|
@ -0,0 +1,653 @@
|
|||
TITLE
|
||||
Xilinx XCVR (axi_xcvr) Regmap
|
||||
XCVR
|
||||
ENDTITLE
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0000
|
||||
VERSION
|
||||
Version Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
VERSION
|
||||
RO
|
||||
Version number.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0001
|
||||
ID
|
||||
Instance Identification Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
ID
|
||||
RO
|
||||
Instance identifier number.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0002
|
||||
SCRATCH
|
||||
Scratch (GP R/W) Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
SCRATCH
|
||||
RW
|
||||
Scratch register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0004
|
||||
RESETN
|
||||
Reset Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[1]
|
||||
BUFSTATUS_RST
|
||||
RW
|
||||
Initially this flag is held in reset with value 0x1, in order for a user to see the RX BUFSTATUS, this flag needs to be set to 0x0.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0]
|
||||
RESETN
|
||||
RW
|
||||
If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock and DRP clock must be active before setting this bit.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0005
|
||||
STATUS
|
||||
Status Reporting Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[6:5]
|
||||
BUFSTATUS
|
||||
RO
|
||||
BUFSTATUS provides status for either the RX buffer or the TX buffer. If BUFSTATUS is referring to the TX buffer, once BUFSTATUS is set High it remains High until RESETN is activated. Else if BUFSTATUS is referring to the RX buffer, once BUFSTSTATUS is High it can be cleared using BUFSTATUS_RST. If BUFTATUS[6] is 0x1 the internal FIFO overflows and when the BUFSTATUS[5] is 0x1 the internal FIFO underflows. Available from version 17.5.a. For more information consult the transceiver user guide(search for RXBUFSTATUS/TXBUFSTATUS).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[4]
|
||||
PLL_LOCK_N
|
||||
RO
|
||||
After setting the RESETN bit above, this bit must clear. If does not clears, indicates the CPLL/QPLL did not locked. Available from version 17.4.a
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0]
|
||||
STATUS
|
||||
RO
|
||||
After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0007
|
||||
FPGA_INFO
|
||||
FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:24]
|
||||
FPGA_TECHNOLOGY
|
||||
RO
|
||||
Encoded value describing the technology/generation of the FPGA device (e.g, 7series, ultrascale)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16]
|
||||
FPGA_FAMILY
|
||||
RO
|
||||
Encoded value describing the family variant of the FPGA device(e.g., zynq, kintex, virtex)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8]
|
||||
SPEED_GRADE
|
||||
RO
|
||||
Encoded value describing the FPGA's speed-grade
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
DEV_PACKAGE
|
||||
RO
|
||||
Encoded value describing the device package. The package might affect high-speed interfaces
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0008
|
||||
CONTROL
|
||||
Transceiver Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[12]
|
||||
LPM_DFE_N
|
||||
RW
|
||||
Transceiver primitive control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[10:8]
|
||||
RATE[2:0]
|
||||
RW
|
||||
Transceiver primitive control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[5:4]
|
||||
SYSCLK_SEL[1:0]
|
||||
RW
|
||||
For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver. Refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see [[:resources:fpga:docs:axi_adxcvr#Table 1]].
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2:0]
|
||||
OUTCLK_SEL[2:0]
|
||||
RW
|
||||
Transceiver primitive control [[:resources:fpga:docs:axi_adxcvr#Table 2]], refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0009
|
||||
GENERIC_INFO
|
||||
Physical layer info
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[20]
|
||||
QPLL_ENABLE
|
||||
RO
|
||||
Using QPLL.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[19:16]
|
||||
XCVR_TYPE[3:0]
|
||||
RO
|
||||
[[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[13:12]
|
||||
LINK_MODE
|
||||
RO
|
||||
Link layer mode : 01 - 8B10B decoder (aka 204B) 10 - 64B66B decoder (aka 204C); Available from version 17.3.a
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[8]
|
||||
TX_OR_RX_N
|
||||
RO
|
||||
Transceiver type (transmit or receive)
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
NUM_OF_LANES
|
||||
RO
|
||||
Physical layer number of lanes.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0010
|
||||
CM_SEL
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
CM_SEL
|
||||
RW
|
||||
Transceiver common-DRP sel, set to 0xff for broadcast.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0011
|
||||
CM_CONTROL
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[28]
|
||||
CM_WR
|
||||
RW
|
||||
Transceiver common-DRP sel, set to 0x1 for write, 0x0 for read.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[27:16]
|
||||
CM_ADDR
|
||||
RW
|
||||
Transceiver common-DRP read/write address.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0]
|
||||
CM_WDATA
|
||||
RW
|
||||
Transceiver common-DRP write data.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0012
|
||||
CM_STATUS
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[16]
|
||||
CM_BUSY
|
||||
RO
|
||||
Transceiver common-DRP access busy (0x1) or idle (0x0).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0]
|
||||
CM_RDATA
|
||||
RW
|
||||
Transceiver common-DRP read data.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0018
|
||||
CH_SEL
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
CH_SEL
|
||||
RW
|
||||
Transceiver channel-DRP sel, set to 0xff for broadcast.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0019
|
||||
CH_CONTROL
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[28]
|
||||
CH_WR
|
||||
RW
|
||||
Transceiver channel-DRP sel, set to 0x1 for write, 0x0 for read.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[27:16]
|
||||
CH_ADDR
|
||||
RW
|
||||
Transceiver channel-DRP read/write address.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0]
|
||||
CH_WDATA
|
||||
RW
|
||||
Transceiver channel-DRP write data.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x001a
|
||||
CH_STATUS
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[16]
|
||||
CH_BUSY
|
||||
RO
|
||||
Transceiver channel-DRP access busy (0x1) or idle (0x0).
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:0]
|
||||
CH_RDATA
|
||||
RW
|
||||
Transceiver channel-DRP read data.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0020
|
||||
ES_SEL
|
||||
Transceiver Access Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
ES_SEL
|
||||
RW
|
||||
Transceiver eye-scan-DRP sel, set to 0xff for broadcast.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0028
|
||||
ES_REQ
|
||||
Transceiver eye-scan Request Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0]
|
||||
ES_REQ
|
||||
RW
|
||||
Transceiver eye-scan request, set this bit to initiate an eye-scan, this bit auto-clears when scan is complete.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0029
|
||||
ES_CONTROL_1
|
||||
Transceiver eye-scan Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[4:0]
|
||||
ES_PRESCALE[4:0]
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002a
|
||||
0x00a8
|
||||
ES_CONTROL_2
|
||||
Transceiver eye-scan Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[25:24]
|
||||
ES_VOFFSET_RANGE
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[23:16]
|
||||
ES_VOFFSET_STEP
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[15:8]
|
||||
ES_VOFFSET_MAX
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[7:0]
|
||||
ES_VOFFSET_MIN
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002b
|
||||
ES_CONTROL_3
|
||||
Transceiver eye-scan Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[27:16]
|
||||
ES_HOFFSET_MAX
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[11:0]
|
||||
ES_HOFFSET_MIN
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002c
|
||||
ES_CONTROL_4
|
||||
Transceiver eye-scan Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[11:0]
|
||||
ES_HOFFSET_STEP
|
||||
RW
|
||||
Transceiver eye-scan control, refer Xilinx documentation.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002d
|
||||
ES_CONTROL_5
|
||||
Transceiver eye-scan Control Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
ES_STARTADDR
|
||||
RW
|
||||
Transceiver eye-scan control, DMA start address (ES data is written to this memory address).
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002e
|
||||
ES_STATUS
|
||||
Transceiver eye-scan Status Register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[0]
|
||||
ES_STATUS
|
||||
RO
|
||||
If set, indicates an error in ES DMA.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x002F
|
||||
ES_RESET
|
||||
Transceiver eye-scan reset control register
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[n]
|
||||
ES_RESET
|
||||
RW
|
||||
Controls the EYESCANRESET pin of the GTH/GTY transceivers for lane n.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
REG
|
||||
0x0030
|
||||
TX_DIFFCTRL
|
||||
Transceiver primitive control, refer Xilinx documentation.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
TX_DIFFCTRL
|
||||
RW
|
||||
TX driver swing control.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0031
|
||||
TX_POSTCURSOR
|
||||
Transceiver primitive control, refer Xilinx documentation.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
TX_POSTCURSOR
|
||||
RW
|
||||
Transmiter post-cursor TX pre-emphasis control.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0032
|
||||
TX_PRECURSOR
|
||||
Transceiver primitive control, refer Xilinx documentation.
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0]
|
||||
TX_PRECURSOR
|
||||
RW
|
||||
Transmiter pre-cursor TX pre-emphasis control.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0050
|
||||
FPGA_VOLTAGE
|
||||
FPGA device voltage information
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[15:0]
|
||||
FPGA_VOLTAGE
|
||||
RO
|
||||
The voltage of the FPGA device in mv
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0060
|
||||
PRBS_CNTRL
|
||||
Transceiver PRBS control
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[16]
|
||||
PRBSFORCEERR
|
||||
RW
|
||||
Valid for TX. If set, a single error is forced in the PRBS transmitter for every clock cycle. Can be used to test the PRBS checkers on the other side of the link.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[8]
|
||||
PRBSCNTRESET
|
||||
RW
|
||||
Valid for RX. Resets the PRBS error counter from the transceiver. Does not self clears. Value of error counter must be accessed via DRP.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[3:0]
|
||||
PRBSSEL
|
||||
RW
|
||||
PRBS checker or generator test pattern control. All zeros will put the PRBS in bypass mode. For TX non-zero values will stop the normal dataflow from link layer and will inject a pattern instead. See transceiver guide for specific values.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0061
|
||||
PRBS_STATUS
|
||||
RX Transceiver PRBS status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[8]
|
||||
PRBSERR
|
||||
RO
|
||||
This sticky status output indicates that PRBS errors have occurred. Value of error counter must be accessed via DRP.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[0]
|
||||
PRBSLOCKED
|
||||
RO
|
||||
Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET
|
||||
ENDFIELD
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue