spi_engine_offload: Define constraints for CDC
parent
ff4ce95110
commit
5493274fb7
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@ -0,0 +1,31 @@
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
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<: if { $async_spi_clk } { :>
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
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[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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<: } :>
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@ -3,10 +3,13 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create spi_engine_offload
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adi_ip_files spi_engine_offload [list \
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"spi_engine_offload_constr.ttcl" \
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"spi_engine_offload.v" \
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]
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adi_ip_properties_lite spi_engine_offload
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adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"
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# Remove all inferred interfaces
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ipx::remove_all_bus_interface [ipx::current_core]
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