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ad_tdd_control: Fix rx/tx only behavior 

When tx_only disable rx_enable and vice-versa
main
Laszlo Nagy 2020-10-02 10:38:06 +01:00 committed by Laszlo Nagy
parent bb44e5399f
commit 54c2cf7d12
2 changed files with 11 additions and 11 deletions
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6
library/axi_adrv9001/axi_adrv9001_core.v
View File

@ -577,9 +577,9 @@ module axi_ad9001_core #(
.up_rdata (up_rdata_s[7]),
.up_rack (up_rack_s[7]));
assign tdd_rx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en;
assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en;
assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode;
assign tdd_rx2_rf_en = rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en;
assign tdd_tx2_rf_en = tx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en;
assign tdd_if2_mode = tx1_r1_mode||rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode;
assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;

16
library/common/ad_tdd_control.v
View File

@ -781,8 +781,8 @@ module ad_tdd_control#(
tdd_rx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
tdd_rx_rf_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_rf_en <= tdd_rx_only;
end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end else begin
tdd_rx_rf_en <= tdd_rx_rf_en;
end
@ -795,8 +795,8 @@ module ad_tdd_control#(
tdd_tx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
tdd_tx_rf_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_rf_en <= tdd_tx_only;
end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end else begin
tdd_tx_rf_en <= tdd_tx_rf_en;
end
@ -809,8 +809,8 @@ module ad_tdd_control#(
tdd_tx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
tdd_tx_dp_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_dp_en <= tdd_tx_only;
end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end else begin
tdd_tx_dp_en <= tdd_tx_dp_en;
end
@ -823,8 +823,8 @@ module ad_tdd_control#(
tdd_rx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin
tdd_rx_dp_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_dp_en <= tdd_rx_only;
end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin
tdd_rx_dp_en <= 1'b0;
end else begin
tdd_rx_dp_en <= tdd_rx_dp_en;
end