zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad_serdes_in: Fix generate block

main
Istvan Csomortani 2017-04-20 18:50:00 +03:00
parent 7659700719
commit 54ff4d7bd0
1 changed files with 203 additions and 196 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

399
library/xilinx/common/ad_serdes_in.v
View File

@ -110,208 +110,215 @@ module ad_serdes_in #(
// received data interface: ibuf -> idelay -> iserdes // received data interface: ibuf -> idelay -> iserdes
genvar l_inst; genvar l_inst;
generate generate if (DEVICE_TYPE == 0) begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
IBUFDS i_ibuf ( IBUFDS i_ibuf (
.I (data_in_p[l_inst]), .I (data_in_p[l_inst]),
.IB (data_in_n[l_inst]), .IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst])); .O (data_in_ibuf_s[l_inst]));
if (DEVICE_TYPE == DEVICE_7SERIES) begin (* IODELAY_GROUP = IODELAY_GROUP *)
(* IODELAY_GROUP = IODELAY_GROUP *) IDELAYE2 #(
IDELAYE2 #( .CINVCTRL_SEL ("FALSE"),
.CINVCTRL_SEL ("FALSE"), .DELAY_SRC ("IDATAIN"),
.DELAY_SRC ("IDATAIN"), .HIGH_PERFORMANCE_MODE ("FALSE"),
.HIGH_PERFORMANCE_MODE ("FALSE"), .IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_TYPE ("VAR_LOAD"), .IDELAY_VALUE (0),
.IDELAY_VALUE (0), .REFCLK_FREQUENCY (200.0),
.REFCLK_FREQUENCY (200.0), .PIPE_SEL ("FALSE"),
.PIPE_SEL ("FALSE"), .SIGNAL_PATTERN ("DATA"))
.SIGNAL_PATTERN ("DATA")) i_idelay (
i_idelay ( .CE (1'b0),
.CE (1'b0), .INC (1'b0),
.INC (1'b0), .DATAIN (1'b0),
.DATAIN (1'b0), .LDPIPEEN (1'b0),
.LDPIPEEN (1'b0), .CINVCTRL (1'b0),
.CINVCTRL (1'b0), .REGRST (1'b0),
.REGRST (1'b0), .C (up_clk),
.C (up_clk), .IDATAIN (data_in_ibuf_s[l_inst]),
.IDATAIN (data_in_ibuf_s[l_inst]), .DATAOUT (data_in_idelay_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]), .LD (up_dld[l_inst]),
.LD (up_dld[l_inst]), .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]), .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
end
if(DEVICE_TYPE == DEVICE_6SERIES) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (data_in_ibuf_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]),
.RST (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
end
if (DEVICE_TYPE == DEVICE_7SERIES) begin ISERDESE2 #(
ISERDESE2 #( .DATA_RATE (DATA_RATE),
.DATA_RATE (DATA_RATE), .DATA_WIDTH (SERDES_FACTOR),
.DATA_WIDTH (SERDES_FACTOR), .DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLKDIV_INV_EN ("FALSE"), .DYN_CLK_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"), .INIT_Q1 (1'b0),
.INIT_Q1 (1'b0), .INIT_Q2 (1'b0),
.INIT_Q2 (1'b0), .INIT_Q3 (1'b0),
.INIT_Q3 (1'b0), .INIT_Q4 (1'b0),
.INIT_Q4 (1'b0), .INTERFACE_TYPE ("NETWORKING"),
.INTERFACE_TYPE ("NETWORKING"), .IOBDELAY ("IFD"),
.IOBDELAY ("IFD"), .NUM_CE (2),
.NUM_CE (2), .OFB_USED ("FALSE"),
.OFB_USED ("FALSE"), .SERDES_MODE ("MASTER"),
.SERDES_MODE ("MASTER"), .SRVAL_Q1 (1'b0),
.SRVAL_Q1 (1'b0), .SRVAL_Q2 (1'b0),
.SRVAL_Q2 (1'b0), .SRVAL_Q3 (1'b0),
.SRVAL_Q3 (1'b0), .SRVAL_Q4 (1'b0))
.SRVAL_Q4 (1'b0)) i_iserdes (
i_iserdes ( .O (),
.O (), .Q1 (data_s0[l_inst]),
.Q1 (data_s0[l_inst]), .Q2 (data_s1[l_inst]),
.Q2 (data_s1[l_inst]), .Q3 (data_s2[l_inst]),
.Q3 (data_s2[l_inst]), .Q4 (data_s3[l_inst]),
.Q4 (data_s3[l_inst]), .Q5 (data_s4[l_inst]),
.Q5 (data_s4[l_inst]), .Q6 (data_s5[l_inst]),
.Q6 (data_s5[l_inst]), .Q7 (data_s6[l_inst]),
.Q7 (data_s6[l_inst]), .Q8 (data_s7[l_inst]),
.Q8 (data_s7[l_inst]), .SHIFTOUT1 (),
.SHIFTOUT1 (), .SHIFTOUT2 (),
.SHIFTOUT2 (), .BITSLIP (1'b0),
.BITSLIP (1'b0), .CE1 (1'b1),
.CE1 (1'b1), .CE2 (1'b1),
.CE2 (1'b1), .CLKDIVP (1'b0),
.CLKDIVP (1'b0), .CLK (clk),
.CLK (clk), .CLKB (~clk),
.CLKB (~clk), .CLKDIV (div_clk),
.CLKDIV (div_clk), .OCLK (1'b0),
.OCLK (1'b0), .DYNCLKDIVSEL (1'b0),
.DYNCLKDIVSEL (1'b0), .DYNCLKSEL (1'b0),
.DYNCLKSEL (1'b0), .D (1'b0),
.D (1'b0), .DDLY (data_in_idelay_s[l_inst]),
.DDLY (data_in_idelay_s[l_inst]), .OFB (1'b0),
.OFB (1'b0), .OCLKB (1'b0),
.OCLKB (1'b0), .RST (rst),
.RST (rst), .SHIFTIN1 (1'b0),
.SHIFTIN1 (1'b0), .SHIFTIN2 (1'b0));
.SHIFTIN2 (1'b0)); end /* g_data */
end
if (DEVICE_TYPE == DEVICE_6SERIES) begin
ISERDESE1 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (SERDES_FACTOR),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("NETWORKING"),
.IOBDELAY ("NONE"),
.NUM_CE (1),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0))
i_iserdes_m (
.O (),
.Q1 (data_s0[l_inst]),
.Q2 (data_s1[l_inst]),
.Q3 (data_s2[l_inst]),
.Q4 (data_s3[l_inst]),
.Q5 (data_s4[l_inst]),
.Q6 (data_s5[l_inst]),
.SHIFTOUT1 (data_shift1_s[l_inst]),
.SHIFTOUT2 (data_shift2_s[l_inst]),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (clk),
.CLKB (~clk),
.CLKDIV (div_clk),
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.D (1'b0),
.DDLY (data_in_idelay_s[l_inst]),
.OFB (1'b0),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0));
ISERDESE1 #( end else begin
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (SERDES_FACTOR), for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"), IBUFDS i_ibuf (
.INIT_Q1 (1'b0), .I (data_in_p[l_inst]),
.INIT_Q2 (1'b0), .IB (data_in_n[l_inst]),
.INIT_Q3 (1'b0), .O (data_in_ibuf_s[l_inst]));
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("NETWORKING"), (* IODELAY_GROUP = IODELAY_GROUP *)
.IOBDELAY ("NONE"), IODELAYE1 #(
.NUM_CE (1), .CINVCTRL_SEL ("FALSE"),
.OFB_USED ("FALSE"), .DELAY_SRC ("I"),
.SERDES_MODE ("SLAVE"), .HIGH_PERFORMANCE_MODE ("TRUE"),
.SRVAL_Q1 (1'b0), .IDELAY_TYPE ("VAR_LOADABLE"),
.SRVAL_Q2 (1'b0), .IDELAY_VALUE (0),
.SRVAL_Q3 (1'b0), .ODELAY_TYPE ("FIXED"),
.SRVAL_Q4 (1'b0)) .ODELAY_VALUE (0),
i_iserdes_s ( .REFCLK_FREQUENCY (200.0),
.O (), .SIGNAL_PATTERN ("DATA"))
.Q1 (), i_idelay (
.Q2 (), .T (1'b1),
.Q3 (data_s6[l_inst]), .CE (1'b0),
.Q4 (data_s7[l_inst]), .INC (1'b0),
.Q5 (), .CLKIN (1'b0),
.Q6 (), .DATAIN (1'b0),
.SHIFTOUT1 (), .ODATAIN (1'b0),
.SHIFTOUT2 (), .CINVCTRL (1'b0),
.BITSLIP (1'b0), .C (up_clk),
.CE1 (1'b1), .IDATAIN (data_in_ibuf_s[l_inst]),
.CE2 (1'b1), .DATAOUT (data_in_idelay_s[l_inst]),
.CLK (clk), .RST (up_dld[l_inst]),
.CLKB (~clk), .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CLKDIV (div_clk), .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0), ISERDESE1 #(
.DYNCLKSEL (1'b0), .DATA_RATE (DATA_RATE),
.D (1'b0), .DATA_WIDTH (SERDES_FACTOR),
.DDLY (data_in_idelay_s[l_inst]), .DYN_CLKDIV_INV_EN ("FALSE"),
.OFB (1'b0), .DYN_CLK_INV_EN ("FALSE"),
.RST (rst), .INIT_Q1 (1'b0),
.SHIFTIN1 (data_shift1_s[l_inst]), .INIT_Q2 (1'b0),
.SHIFTIN2 (data_shift2_s[l_inst])); .INIT_Q3 (1'b0),
end .INIT_Q4 (1'b0),
end .INTERFACE_TYPE ("NETWORKING"),
.IOBDELAY ("NONE"),
.NUM_CE (1),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0))
i_iserdes_m (
.O (),
.Q1 (data_s0[l_inst]),
.Q2 (data_s1[l_inst]),
.Q3 (data_s2[l_inst]),
.Q4 (data_s3[l_inst]),
.Q5 (data_s4[l_inst]),
.Q6 (data_s5[l_inst]),
.SHIFTOUT1 (data_shift1_s[l_inst]),
.SHIFTOUT2 (data_shift2_s[l_inst]),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (clk),
.CLKB (~clk),
.CLKDIV (div_clk),
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.D (1'b0),
.DDLY (data_in_idelay_s[l_inst]),
.OFB (1'b0),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0));
ISERDESE1 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (SERDES_FACTOR),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("NETWORKING"),
.IOBDELAY ("NONE"),
.NUM_CE (1),
.OFB_USED ("FALSE"),
.SERDES_MODE ("SLAVE"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0))
i_iserdes_s (
.O (),
.Q1 (),
.Q2 (),
.Q3 (data_s6[l_inst]),
.Q4 (data_s7[l_inst]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (clk),
.CLKB (~clk),
.CLKDIV (div_clk),
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.D (1'b0),
.DDLY (data_in_idelay_s[l_inst]),
.OFB (1'b0),
.RST (rst),
.SHIFTIN1 (data_shift1_s[l_inst]),
.SHIFTIN2 (data_shift2_s[l_inst]));
end /* g_data */
end
endgenerate endgenerate
endmodule endmodule
// *************************************************************************** // ***************************************************************************