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ad_serdes_in: Fix generate block

main
Istvan Csomortani 2017-04-20 18:50:00 +03:00
parent 7659700719
commit 54ff4d7bd0
1 changed files with 203 additions and 196 deletions
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75
library/xilinx/common/ad_serdes_in.v
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@ -110,7 +110,7 @@ module ad_serdes_in #(
// received data interface: ibuf -> idelay -> iserdes
genvar l_inst;
generate
generate if (DEVICE_TYPE == 0) begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
IBUFDS i_ibuf (
@ -118,7 +118,6 @@ module ad_serdes_in #(
.IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst]));
if (DEVICE_TYPE == DEVICE_7SERIES) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
@ -142,36 +141,7 @@ module ad_serdes_in #(
.LD (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
end
if(DEVICE_TYPE == DEVICE_6SERIES) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (data_in_ibuf_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]),
.RST (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
end
if (DEVICE_TYPE == DEVICE_7SERIES) begin
ISERDESE2 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (SERDES_FACTOR),
@ -219,8 +189,43 @@ module ad_serdes_in #(
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0));
end
if (DEVICE_TYPE == DEVICE_6SERIES) begin
end /* g_data */
end else begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
IBUFDS i_ibuf (
.I (data_in_p[l_inst]),
.IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst]));
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (data_in_ibuf_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]),
.RST (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
ISERDESE1 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (SERDES_FACTOR),
@ -308,10 +313,12 @@ module ad_serdes_in #(
.RST (rst),
.SHIFTIN1 (data_shift1_s[l_inst]),
.SHIFTIN2 (data_shift2_s[l_inst]));
end
end /* g_data */
end
endgenerate
endmodule
// ***************************************************************************