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axi_adxcvr- compile fixes

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Rejeesh Kutty 2016-09-01 10:05:16 -04:00
parent 230f1526c0
commit 5544e3cf10
3 changed files with 102 additions and 72 deletions
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74
library/altera/axi_adxcvr/axi_adxcvr.v
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@ -41,50 +41,50 @@ module axi_adxcvr (
// xcvr, lane-pll and ref-pll are shared // xcvr, lane-pll and ref-pll are shared
output up_rst, output up_rst,
input up_ref_pll_locked, input up_ref_pll_locked,
input up_pll_locked, input [(NUM_OF_LANES-1):0] up_ready,
input up_ready,
input s_axi_clk, input s_axi_clk,
input s_axi_aresetn, input s_axi_aresetn,
input s_axi_awvalid, input s_axi_awvalid,
input [31:0] s_axi_awaddr, input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
output s_axi_awready, output s_axi_awready,
input s_axi_wvalid, input s_axi_wvalid,
input [31:0] s_axi_wdata, input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb, input [ 3:0] s_axi_wstrb,
output s_axi_wready, output s_axi_wready,
output s_axi_bvalid, output s_axi_bvalid,
output [ 1:0] s_axi_bresp, output [ 1:0] s_axi_bresp,
input s_axi_bready, input s_axi_bready,
input s_axi_arvalid, input s_axi_arvalid,
input [31:0] s_axi_araddr, input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot, input [ 2:0] s_axi_arprot,
output s_axi_arready, output s_axi_arready,
output s_axi_rvalid, output s_axi_rvalid,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
input s_axi_rready); input s_axi_rready);
// parameters // parameters
parameter integer ID = 0; parameter integer ID = 0;
parameter integer TX_OR_RX_N = 0; parameter integer TX_OR_RX_N = 0;
parameter integer NUM_OF_LANES = 4;
// internal signals // internal signals
wire up_rstn; wire up_rstn;
wire up_clk; wire up_clk;
wire up_wreq; wire up_wreq;
wire [ 9:0] up_waddr; wire [ 9:0] up_waddr;
wire [31:0] up_wdata; wire [31:0] up_wdata;
wire up_wack; wire up_wack;
wire up_rreq; wire up_rreq;
wire [ 9:0] up_raddr; wire [ 9:0] up_raddr;
wire [31:0] up_rdata; wire [31:0] up_rdata;
wire up_rack; wire up_rack;
// clk & rst // clk & rst
@ -95,11 +95,11 @@ module axi_adxcvr (
axi_adxcvr_up #( axi_adxcvr_up #(
.ID (ID), .ID (ID),
.TX_OR_RX_N (TX_OR_RX_N)) .TX_OR_RX_N (TX_OR_RX_N),
.NUM_OF_LANES (NUM_OF_LANES))
i_up ( i_up (
.up_rst (up_rst), .up_rst (up_rst),
.up_ref_pll_locked (up_ref_pll_locked), .up_ref_pll_locked (up_ref_pll_locked),
.up_pll_locked (up_pll_locked),
.up_ready (up_ready), .up_ready (up_ready),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),

44
library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
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@ -5,10 +5,11 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
set_module_property NAME axi_adxcvr set_module_property NAME axi_adxcvr
set_module_property DESCRIPTION "AXI ADXCVR Interface" set_module_property DESCRIPTION "AXI ADXCVR Core"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_adxcvr set_module_property DISPLAY_NAME axi_adxcvr
set_module_property ELABORATION_CALLBACK p_axi_adxcvr
# files # files
@ -27,10 +28,16 @@ set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true set_parameter_property ID HDL_PARAMETER true
add_parameter TX_OR_RX_N INTEGER 0 add_parameter TX_OR_RX_N INTEGER 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
set_parameter_property DEVICE_TYPE TYPE INTEGER set_parameter_property TX_OR_RX_N TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None set_parameter_property TX_OR_RX_N UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true set_parameter_property TX_OR_RX_N HDL_PARAMETER true
add_parameter NUM_OF_LANES INTEGER 4
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
# axi4 slave interface # axi4 slave interface
@ -66,12 +73,27 @@ add_interface_port s_axi s_axi_rready rready Input 1
# xcvr interface # xcvr interface
add_interface if_xcvr conduit end ad_alt_intf reset up_rst output 1 s_axi_clock
add_interface_port if_xcvr up_rst up_rst Output 1 set_interface_property if_up_rst associatedResetSinks s_axi_reset
add_interface_port if_xcvr up_ref_pll_locked up_ref_pll_locked Input 1
add_interface_port if_xcvr up_pll_locked up_pll_locked Input 1
add_interface_port if_xcvr up_ready up_ready Input 1
set_interface_property if_xcvr associatedClock s_axi_clock add_interface ref_pll_locked conduit end
add_interface_port ref_pll_locked up_ref_pll_locked export Input 1
# name changes
proc p_axi_adxcvr {} {
set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
if {$m_tx_or_rx_n == 1} {
add_interface ready conduit end
add_interface_port ready up_ready tx_ready input $m_num_of_lanes
}
if {$m_tx_or_rx_n == 0} {
add_interface ready conduit end
add_interface_port ready up_ready rx_ready input $m_num_of_lanes
}
}

56
library/altera/axi_adxcvr/axi_adxcvr_up.v
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@ -41,39 +41,44 @@ module axi_adxcvr_up (
// xcvr, lane-pll and ref-pll are shared // xcvr, lane-pll and ref-pll are shared
output up_rst, output up_rst,
input up_ref_pll_locked, input up_ref_pll_locked,
input up_pll_locked, input [(NUM_OF_LANES-1):0] up_ready,
input up_ready,
// bus interface // bus interface
input up_rstn, input up_rstn,
input up_clk, input up_clk,
input up_wreq, input up_wreq,
input [ 9:0] up_waddr, input [ 9:0] up_waddr,
input [31:0] up_wdata, input [31:0] up_wdata,
output up_wack, output up_wack,
input up_rreq, input up_rreq,
input [ 9:0] up_raddr, input [ 9:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack);
// parameters // parameters
localparam [31:0] VERSION = 32'h00100161; localparam [31:0] VERSION = 32'h00100161;
parameter integer ID = 0; parameter integer ID = 0;
parameter integer TX_OR_RX_N = 0; parameter integer TX_OR_RX_N = 0;
parameter integer NUM_OF_LANES = 4;
// internal registers // internal registers
reg up_wreq_d = 'd0; reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0; reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0; reg up_resetn = 'd0;
reg [ 3:0] up_rst_cnt = 'd0; reg [ 3:0] up_rst_cnt = 'd0;
reg up_status_int = 'd0; reg up_status_int = 'd0;
reg up_rreq_d = 'd0; reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0; reg [31:0] up_rdata_d = 'd0;
// internal signals
wire up_ready_s;
wire [31:0] up_status_32_s;
// defaults // defaults
@ -105,6 +110,10 @@ module axi_adxcvr_up (
assign up_rst = up_rst_cnt[3]; assign up_rst = up_rst_cnt[3];
assign up_status = up_status_int; assign up_status = up_status_int;
assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
assign up_status_32_s[31:(NUM_OF_LANES+1)] <= 'd0;
assign up_status_32_s[NUM_OF_LANES] <= up_ref_pll_locked;
assign up_status_32_s[(NUM_OF_LANES-1):0] <= up_ready;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
@ -118,8 +127,7 @@ module axi_adxcvr_up (
end end
if (up_resetn == 1'b0) begin if (up_resetn == 1'b0) begin
up_status_int <= 1'b0; up_status_int <= 1'b0;
end else if ((up_pll_locked == 1'b1) && (up_ready == 1'b1) && end else if (up_ready_s == 1'b1) begin
(up_ref_pll_locked == 1'b1)) begin
up_status_int <= 1'b1; up_status_int <= 1'b1;
end end
end end
@ -143,7 +151,7 @@ module axi_adxcvr_up (
10'h002: up_rdata_d <= up_scratch; 10'h002: up_rdata_d <= up_scratch;
10'h004: up_rdata_d <= {31'd0, up_resetn}; 10'h004: up_rdata_d <= {31'd0, up_resetn};
10'h005: up_rdata_d <= {31'd0, up_status_int}; 10'h005: up_rdata_d <= {31'd0, up_status_int};
10'h006: up_rdata_d <= {29'd0, up_pll_locked, up_ref_pll_locked, up_ready}; 10'h006: up_rdata_d <= up_status_32_s;
default: up_rdata_d <= 32'd0; default: up_rdata_d <= 32'd0;
endcase endcase
end else begin end else begin