axi_ad9467: Independent read/write update
Independent read/write operation is supported on "up" interfacemain
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82717b354a
commit
5565cf8fad
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@ -138,8 +138,9 @@ module axi_ad9467(
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// internal registers
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reg up_wack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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reg up_rack = 'd0;
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// internal clocks & resets
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@ -163,11 +164,13 @@ module axi_ad9467(
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wire up_status_pn_err_s;
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wire up_status_pn_oos_s;
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wire up_status_or_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s[0:1];
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wire up_ack_s[0:1];
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire up_rack_s[0:1];
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wire up_wack_s[0:1];
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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//defaults
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@ -181,10 +184,12 @@ module axi_ad9467(
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 32'd0;
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up_ack <= 1'd0;
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up_rack <= 1'd0;
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up_wack <= 1'd0;
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end else begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1];
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up_ack <= up_ack_s[0] | up_ack_s[1];
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up_rack <= up_rack_s[0] | up_rack_s[1];
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up_wack <= up_wack_s[0] | up_wack_s[1];
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end
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end
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@ -228,12 +233,14 @@ module axi_ad9467(
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.up_adc_or (up_status_or_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[0]),
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.up_ack (up_ack_s[0]));
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.up_rack (up_rack_s[0]));
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// common processor control
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@ -275,12 +282,14 @@ module axi_ad9467(
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[1]),
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.up_ack (up_ack_s[1]));
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.up_rack (up_rack_s[1]));
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// up bus interface
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@ -304,12 +313,14 @@ module axi_ad9467(
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_ack (up_ack));
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.up_rack (up_rack));
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endmodule
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@ -58,12 +58,14 @@ module axi_ad9467_channel(
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up_rstn,
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up_clk,
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up_sel,
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up_wr,
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up_addr,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_ack);
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up_rack);
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// parameters
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@ -88,12 +90,14 @@ module axi_ad9467_channel(
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input up_rstn;
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input up_clk;
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input up_sel;
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input up_wr;
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input [13:0] up_addr;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_ack;
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output up_rack;
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// internal signals
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@ -112,7 +116,7 @@ module axi_ad9467_channel(
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.adc_pn_oos (adc_pn_oos_s),
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.adc_pn_err (adc_pn_err_s),
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.adc_pnseq_sel (adc_pnseq_sel_s));
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ad_datafmt #(.DATA_WIDTH(16)) i_datafmt (
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.clk(adc_clk),
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.valid(1'b1),
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@ -122,7 +126,7 @@ module axi_ad9467_channel(
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.dfmt_enable(adc_dfmt_enable_s),
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.dfmt_type(adc_dfmt_type_s),
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.dfmt_se(adc_dfmt_se_s));
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up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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@ -160,12 +164,14 @@ module axi_ad9467_channel(
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_ack (up_ack));
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.up_rack (up_rack));
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endmodule
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