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axi_ad9467: Independent read/write update 

Independent read/write operation is supported on "up" interface
main
Istvan Csomortani 2014-10-08 11:23:44 +03:00
parent 82717b354a
commit 5565cf8fad
2 changed files with 50 additions and 33 deletions
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49
library/axi_ad9467/axi_ad9467.v
View File

@ -138,8 +138,9 @@ module axi_ad9467(
// internal registers // internal registers
reg up_wack = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0; reg up_rack = 'd0;
// internal clocks & resets // internal clocks & resets
@ -163,11 +164,13 @@ module axi_ad9467(
wire up_status_pn_err_s; wire up_status_pn_err_s;
wire up_status_pn_oos_s; wire up_status_pn_oos_s;
wire up_status_or_s; wire up_status_or_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:1]; wire [31:0] up_rdata_s[0:1];
wire up_ack_s[0:1]; wire up_rack_s[0:1];
wire up_sel_s; wire up_wack_s[0:1];
wire up_wr_s; wire up_wreq_s;
wire [13:0] up_addr_s; wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s; wire [31:0] up_wdata_s;
//defaults //defaults
@ -181,10 +184,12 @@ module axi_ad9467(
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_rdata <= 32'd0; up_rdata <= 32'd0;
up_ack <= 1'd0; up_rack <= 1'd0;
up_wack <= 1'd0;
end else begin end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1]; up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_ack <= up_ack_s[0] | up_ack_s[1]; up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
end end
end end
@ -228,12 +233,14 @@ module axi_ad9467(
.up_adc_or (up_status_or_s), .up_adc_or (up_status_or_s),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_wreq (up_wreq_s),
.up_wr (up_wr_s), .up_waddr (up_waddr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]), .up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0])); .up_rack (up_rack_s[0]));
// common processor control // common processor control
@ -275,12 +282,14 @@ module axi_ad9467(
.up_adc_gpio_out (), .up_adc_gpio_out (),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_wreq (up_wreq_s),
.up_wr (up_wr_s), .up_waddr (up_waddr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]), .up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1])); .up_rack (up_rack_s[1]));
// up bus interface // up bus interface
@ -304,12 +313,14 @@ module axi_ad9467(
.up_axi_rresp (s_axi_rresp), .up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata), .up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready), .up_axi_rready (s_axi_rready),
.up_sel (up_sel_s), .up_wreq (up_wreq_s),
.up_wr (up_wr_s), .up_waddr (up_waddr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata), .up_rdata (up_rdata),
.up_ack (up_ack)); .up_rack (up_rack));
endmodule endmodule

30
library/axi_ad9467/axi_ad9467_channel.v
View File

@ -58,12 +58,14 @@ module axi_ad9467_channel(
up_rstn, up_rstn,
up_clk, up_clk,
up_sel, up_wreq,
up_wr, up_waddr,
up_addr,
up_wdata, up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata, up_rdata,
up_ack); up_rack);
// parameters // parameters
@ -88,12 +90,14 @@ module axi_ad9467_channel(
input up_rstn; input up_rstn;
input up_clk; input up_clk;
input up_sel; input up_wreq;
input up_wr; input [13:0] up_waddr;
input [13:0] up_addr;
input [31:0] up_wdata; input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata; output [31:0] up_rdata;
output up_ack; output up_rack;
// internal signals // internal signals
@ -160,12 +164,14 @@ module axi_ad9467_channel(
.adc_usr_decimation_n (16'd1), .adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel), .up_wreq (up_wreq),
.up_wr (up_wr), .up_waddr (up_waddr),
.up_addr (up_addr),
.up_wdata (up_wdata), .up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata), .up_rdata (up_rdata),
.up_ack (up_ack)); .up_rack (up_rack));
endmodule endmodule