From 557efed5d958f7dea3406c51b597f42b15cf3e3e Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 14 Dec 2016 17:35:35 +0200 Subject: [PATCH] ad6676evb: Update clock constraints --- projects/ad6676evb/vc707/system_constr.xdc | 4 ++-- projects/ad6676evb/zc706/system_constr.xdc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc index 4d650e118..cfde1a20c 100644 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -30,8 +30,8 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] # clocks -create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc index f5d2f91db..3e7474150 100644 --- a/projects/ad6676evb/zc706/system_constr.xdc +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -30,8 +30,8 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4 # clocks -create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]