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ad6676evb: Update clock constraints

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Istvan Csomortani 2016-12-14 17:35:35 +02:00 committed by Csomortani
parent 3a2c889115
commit 557efed5d9
2 changed files with 4 additions and 4 deletions
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4
projects/ad6676evb/vc707/system_constr.xdc
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@ -30,8 +30,8 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
# clocks # clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

4
projects/ad6676evb/zc706/system_constr.xdc
View File

@ -30,8 +30,8 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4
# clocks # clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]