zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

adrv9009/zcu102: Increase DAC buffer depth to 18Mb

main
Istvan Csomortani 2018-09-05 09:32:28 +01:00 committed by István Csomortáni
parent d2939f2a44
commit 559e00fd75
2 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
projects/adrv9009/zcu102/system_bd.tcl
View File

@ -1,9 +1,12 @@
## FIFO depth is 18Mb - 1M samples
set dac_fifo_name axi_adrv9009_dacfifo
set dac_fifo_address_width 14
set dac_fifo_address_width 17
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl

3
projects/adrv9009/zcu102/system_project.tcl
View File

@ -10,5 +10,8 @@ adi_project_files adrv9009_zcu102 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
## To improve timing of the BRAM buffers
set_property strategy Performance_RefinePlacement [get_runs impl_1]
adi_project_run adrv9009_zcu102