zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcomms11: Update the clock tree 

- one single reference clock for both rx and tx channels
  - delete the SYSREF inputs
  - update the IO location of the usr_clk
main
Istvan Csomortani 2018-01-29 18:44:15 +02:00
parent ff562e7165
commit 55b4603e60
2 changed files with 15 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
projects/fmcomms11/zc706/system_constr.xdc
View File

@ -1,8 +1,6 @@
# fmcomms11
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
@ -22,8 +20,8 @@ set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[7]]
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AD10} [get_ports trx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports trx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P
@ -43,10 +41,8 @@ set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[7]]
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_p] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_n] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9625] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9162] ; ## G12 FMC_HPC_LA08_P
@ -65,8 +61,7 @@ set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_i
# clocks
create_clock -name tx_ref_clk -period 6.40 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 6.40 [get_ports rx_ref_clk_p]
create_clock -name rx_ref_clk -period 6.40 [get_ports trx_ref_clk_p]
create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]

38
projects/fmcomms11/zc706/system_top.v
View File

@ -93,22 +93,18 @@ module system_top (
inout iic_scl,
inout iic_sda,
input rx_ref_clk_p,
input rx_ref_clk_n,
output rx_sync_p,
output rx_sync_n,
input [ 7:0] rx_data_p,
input [ 7:0] rx_data_n,
input tx_ref_clk_p,
input tx_ref_clk_n,
input trx_ref_clk_p,
input trx_ref_clk_n,
input tx_sync_p,
input tx_sync_n,
output [ 7:0] tx_data_p,
output [ 7:0] tx_data_n,
input sysref_p,
input sysref_n,
input usr_clk_p,
input usr_clk_n,
@ -140,22 +136,13 @@ module system_top (
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sync;
wire tx_ref_clk;
wire trx_ref_clk;
wire tx_sync;
wire sysref;
wire usr_clk;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
@ -163,9 +150,9 @@ module system_top (
IBUFDS_GTE2 i_ibufds_tx_ref_clk (
.CEB (1'd0),
.I (tx_ref_clk_p),
.IB (tx_ref_clk_n),
.O (tx_ref_clk),
.I (trx_ref_clk_p),
.IB (trx_ref_clk_n),
.O (trx_ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_tx_sync (
@ -173,11 +160,6 @@ module system_top (
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
IBUFDS i_ibufds_usr_clk (
.I (usr_clk_p),
.IB (usr_clk_n),
@ -291,9 +273,9 @@ module system_top (
.rx_data_6_p (rx_data_p[6]),
.rx_data_7_n (rx_data_n[7]),
.rx_data_7_p (rx_data_p[7]),
.rx_ref_clk_0 (tx_ref_clk),
.rx_ref_clk_0 (trx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (sysref),
.rx_sysref_0 (1'b0),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
@ -332,9 +314,9 @@ module system_top (
.tx_data_6_p (tx_data_p[6]),
.tx_data_7_n (tx_data_n[7]),
.tx_data_7_p (tx_data_p[7]),
.tx_ref_clk_0 (tx_ref_clk),
.tx_ref_clk_0 (trx_ref_clk),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref));
.tx_sysref_0 (1'b0));
endmodule