diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile b/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile index af2a0ffcc..b6ad44a3e 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile @@ -16,6 +16,7 @@ GENERIC_DEPS += ../../common/up_axi.v GENERIC_DEPS += ../../common/up_clock_mon.v GENERIC_DEPS += ../../common/up_xfer_cntrl.v GENERIC_DEPS += ../../common/up_xfer_status.v +GENERIC_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v index ba94931a7..1323c7f01 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v @@ -85,6 +85,8 @@ module ad_ip_jesd204_tpl_adc #( localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8; localparam DMA_DATA_WIDTH = 16 * DATA_PATH_WIDTH * NUM_CHANNELS; + localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES); + wire [NUM_CHANNELS-1:0] dfmt_enable_s; wire [NUM_CHANNELS-1:0] dfmt_sign_extend_s; wire [NUM_CHANNELS-1:0] dfmt_type_s; @@ -97,7 +99,8 @@ module ad_ip_jesd204_tpl_adc #( ad_ip_jesd204_tpl_adc_regmap #( .ID (ID), .NUM_CHANNELS (NUM_CHANNELS), - .DATA_PATH_WIDTH (DATA_PATH_WIDTH) + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .NUM_PROFILES(1) ) i_regmap ( .s_axi_aclk (s_axi_aclk), .s_axi_aresetn (s_axi_aresetn), @@ -133,14 +136,22 @@ module ad_ip_jesd204_tpl_adc #( .enable (enable), - .adc_dovf (adc_dovf) + .adc_dovf (adc_dovf), + + .jesd_m (NUM_CHANNELS), + .jesd_l (NUM_LANES), + .jesd_s (SAMPLES_PER_FRAME), + .jesd_f (BYTES_PER_FRAME), + .jesd_n (CONVERTER_RESOLUTION), + .jesd_np (BITS_PER_SAMPLE), + .up_profile_sel () ); ad_ip_jesd204_tpl_adc_core #( .NUM_LANES (NUM_LANES), .NUM_CHANNELS (NUM_CHANNELS), .BITS_PER_SAMPLE (BITS_PER_SAMPLE), - .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME), .OCTETS_PER_BEAT (OCTETS_PER_BEAT), .LINK_DATA_WIDTH (LINK_DATA_WIDTH), diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl index 824333af3..48f979f7e 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl @@ -41,6 +41,7 @@ adi_ip_files ad_ip_jesd204_tpl_adc [list \ "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ "ad_ip_jesd204_tpl_adc_core.v" \ "ad_ip_jesd204_tpl_adc_channel.v" \ "ad_ip_jesd204_tpl_adc_deframer.v" \ diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index 9d4ffedee..a36e988c5 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -26,7 +26,8 @@ module ad_ip_jesd204_tpl_adc_regmap #( parameter ID = 0, parameter NUM_CHANNELS = 1, - parameter DATA_PATH_WIDTH = 1 + parameter DATA_PATH_WIDTH = 1, + parameter NUM_PROFILES = 1 // Number of supported JESD profiles ) ( // axi interface input s_axi_aclk, @@ -67,7 +68,17 @@ module ad_ip_jesd204_tpl_adc_regmap #( output [NUM_CHANNELS-1:0] enable, // Underflow - input adc_dovf + input adc_dovf, + + // Deframer interface + input [NUM_PROFILES*8-1: 0] jesd_m, + input [NUM_PROFILES*8-1: 0] jesd_l, + input [NUM_PROFILES*8-1: 0] jesd_s, + input [NUM_PROFILES*8-1: 0] jesd_f, + input [NUM_PROFILES*8-1: 0] jesd_n, + input [NUM_PROFILES*8-1: 0] jesd_np, + + output [$clog2(NUM_PROFILES):0] up_profile_sel ); localparam [31:0] CLK_RATIO = DATA_PATH_WIDTH; @@ -91,11 +102,11 @@ module ad_ip_jesd204_tpl_adc_regmap #( wire up_wreq_s; wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; - wire [NUM_CHANNELS:0] up_wack_s; + wire [NUM_CHANNELS+1:0] up_wack_s; wire up_rreq_s; wire [13:0] up_raddr_s; - wire [31:0] up_rdata_s[0:NUM_CHANNELS]; - wire [NUM_CHANNELS:0] up_rack_s; + wire [31:0] up_rdata_s[0:NUM_CHANNELS+1]; + wire [NUM_CHANNELS+1:0] up_rack_s; wire [NUM_CHANNELS-1:0] up_adc_pn_err_s; wire [NUM_CHANNELS-1:0] up_adc_pn_oos_s; @@ -155,7 +166,7 @@ module ad_ip_jesd204_tpl_adc_regmap #( always @(*) begin up_rdata_all = 'h00; - for (n = 0; n <= NUM_CHANNELS; n = n + 1) begin + for (n = 0; n <= NUM_CHANNELS+1; n = n + 1) begin up_rdata_all = up_rdata_all | up_rdata_s[n]; end end @@ -290,4 +301,31 @@ module ad_ip_jesd204_tpl_adc_regmap #( end endgenerate + up_tpl_common #( + .COMMON_ID(4'h3), // Offset of regmap + .NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles + ) i_up_tpl_adc ( + + .jesd_m (jesd_m), + .jesd_l (jesd_l), + .jesd_s (jesd_s), + .jesd_f (jesd_f), + .jesd_n (jesd_n), + .jesd_np (jesd_np), + + .up_profile_sel (up_profile_sel), + + // bus interface + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[NUM_CHANNELS+1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[NUM_CHANNELS+1]), + .up_rack (up_rack_s[NUM_CHANNELS+1]) + ); endmodule diff --git a/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v b/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v new file mode 100644 index 000000000..44e9265f4 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v @@ -0,0 +1,141 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_tpl_common #( + + // parameters + parameter COMMON_ID = 4'hF, // Offset of regmap + parameter NUM_PROFILES = 1 // Number of JESD profiles + )( + + input [NUM_PROFILES*8-1: 0] jesd_m, + input [NUM_PROFILES*8-1: 0] jesd_l, + input [NUM_PROFILES*8-1: 0] jesd_s, + input [NUM_PROFILES*8-1: 0] jesd_f, + input [NUM_PROFILES*8-1: 0] jesd_n, + input [NUM_PROFILES*8-1: 0] jesd_np, + + output reg [$clog2(NUM_PROFILES):0] up_profile_sel = 'h0, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal registers + reg up_rack_int = 'd0; + reg up_wack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + + // internal signals + wire up_wreq_s; + wire up_rreq_s; + reg [31:0] up_rdata_jesd_params; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0; + + // processor write interface + + assign up_wack = up_wack_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + up_profile_sel <= 'd0; + end else begin + up_wack_int <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h00)) begin + up_profile_sel <= up_wdata[$clog2(NUM_PROFILES):0]; + end + end + end + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata_int <= up_profile_sel; + 8'h01: up_rdata_int <= NUM_PROFILES; + default: up_rdata_int <= up_rdata_jesd_params; + endcase + end else begin + up_rdata_int <= 32'd0; + end + end + end + + integer i; + always @(*) begin + for (i=0; i