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ad4630_fmc: Match project name with folder name

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Stanca Pop 2022-09-23 13:45:35 +03:00 committed by StancaPop
parent d2d32458f4
commit 56290a609d
4 changed files with 19 additions and 27 deletions
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2
projects/ad4630_fmc/zed/Makefile
View File

@ -4,7 +4,7 @@
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad463x_fmc_zed
PROJECT_NAME := ad4630_fmc_zed
M_DEPS += system_constr_8sdi.xdc
M_DEPS += system_constr_4sdi.xdc

5
projects/ad4630_fmc/zed/system_bd.tcl
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@ -3,10 +3,9 @@ source $ad_hdl_dir/projects/scripts/adi_pd.tcl
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
# add RTL source that will be instantiated in system_bd directly
adi_project_files ad463x_fmc_zed [list \
adi_project_files ad4630_fmc_zed [list \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
]
"$ad_hdl_dir/library/util_cdc/sync_bits.v" ]
# block design
source ../common/ad463x_bd.tcl

37
projects/ad4630_fmc/zed/system_project.tcl
View File

@ -44,48 +44,41 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# make NUM_OF_SDI=2 CAPTURE_ZONE=2
#
adi_project ad463x_fmc_zed 0 [list \
adi_project ad4630_fmc_zed 0 [list \
CLK_MODE [get_env_param CLK_MODE 0] \
NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \
CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \
DDR_EN [get_env_param DDR_EN 0] \
]
DDR_EN [get_env_param DDR_EN 0] ]
adi_project_files ad463x_fmc_zed [list \
adi_project_files ad4630_fmc_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"system_constr.xdc" \
"system_top.v" \
]
"system_top.v" ]
switch [get_env_param NUM_OF_SDI 4] {
1 {
adi_project_files ad463x_fmc_zed [list \
"system_constr_1sdi.xdc"
]
adi_project_files ad4630_fmc_zed [list \
"system_constr_1sdi.xdc" ]
}
2 {
adi_project_files ad463x_fmc_zed [list \
"system_constr_2sdi.xdc"
]
adi_project_files ad4630_fmc_zed [list \
"system_constr_2sdi.xdc" ]
}
4 {
adi_project_files ad463x_fmc_zed [list \
"system_constr_4sdi.xdc"
]
adi_project_files ad4630_fmc_zed [list \
"system_constr_4sdi.xdc" ]
}
8 {
adi_project_files ad463x_fmc_zed [list \
"system_constr_8sdi.xdc"
]
adi_project_files ad4630_fmc_zed [list \
"system_constr_8sdi.xdc" ]
}
default {
adi_project_files ad463x_fmc_zed [list \
"system_constr_2sdi.xdc"
]
adi_project_files ad4630_fmc_zed [list \
"system_constr_2sdi.xdc" ]
}
}
adi_project_run ad463x_fmc_zed
adi_project_run ad4630_fmc_zed

2
projects/ad4630_fmc/zed/system_top.v
View File

@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are