From 563710e90472f22064f39fafaee76989b7d4ff5c Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 3 Jul 2018 12:11:58 +0100 Subject: [PATCH] daq3: ZCU102: Fixed system_top to be similar with ZC706. Updated constraints to specify exactly transceiver pin locations --- projects/daq3/zcu102/system_constr.xdc | 52 +++++++++++++------------- projects/daq3/zcu102/system_top.v | 38 ++++++++++--------- 2 files changed, 47 insertions(+), 43 deletions(-) diff --git a/projects/daq3/zcu102/system_constr.xdc b/projects/daq3/zcu102/system_constr.xdc index 283d78e9a..1eaf4ace8 100644 --- a/projects/daq3/zcu102/system_constr.xdc +++ b/projects/daq3/zcu102/system_constr.xdc @@ -33,13 +33,13 @@ set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports adc_fdb] set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC0_LA07_P set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC0_LA07_N -set_property LOC GTHE4_COMMON_X1Y1 [get_cells -hierarchical -filter {NAME =~ *i_ibufds_rx_ref_clk}] -set_property LOC GTHE4_COMMON_X1Y2 [get_cells -hierarchical -filter {NAME =~ *i_ibufds_tx_ref_clk}] +#set_property LOC GTHE5_COMMON_X1Y1 [get_cells -hierarchical -filter {NAME =~ *i_ibufds_rx_ref_clk}] +#set_property LOC GTHE4_COMMON_X1Y2 [get_cells -hierarchical -filter {NAME =~ *i_ibufds_tx_ref_clk}] -set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel}] -set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_1/i_gthe4_channel}] -set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe4_channel}] -set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe4_channel}] +#set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel}] +#set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_1/i_gthe4_channel}] +#set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe4_channel}] +#set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe4_channel}] # clocks @@ -50,25 +50,25 @@ create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_ # pin assignments below are for reference only and are ignored by the tool! -# set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P -# set_property -dict {PACKAGE_PIN L7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_N -# set_property -dict {PACKAGE_PIN G8 } [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P -# set_property -dict {PACKAGE_PIN G7 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N +set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P +set_property -dict {PACKAGE_PIN L7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_N +set_property -dict {PACKAGE_PIN G8 } [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P +set_property -dict {PACKAGE_PIN G7 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N -# set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC0_DP3_M2C_P -# set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC0_DP3_M2C_N -# set_property -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC0_DP0_M2C_P -# set_property -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC0_DP0_M2C_N -# set_property -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC0_DP2_M2C_P -# set_property -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC0_DP2_M2C_N -# set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC0_DP1_M2C_P -# set_property -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC0_DP1_M2C_N +set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC0_DP3_M2C_P +set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC0_DP3_M2C_N +set_property -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC0_DP0_M2C_P +set_property -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC0_DP0_M2C_N +set_property -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC0_DP2_M2C_P +set_property -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC0_DP2_M2C_N +set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC0_DP1_M2C_P +set_property -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC0_DP1_M2C_N -# set_property -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC0_DP3_C2M_P (tx_data_p[0]) -# set_property -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC0_DP3_C2M_N (tx_data_n[0]) -# set_property -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[1]] ; ## C02 FMC_HPC0_DP0_C2M_P (tx_data_p[3]) -# set_property -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC0_DP0_C2M_N (tx_data_n[3]) -# set_property -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC0_DP2_C2M_P (tx_data_p[1]) -# set_property -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC0_DP2_C2M_N (tx_data_n[1]) -# set_property -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC0_DP1_C2M_P (tx_data_p[2]) -# set_property -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC0_DP1_C2M_N (tx_data_n[2]) +set_property -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC0_DP3_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC0_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[1]] ; ## C02 FMC_HPC0_DP0_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC0_DP0_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC0_DP2_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC0_DP2_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC0_DP1_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC0_DP1_C2M_N (tx_data_n[2]) diff --git a/projects/daq3/zcu102/system_top.v b/projects/daq3/zcu102/system_top.v index 83769f8d3..151a0bc87 100644 --- a/projects/daq3/zcu102/system_top.v +++ b/projects/daq3/zcu102/system_top.v @@ -82,6 +82,8 @@ module system_top ( wire [94:0] gpio_i; wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [20:0] gpio_bd; wire [ 2:0] spi_csn; wire spi_mosi; wire spi_miso; @@ -144,7 +146,7 @@ module system_top ( .spi_dir (spi_dir)); OBUFDS i_obufds_sysref ( - .I (gpio_o[43]), + .I (gpio_o[40]), .O (sysref_p), .OB (sysref_n)); @@ -153,27 +155,29 @@ module system_top ( .IB (trig_n), .O (trig)); - assign adc_pd = gpio_o[42]; - assign dac_txen = gpio_o[41]; - assign dac_reset = gpio_o[40]; - assign clkd_sync = gpio_o[38]; - assign gpio_bd_o = gpio_o[7:0]; + assign gpio_i[94:40] = gpio_o[94:40]; + assign gpio_i[39] = trig; - assign gpio_i[94:44] = 'h0; - assign gpio_i[43:43] = trig; - assign gpio_i[42:37] = 'h0; - assign gpio_i[36:36] = adc_fdb; - assign gpio_i[35:35] = adc_fda; - assign gpio_i[34:34] = dac_irq; - assign gpio_i[33:32] = clkd_status; - assign gpio_i[31:21] = 'h0; - assign gpio_i[20: 8] = gpio_bd_i; - assign gpio_i[ 7: 0] = 'h0; + ad_iobuf #(.DATA_WIDTH(7)) i_iobuf ( + .dio_t (gpio_t[38:32]), + .dio_i (gpio_o[38:32]), + .dio_o (gpio_i[38:32]), + .dio_p ({ adc_pd, // 38 + dac_txen, // 37 + adc_fdb, // 36 + adc_fda, // 35 + dac_irq, // 34 + clkd_status})); // 32 + + assign gpio_i[31:21] = gpio_o[31:21]; + + assign gpio_bd_i = gpio_bd[20:8]; + assign gpio_bd_o = gpio_bd[ 7:0]; system_wrapper i_system_wrapper ( .gpio_i (gpio_i), .gpio_o (gpio_o), - .gpio_t (), + .gpio_t (gpio_t), .rx_data_0_n (rx_data_n[0]), .rx_data_0_p (rx_data_p[0]), .rx_data_1_n (rx_data_n[1]),