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usdrx1: Added synchronization, updated constraints, added timing check for a5gt project

main
Adrian Costina 2014-10-29 19:29:42 +02:00
parent cc265b6b9c
commit 56374cf592
4 changed files with 102 additions and 35 deletions
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78
projects/usdrx1/a5gt/system_bd.qsys
View File

@ -180,14 +180,6 @@
type = "String";
}
}
element sys_gpio.s1
{
datum baseAddress
{
value = "86025408";
type = "String";
}
}
element sys_timer.s1
{
datum baseAddress
@ -209,14 +201,6 @@
type = "String";
}
}
element sys_tcm_mem.s1
{
datum baseAddress
{
value = "86016000";
type = "String";
}
}
element sys_ethernet_desc_mem.s1
{
datum baseAddress
@ -225,6 +209,22 @@
type = "String";
}
}
element sys_gpio.s1
{
datum baseAddress
{
value = "86025408";
type = "String";
}
}
element sys_tcm_mem.s1
{
datum baseAddress
{
value = "86016000";
type = "String";
}
}
element sys_tcm_mem.s2
{
datum baseAddress
@ -246,14 +246,6 @@
type = "String";
}
}
element axi_ad9671_2.s_axi
{
datum baseAddress
{
value = "86114304";
type = "String";
}
}
element axi_ad9671_3.s_axi
{
datum baseAddress
@ -262,6 +254,14 @@
type = "String";
}
}
element axi_ad9671_2.s_axi
{
datum baseAddress
{
value = "86114304";
type = "String";
}
}
element axi_ad9671_0.s_axi
{
datum baseAddress
@ -846,6 +846,26 @@
type="conduit"
dir="end" />
<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
<interface
name="axi_ad9671_1_xcvr_sync"
internal="axi_ad9671_1.xcvr_sync"
type="conduit"
dir="end" />
<interface
name="axi_ad9671_0_xcvr_sync"
internal="axi_ad9671_0.xcvr_sync"
type="conduit"
dir="end" />
<interface
name="axi_ad9671_2_xcvr_sync"
internal="axi_ad9671_2.xcvr_sync"
type="conduit"
dir="end" />
<interface
name="axi_ad9671_3_xcvr_sync"
internal="axi_ad9671_3.xcvr_sync"
type="conduit"
dir="end" />
<module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
@ -2089,31 +2109,27 @@
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>
<module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_1">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_ID" value="1" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>
<module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_2">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_ID" value="2" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>
<module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_3">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_ID" value="3" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>

22
projects/usdrx1/a5gt/system_constr.sdc
View File

@ -1,9 +1,29 @@
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_ports {eth_tx_clk_out}]
create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set_clock_groups -asynchronous -group [get_clocks {n_clk_80m} ]
set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
set_false_path -from {sys_resetn} -to *
set_false_path -from * -to {sys_resetn}

17
projects/usdrx1/a5gt/system_timing.tcl
View File

@ -1,3 +1,16 @@
report_timing -detail path_only -npaths 20 -file timing_impl.log
set worst_path [get_timing_paths -npaths 1 -setup]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
if {$slack > 0} {
set worst_path [get_timing_paths -npaths 1 -hold]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
}
if {$slack < 0} {
use_this_invalid_command_to_crash
}

20
projects/usdrx1/a5gt/system_top.v
View File

@ -280,6 +280,8 @@ module system_top (
wire rx_pll_locked_s;
wire [ 22:0] rx_xcvr_status_s;
wire [ 7:0] rx_data_sof;
wire [ 3:0] sync_raddr;
wire sync_signal;
// ethernet transmit clock
@ -503,7 +505,23 @@ module system_top (
.axi_ad9671_3_adc_dma_if_enable (adc_enable_3),
.axi_ad9671_3_adc_dma_if_data (adc_data_3),
.axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3),
.axi_ad9671_3_adc_dma_if_dunf (1'b0));
.axi_ad9671_3_adc_dma_if_dunf (1'b0),
.axi_ad9671_0_xcvr_sync_sync_in (),
.axi_ad9671_0_xcvr_sync_sync_out (sync_signal),
.axi_ad9671_0_xcvr_sync_raddr_in (),
.axi_ad9671_0_xcvr_sync_raddr_out (sync_raddr),
.axi_ad9671_1_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_1_xcvr_sync_sync_out (),
.axi_ad9671_1_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_1_xcvr_sync_raddr_out(),
.axi_ad9671_2_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_2_xcvr_sync_sync_out (),
.axi_ad9671_2_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_2_xcvr_sync_raddr_out (),
.axi_ad9671_3_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_3_xcvr_sync_sync_out (),
.axi_ad9671_3_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_3_xcvr_sync_raddr_out ());
endmodule