From 56374cf59238413a9f7c5f3bd379199661f073e7 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 29 Oct 2014 19:29:42 +0200 Subject: [PATCH] usdrx1: Added synchronization, updated constraints, added timing check for a5gt project --- projects/usdrx1/a5gt/system_bd.qsys | 78 ++++++++++++++++---------- projects/usdrx1/a5gt/system_constr.sdc | 22 +++++++- projects/usdrx1/a5gt/system_timing.tcl | 17 +++++- projects/usdrx1/a5gt/system_top.v | 20 ++++++- 4 files changed, 102 insertions(+), 35 deletions(-) diff --git a/projects/usdrx1/a5gt/system_bd.qsys b/projects/usdrx1/a5gt/system_bd.qsys index 38aeea349..1af6d54da 100644 --- a/projects/usdrx1/a5gt/system_bd.qsys +++ b/projects/usdrx1/a5gt/system_bd.qsys @@ -180,14 +180,6 @@ type = "String"; } } - element sys_gpio.s1 - { - datum baseAddress - { - value = "86025408"; - type = "String"; - } - } element sys_timer.s1 { datum baseAddress @@ -209,14 +201,6 @@ type = "String"; } } - element sys_tcm_mem.s1 - { - datum baseAddress - { - value = "86016000"; - type = "String"; - } - } element sys_ethernet_desc_mem.s1 { datum baseAddress @@ -225,6 +209,22 @@ type = "String"; } } + element sys_gpio.s1 + { + datum baseAddress + { + value = "86025408"; + type = "String"; + } + } + element sys_tcm_mem.s1 + { + datum baseAddress + { + value = "86016000"; + type = "String"; + } + } element sys_tcm_mem.s2 { datum baseAddress @@ -246,14 +246,6 @@ type = "String"; } } - element axi_ad9671_2.s_axi - { - datum baseAddress - { - value = "86114304"; - type = "String"; - } - } element axi_ad9671_3.s_axi { datum baseAddress @@ -262,6 +254,14 @@ type = "String"; } } + element axi_ad9671_2.s_axi + { + datum baseAddress + { + value = "86114304"; + type = "String"; + } + } element axi_ad9671_0.s_axi { datum baseAddress @@ -846,6 +846,26 @@ type="conduit" dir="end" /> + + + + @@ -2089,31 +2109,27 @@ - - + - - + - - + - diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc index 646fb2dbe..578df95d7 100644 --- a/projects/usdrx1/a5gt/system_constr.sdc +++ b/projects/usdrx1/a5gt/system_constr.sdc @@ -1,9 +1,29 @@ +create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}] +create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_ports {eth_tx_clk_out}] create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}] create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}] - derive_pll_clocks derive_clock_uncertainty +set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} +set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} +set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} +set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} +set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} +set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} +set_clock_groups -asynchronous -group [get_clocks {n_clk_80m} ] +set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ] +set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ] +set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ] +set_clock_groups -asynchronous -group [get_clocks $clk_100m ] +set_clock_groups -asynchronous -group [get_clocks $clk_166m ] +set_clock_groups -asynchronous -group [get_clocks $clk_125m ] +set_clock_groups -asynchronous -group [get_clocks $clk_25m ] +set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ] +set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ] + +set_false_path -from {sys_resetn} -to * +set_false_path -from * -to {sys_resetn} diff --git a/projects/usdrx1/a5gt/system_timing.tcl b/projects/usdrx1/a5gt/system_timing.tcl index e1f355d44..a62293897 100644 --- a/projects/usdrx1/a5gt/system_timing.tcl +++ b/projects/usdrx1/a5gt/system_timing.tcl @@ -1,3 +1,16 @@ -report_timing -detail path_only -npaths 20 -file timing_impl.log - +set worst_path [get_timing_paths -npaths 1 -setup] +foreach_in_collection path $worst_path { + set slack [get_path_info $path -slack] +} + +if {$slack > 0} { + set worst_path [get_timing_paths -npaths 1 -hold] + foreach_in_collection path $worst_path { + set slack [get_path_info $path -slack] + } +} + +if {$slack < 0} { + use_this_invalid_command_to_crash +} diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v index c77a10bc5..9b6da1702 100644 --- a/projects/usdrx1/a5gt/system_top.v +++ b/projects/usdrx1/a5gt/system_top.v @@ -280,6 +280,8 @@ module system_top ( wire rx_pll_locked_s; wire [ 22:0] rx_xcvr_status_s; wire [ 7:0] rx_data_sof; + wire [ 3:0] sync_raddr; + wire sync_signal; // ethernet transmit clock @@ -503,7 +505,23 @@ module system_top ( .axi_ad9671_3_adc_dma_if_enable (adc_enable_3), .axi_ad9671_3_adc_dma_if_data (adc_data_3), .axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3), - .axi_ad9671_3_adc_dma_if_dunf (1'b0)); + .axi_ad9671_3_adc_dma_if_dunf (1'b0), + .axi_ad9671_0_xcvr_sync_sync_in (), + .axi_ad9671_0_xcvr_sync_sync_out (sync_signal), + .axi_ad9671_0_xcvr_sync_raddr_in (), + .axi_ad9671_0_xcvr_sync_raddr_out (sync_raddr), + .axi_ad9671_1_xcvr_sync_sync_in (sync_signal), + .axi_ad9671_1_xcvr_sync_sync_out (), + .axi_ad9671_1_xcvr_sync_raddr_in (sync_raddr), + .axi_ad9671_1_xcvr_sync_raddr_out(), + .axi_ad9671_2_xcvr_sync_sync_in (sync_signal), + .axi_ad9671_2_xcvr_sync_sync_out (), + .axi_ad9671_2_xcvr_sync_raddr_in (sync_raddr), + .axi_ad9671_2_xcvr_sync_raddr_out (), + .axi_ad9671_3_xcvr_sync_sync_in (sync_signal), + .axi_ad9671_3_xcvr_sync_sync_out (), + .axi_ad9671_3_xcvr_sync_raddr_in (sync_raddr), + .axi_ad9671_3_xcvr_sync_raddr_out ()); endmodule