From 56691bd440f3765be2c953462b361a8718308981 Mon Sep 17 00:00:00 2001 From: PopPaul2021 Date: Thu, 29 Sep 2022 11:31:57 +0300 Subject: [PATCH] projects/cn0501: Updated with axi_ad7768 IP for Coraz7s --- projects/cn0501/Readme.md | 10 +- projects/cn0501/common/cn0501_bd.tcl | 154 ++++++--------------- projects/cn0501/coraz7s/Makefile | 4 +- projects/cn0501/coraz7s/system_bd.tcl | 7 +- projects/cn0501/coraz7s/system_constr.xdc | 41 +++--- projects/cn0501/coraz7s/system_project.tcl | 13 +- projects/cn0501/coraz7s/system_top.v | 119 ++++------------ 7 files changed, 108 insertions(+), 240 deletions(-) diff --git a/projects/cn0501/Readme.md b/projects/cn0501/Readme.md index ec701879a..8088a18a3 100755 --- a/projects/cn0501/Readme.md +++ b/projects/cn0501/Readme.md @@ -1,8 +1,8 @@ # CN0501 HDL Project Here are some pointers to help you: - * [Board Product Page](https://www.analog.com/cn0501) - * Parts : []() - * Project Doc: - * HDL Doc: - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all + * [Board Product Page](https://www.analog.com/en/products/cn0501.html) + * Parts : [CN0501-geophone](https://www.analog.com/en/products/cn0501.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501 + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501 + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl \ No newline at end of file diff --git a/projects/cn0501/common/cn0501_bd.tcl b/projects/cn0501/common/cn0501_bd.tcl index ea2876c24..e9e19a573 100644 --- a/projects/cn0501/common/cn0501_bd.tcl +++ b/projects/cn0501/common/cn0501_bd.tcl @@ -1,129 +1,63 @@ - # ad7768 interface -create_bd_port -dir I adc_clk -create_bd_port -dir I adc_valid -create_bd_port -dir I adc_valid_pp -create_bd_port -dir I adc_sync -create_bd_port -dir I -from 31 -to 0 adc_data -create_bd_port -dir I -from 31 -to 0 adc_data_0 -create_bd_port -dir I -from 31 -to 0 adc_data_1 -create_bd_port -dir I -from 31 -to 0 adc_data_2 -create_bd_port -dir I -from 31 -to 0 adc_data_3 -create_bd_port -dir I -from 31 -to 0 adc_data_4 -create_bd_port -dir I -from 31 -to 0 adc_data_5 -create_bd_port -dir I -from 31 -to 0 adc_data_6 -create_bd_port -dir I -from 31 -to 0 adc_data_7 -create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i -create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o -create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t -create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i -create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o -create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t +create_bd_port -dir I clk_in +create_bd_port -dir I ready_in +create_bd_port -dir I -from 7 -to 0 data_in -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io +# adc(cn0501-dma) -# instances +ad_ip_instance axi_dmac cn0501_dma +ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter cn0501_dma CONFIG.CYCLIC 0 +ad_ip_parameter cn0501_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter cn0501_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_SRC 256 +ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_DEST 64 -ad_ip_instance axi_dmac ad7768_dma -ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_SRC 2 -ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter ad7768_dma CONFIG.CYCLIC 0 -ad_ip_parameter ad7768_dma CONFIG.SYNC_TRANSFER_START 1 -ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter ad7768_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter ad7768_dma CONFIG.DMA_DATA_WIDTH_SRC 32 +# axi_ad77684 -ad_ip_instance axi_dmac ad7768_dma_2 -ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_SRC 2 -ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter ad7768_dma_2 CONFIG.CYCLIC 0 -ad_ip_parameter ad7768_dma_2 CONFIG.SYNC_TRANSFER_START 1 -ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter ad7768_dma_2 CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter ad7768_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 256 - -# ps7-hp1 - -ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1 - -# gpio - -ad_ip_instance axi_gpio ad7768_gpio -ad_ip_parameter ad7768_gpio CONFIG.C_IS_DUAL 1 -ad_ip_parameter ad7768_gpio CONFIG.C_GPIO_WIDTH 32 -ad_ip_parameter ad7768_gpio CONFIG.C_GPIO2_WIDTH 32 -ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1 - -#i2c - -ad_ip_instance axi_iic axi_iic_0 +ad_ip_instance axi_ad7768 axi_ad7768_adc +ad_ip_parameter axi_ad7768_adc CONFIG.NUM_CHANNELS 8 # adc-path channel pack -ad_ip_instance util_cpack2 util_ad7768_adc_pack -ad_ip_parameter util_ad7768_adc_pack CONFIG.NUM_OF_CHANNELS 8 -ad_ip_parameter util_ad7768_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32 +ad_ip_instance util_cpack2 cn0501_adc_pack +ad_ip_parameter cn0501_adc_pack CONFIG.NUM_OF_CHANNELS 8 +ad_ip_parameter cn0501_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32 -ad_connect adc_clk util_ad7768_adc_pack/clk -ad_connect sys_rstgen/peripheral_reset util_ad7768_adc_pack/reset -ad_connect adc_valid_pp util_ad7768_adc_pack/fifo_wr_en +# connections for {set i 0} {$i < 8} {incr i} { - ad_connect adc_data_$i util_ad7768_adc_pack/fifo_wr_data_$i + ad_connect axi_ad7768_adc/adc_enable_$i cn0501_adc_pack/enable_$i + ad_connect axi_ad7768_adc/adc_data_$i cn0501_adc_pack/fifo_wr_data_$i } -# axi_generic_adc +ad_connect axi_ad7768_adc/s_axi_aclk sys_ps7/FCLK_CLK0 +ad_connect axi_ad7768_adc/clk_in clk_in +ad_connect axi_ad7768_adc/ready_in ready_in +ad_connect axi_ad7768_adc/data_in data_in +ad_connect axi_ad7768_adc/adc_valid cn0501_adc_pack/fifo_wr_en +ad_connect axi_ad7768_adc/adc_clk cn0501_adc_pack/clk +ad_connect axi_ad7768_adc/adc_reset cn0501_adc_pack/reset +ad_connect axi_ad7768_adc/adc_dovf cn0501_adc_pack/fifo_wr_overflow -ad_ip_instance axi_generic_adc axi_ad7768_adc -ad_ip_parameter axi_ad7768_adc CONFIG.NUM_OF_CHANNELS 8 - -for {set i 0} {$i < 8} {incr i} { - ad_ip_instance xlslice xlslice_$i - set_property -dict [list CONFIG.DIN_FROM $i CONFIG.DIN_WIDTH {8} CONFIG.DOUT_WIDTH {1} CONFIG.DIN_TO $i] [get_bd_cells xlslice_$i] - ad_connect axi_ad7768_adc/adc_enable xlslice_$i/Din - ad_connect xlslice_$i/Dout util_ad7768_adc_pack/enable_$i -} - -# interconnects - -ad_connect adc_clk ad7768_dma/fifo_wr_clk -ad_connect adc_valid ad7768_dma/fifo_wr_en -ad_connect adc_sync ad7768_dma/fifo_wr_sync -ad_connect adc_data ad7768_dma/fifo_wr_din -ad_connect adc_clk ad7768_dma_2/fifo_wr_clk -ad_connect sys_cpu_resetn ad7768_dma/m_dest_axi_aresetn -ad_connect sys_cpu_resetn ad7768_dma_2/m_dest_axi_aresetn -ad_connect util_ad7768_adc_pack/packed_fifo_wr ad7768_dma_2/fifo_wr -ad_connect util_ad7768_adc_pack/fifo_wr_overflow axi_ad7768_adc/adc_dovf -ad_connect adc_clk axi_ad7768_adc/adc_clk -ad_connect sys_ps7/FCLK_CLK0 axi_ad7768_adc/s_axi_aclk -ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i -ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o -ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t -ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i -ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o -ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t - -ad_connect iic_0_io axi_iic_0/iic - -# interrupts - -ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq -ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt -ad_cpu_interrupt ps-11 mb-11 axi_iic_0/iic2intc_irpt -ad_cpu_interrupt ps-10 mb-10 ad7768_dma_2/irq +ad_connect cn0501_dma/s_axi_aclk $sys_cpu_clk +ad_connect cn0501_dma/m_dest_axi_aresetn $sys_cpu_resetn +ad_connect cn0501_dma/m_dest_axi_aclk $sys_cpu_clk +ad_connect cn0501_dma/fifo_wr_clk axi_ad7768_adc/adc_clk +ad_connect cn0501_dma/fifo_wr cn0501_adc_pack/packed_fifo_wr # cpu / memory interconnects -ad_cpu_interconnect 0x7C400000 ad7768_dma -ad_cpu_interconnect 0x7C420000 ad7768_gpio -ad_cpu_interconnect 0x7C440000 axi_iic_0 -ad_cpu_interconnect 0x7C480000 ad7768_dma_2 -ad_cpu_interconnect 0x43c00000 axi_ad7768_adc +ad_cpu_interconnect 0x44a00000 axi_ad7768_adc +ad_cpu_interconnect 0x44a30000 cn0501_dma -ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp0_interconnect sys_cpu_clk ad7768_dma/m_dest_axi -ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma_2/m_dest_axi +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_cpu_clk cn0501_dma/m_dest_axi + +# interrupts + +ad_cpu_interrupt "ps-13" "mb-13" cn0501_dma/irq diff --git a/projects/cn0501/coraz7s/Makefile b/projects/cn0501/coraz7s/Makefile index 2fe3acc92..b20d31193 100644 --- a/projects/cn0501/coraz7s/Makefile +++ b/projects/cn0501/coraz7s/Makefile @@ -11,10 +11,10 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl -M_DEPS += ../../ad7768evb/common/ad7768_if.v +M_DEPS += ../../../library/common/ad_iobuf.v +LIB_DEPS += axi_ad7768 LIB_DEPS += axi_dmac -LIB_DEPS += axi_generic_adc LIB_DEPS += axi_sysid LIB_DEPS += sysid_rom LIB_DEPS += util_pack/util_cpack2 diff --git a/projects/cn0501/coraz7s/system_bd.tcl b/projects/cn0501/coraz7s/system_bd.tcl index ce996c2c8..27071d213 100644 --- a/projects/cn0501/coraz7s/system_bd.tcl +++ b/projects/cn0501/coraz7s/system_bd.tcl @@ -1,5 +1,5 @@ - source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl +source ../common/cn0501_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl #system ID @@ -7,8 +7,5 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "sys rom custom string placeholder" + sysid_gen_sys_init_file $sys_cstring - -#set sys_dma_clk [get_bd_nets sys_dma_clk] - -source ../common/cn0501_bd.tcl diff --git a/projects/cn0501/coraz7s/system_constr.xdc b/projects/cn0501/coraz7s/system_constr.xdc index 031a8bc42..bcc405ea1 100644 --- a/projects/cn0501/coraz7s/system_constr.xdc +++ b/projects/cn0501/coraz7s/system_constr.xdc @@ -1,22 +1,25 @@ + set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in ]; ## P12.10 IO8 + set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in ]; ## P12.9 IO9 + + set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]]; ## P14.1 IO0 + set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]]; ## P14.2 IO1 + set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]]; ## P14.3 IO2 + set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]]; ## P14.4 IO3 + set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]]; ## P14.1 IO4 + set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]]; ## P14.2 IO5 + set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]]; ## P14.3 IO6 + set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]]; ## P14.4 IO7 + + set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn ]; ## P12.8 IO10 + set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11 + set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12 + set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13 -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in] ; ## IO8 -set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in] ; ## IO9 +set input_clock_period 31.25; # Period of input clock fMAX_DCLK=32MHz +set hold_time 8.5; +set setup_time 8.5; -set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]] ; ## IO7 -set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]] ; ## IO6 -set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]] ; ## IO5 -set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]] ; ## IO4 -set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]] ; ## IO3 -set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]] ; ## IO2 -set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]] ; ## IO1 -set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]] ; ## IO0 +create_clock -name adc_clk -period $input_clock_period [get_ports clk_in] -set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn] ; ## IO10 -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; ## IO13 -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi] ; ## IO11 -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso] ; ## IO12 - -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_sda] - -create_clock -name adc_clk -period 20 [get_ports clk_in] +set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay; diff --git a/projects/cn0501/coraz7s/system_project.tcl b/projects/cn0501/coraz7s/system_project.tcl index 3cb98e086..65cbf6aa6 100644 --- a/projects/cn0501/coraz7s/system_project.tcl +++ b/projects/cn0501/coraz7s/system_project.tcl @@ -1,4 +1,4 @@ - +# load script source ../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -6,10 +6,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project cn0501_coraz7s adi_project_files cn0501_coraz7s [list \ - "$ad_hdl_dir/projects/ad7768evb/common/ad7768_if.v" \ - "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \ - "system_top.v" \ - "system_constr.xdc" \ - ] - + "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" ] + adi_project_run cn0501_coraz7s diff --git a/projects/cn0501/coraz7s/system_top.v b/projects/cn0501/coraz7s/system_top.v index ff19b96bd..5e1bec5ed 100644 --- a/projects/cn0501/coraz7s/system_top.v +++ b/projects/cn0501/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -36,18 +36,17 @@ `timescale 1ns/100ps module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, inout ddr_cas_n, inout ddr_ck_n, inout ddr_ck_p, inout ddr_cke, inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, inout ddr_odt, inout ddr_ras_n, inout ddr_reset_n, @@ -55,20 +54,17 @@ module system_top ( inout fixed_io_ddr_vrn, inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, + inout [53:0] fixed_io_mio, inout fixed_io_ps_clk, inout fixed_io_ps_porb, inout fixed_io_ps_srstb, - inout [1:0] btn, - inout [5:0] led, - - inout iic_scl, - inout iic_sda, + inout [ 1:0] btn, + inout [ 5:0] led, input clk_in, input ready_in, - input [ 7:0] data_in, + input [ 7:0] data_in, output spi_csn, output spi_clk, @@ -78,94 +74,35 @@ module system_top ( // internal signals - wire adc_clk; - wire adc_valid; - wire adc_valid_pp; - wire adc_sync; - wire [31:0] adc_data; - wire [31:0] adc_data_0; - wire [31:0] adc_data_1; - wire [31:0] adc_data_2; - wire [31:0] adc_data_3; - wire [31:0] adc_data_4; - wire [31:0] adc_data_5; - wire [31:0] adc_data_6; - wire [31:0] adc_data_7; - wire up_sshot; - wire [ 1:0] up_format; - wire up_crc_enable; - wire up_crc_4_or_16_n; wire [63:0] adc_gpio_i; wire [63:0] adc_gpio_o; wire [63:0] adc_gpio_t; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire [ 1:0] iic_mux_scl_i_s; - wire [ 1:0] iic_mux_scl_o_s; - wire iic_mux_scl_t_s; - wire [ 1:0] iic_mux_sda_i_s; - wire [ 1:0] iic_mux_sda_o_s; - wire iic_mux_sda_t_s; - // use crystal + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_buttons ( + .dio_t(gpio_t[1:0]), + .dio_i(gpio_o[1:0]), + .dio_o(gpio_i[1:0]), + .dio_p(btn)); - assign up_sshot = gpio_o[36]; - assign up_format = gpio_o[35:34]; - assign up_crc_enable = gpio_o[33]; - assign up_crc_4_or_16_n = gpio_o[32]; + ad_iobuf #( + .DATA_WIDTH(6) + ) i_iobuf_leds ( + .dio_t(gpio_t[7:2]), + .dio_i(gpio_o[7:2]), + .dio_o(gpio_i[7:2]), + .dio_p(led)); - // instantiations + assign gpio_i[63:8] = gpio_o[63:8]; - assign gpio_i[36:32] = 5'b0; - assign gpio_i[39:37] = gpio_o[39:37]; - assign gpio_i[47:44] = gpio_o[47:44]; - assign gpio_i[63:53] = gpio_o[63:53]; - - ad7768_if i_ad7768_if ( + system_wrapper i_system_wrapper ( .clk_in (clk_in), .ready_in (ready_in), .data_in (data_in), - .adc_clk (adc_clk), - .adc_valid (adc_valid), - .adc_valid_pp (adc_valid_pp), - .adc_sync (adc_sync), - .adc_data (adc_data), - .adc_data_0 (adc_data_0), - .adc_data_1 (adc_data_1), - .adc_data_2 (adc_data_2), - .adc_data_3 (adc_data_3), - .adc_data_4 (adc_data_4), - .adc_data_5 (adc_data_5), - .adc_data_6 (adc_data_6), - .adc_data_7 (adc_data_7), - .up_sshot (up_sshot), - .up_format (up_format), - .up_crc_enable (up_crc_enable), - .up_crc_4_or_16_n (up_crc_4_or_16_n), - .up_status_clr (adc_gpio_o[32:0]), - .up_status (adc_gpio_i[32:0])); - - system_wrapper i_system_wrapper ( - .adc_clk (adc_clk), - .adc_data (adc_data), - .adc_data_0 (adc_data_0), - .adc_data_1 (adc_data_1), - .adc_data_2 (adc_data_2), - .adc_data_3 (adc_data_3), - .adc_data_4 (adc_data_4), - .adc_data_5 (adc_data_5), - .adc_data_6 (adc_data_6), - .adc_data_7 (adc_data_7), - .adc_gpio_0_i (adc_gpio_i[31:0]), - .adc_gpio_0_o (adc_gpio_o[31:0]), - .adc_gpio_0_t (adc_gpio_t[31:0]), - .adc_gpio_1_i (adc_gpio_i[63:32]), - .adc_gpio_1_o (adc_gpio_o[63:32]), - .adc_gpio_1_t (adc_gpio_t[63:32]), - .adc_valid (adc_valid), - .adc_valid_pp (adc_valid_pp), - .adc_sync (adc_sync), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), @@ -190,8 +127,6 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .iic_0_io_scl_io (iic_scl), - .iic_0_io_sda_io (iic_sda), .spi0_clk_i (1'b0), .spi0_clk_o (spi_clk), .spi0_csn_0_o (spi_csn),