From 56789abf2b85952f0deffffa78ac7667b6d97d96 Mon Sep 17 00:00:00 2001
From: Filip Gherman <Filip.Gherman@analog.com>
Date: Tue, 18 Oct 2022 16:21:34 +0300
Subject: [PATCH] docs/regmap: Added the new ADDRESS_HIGH registers to the DMAC
 regmap

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
---
 docs/regmap/adi_regmap_dmac.txt | 68 ++++++++++++++++++++++++++++++++-
 1 file changed, 67 insertions(+), 1 deletion(-)

diff --git a/docs/regmap/adi_regmap_dmac.txt b/docs/regmap/adi_regmap_dmac.txt
index 08027eddb..5716a3477 100644
--- a/docs/regmap/adi_regmap_dmac.txt
+++ b/docs/regmap/adi_regmap_dmac.txt
@@ -9,7 +9,7 @@ ENDTITLE
 REG
 0x000
 VERSION
-Version of the peripheral. Follows semantic versioning. Current version 4.03.61.
+Version of the peripheral. Follows semantic versioning. Current version 4.04.61.
 ENDREG
 
 FIELD
@@ -558,4 +558,70 @@ ENDFIELD
 ############################################################################################
 ############################################################################################
 
+REG
+0x124
+DEST_ADDRESS_HIGH
+ENDREG
 
+FIELD
+[31:0] 0x00000000
+DEST_ADDRESS_HIGH
+RW
+This register contains the HIGH segment of the destination address of the transfer.
+
+This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
+REG
+0x125
+SRC_ADDRESS_HIGH
+ENDREG
+
+FIELD
+[31:0] 0x00000000
+SRC_ADDRESS_HIGH
+RW
+This register contains the HIGH segment of the source address of the transfer.
+
+This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
+REG
+0x126
+CURRENT_DEST_ADDRESS_HIGH
+ENDREG
+
+FIELD
+[31:0] 0x00
+CURRENT_DEST_ADDRESS_HIGH
+RO
+HIGH segment of the address to which the next data sample is written to.
+
+This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
+REG
+0x127
+CURRENT_SRC_ADDRESS_HIGH
+ENDREG
+
+FIELD
+[31:0] 0x00
+CURRENT_SRC_ADDRESS_HIGH
+RO
+HIGH segment of the address from which the next data sample is read.
+
+This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
+ENDFIELD
+
+############################################################################################
+############################################################################################