diff --git a/projects/adrv9001/a10soc/Makefile b/projects/adrv9001/a10soc/Makefile new file mode 100644 index 000000000..8249e3d4f --- /dev/null +++ b/projects/adrv9001/a10soc/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9001_a10soc + +M_DEPS += ../common/adrv9001_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl +M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl + +LIB_DEPS += axi_adrv9001 +LIB_DEPS += axi_dmac +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_rfifo +LIB_DEPS += util_wfifo + +include ../../scripts/project-intel.mk diff --git a/projects/adrv9001/a10soc/system_constr.sdc b/projects/adrv9001/a10soc/system_constr.sdc new file mode 100644 index 000000000..f773b64fd --- /dev/null +++ b/projects/adrv9001/a10soc/system_constr.sdc @@ -0,0 +1,13 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] + +# In CMOS mode interface max frequency is 80MHz +create_clock -period "12.500 ns" -name rx1_clk [get_ports {rx1_dclk_out_p}] +create_clock -period "12.500 ns" -name rx2_clk [get_ports {rx2_dclk_out_p}] +create_clock -period "12.500 ns" -name tx1_clk [get_ports {tx1_dclk_out_p}] +create_clock -period "12.500 ns" -name tx2_clk [get_ports {tx2_dclk_out_p}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/adrv9001/a10soc/system_project.tcl b/projects/adrv9001/a10soc/system_project.tcl new file mode 100644 index 000000000..01f422ef7 --- /dev/null +++ b/projects/adrv9001/a10soc/system_project.tcl @@ -0,0 +1,100 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project adrv9001_a10soc + +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl + +# lane interface + +# Note: This projects requires a hardware rework to function correctly. +# The rework connects FMC header pins directly to the FPGA so that they can be +# accessed by the fabric. +# +# Changes required: +# R610: DNI -> R0 +# R611: DNI -> R0 +# R612: R0 -> DNI +# R613: R0 -> DNI +# R620: DNI -> R0 +# R632: DNI -> R0 +# R621: R0 -> DNI +# R633: R0 -> DNI + +## constraints +## adrv9001 +# +set_location_assignment PIN_E5 -to dev_clk_in ; ## FMCA_HPC_CLK0_M2C_P +set_location_assignment PIN_J10 -to dev_mcs_fpga_out_n ; ## FMCA_HPC_LA14_N +set_location_assignment PIN_J9 -to dev_mcs_fpga_out_p ; ## FMCA_HPC_LA14_P +set_location_assignment PIN_D6 -to dgpio_0 ; ## FMCA_HPC_LA16_P +set_location_assignment PIN_E6 -to dgpio_1 ; ## FMCA_HPC_LA16_N +set_location_assignment PIN_D5 -to dgpio_2 ; ## FMCA_HPC_LA15_N +set_location_assignment PIN_D9 -to dgpio_3 ; ## FMCA_HPC_LA11_N +set_location_assignment PIN_A13 -to dgpio_4 ; ## FMCA_HPC_LA09_N +set_location_assignment PIN_A8 -to dgpio_5 ; ## FMCA_HPC_LA10_N +set_location_assignment PIN_G1 -to dgpio_6 ; ## FMCA_HPC_LA27_P +set_location_assignment PIN_F2 -to dgpio_7 ; ## FMCA_HPC_LA26_P +set_location_assignment PIN_L5 -to dgpio_8 ; ## FMCA_HPC_LA28_P +set_location_assignment PIN_M5 -to dgpio_9 ; ## FMCA_HPC_LA28_N +set_location_assignment PIN_C9 -to dgpio_10 ; ## FMCA_HPC_LA11_P +set_location_assignment PIN_H2 -to dgpio_11 ; ## FMCA_HPC_LA27_N +set_location_assignment PIN_L9 -to fpga_mcs_in_n ; ## FMCA_HPC_LA32_N +set_location_assignment PIN_L8 -to fpga_mcs_in_p ; ## FMCA_HPC_LA32_P +set_location_assignment PIN_W6 -to fpga_ref_clk_n ; ## FMCA_HPC_CLK1_M2C_N +set_location_assignment PIN_W5 -to fpga_ref_clk_p ; ## FMCA_HPC_CLK1_M2C_P +set_location_assignment PIN_P9 -to gp_int ; ## FMCA_HPC_LA30_P +set_location_assignment PIN_J11 -to mode ; ## FMCA_HPC_LA13_P +set_location_assignment PIN_K11 -to reset_trx ; ## FMCA_HPC_LA13_N +set_location_assignment PIN_A7 -to rx1_enable ; ## FMCA_HPC_LA10_P +set_location_assignment PIN_G2 -to rx2_enable ; ## FMCA_HPC_LA26_N +set_location_assignment PIN_F5 -to sm_fan_tach ; ## FMCA_HPC_CLK0_M2C_N +set_location_assignment PIN_M12 -to spi_clk ; ## FMCA_HPC_LA12_P +set_location_assignment PIN_P10 -to spi_dio ; ## FMCA_HPC_LA29_N +set_location_assignment PIN_N13 -to spi_do ; ## FMCA_HPC_LA12_N +set_location_assignment PIN_D4 -to spi_en ; ## FMCA_HPC_LA15_P +set_location_assignment PIN_A12 -to tx1_enable ; ## FMCA_HPC_LA09_P +set_location_assignment PIN_N9 -to tx2_enable ; ## FMCA_HPC_LA29_P +set_location_assignment PIN_P8 -to vadj_err ; ## FMCA_HPC_LA31_P +set_location_assignment PIN_R8 -to platform_status ; ## FMCA_HPC_LA31_N +set_location_assignment PIN_H14 -to rx1_dclk_in_n ; ## FMCA_HPC_LA00_CC_N +set_location_assignment PIN_G14 -to rx1_dclk_in_p ; ## FMCA_HPC_LA00_CC_P +set_location_assignment PIN_D14 -to rx1_idata_in_n ; ## FMCA_HPC_LA03_N +set_location_assignment PIN_C14 -to rx1_idata_in_p ; ## FMCA_HPC_LA03_P +set_location_assignment PIN_H13 -to rx1_qdata_in_n ; ## FMCA_HPC_LA04_N +set_location_assignment PIN_H12 -to rx1_qdata_in_p ; ## FMCA_HPC_LA04_P +set_location_assignment PIN_D13 -to rx1_strobe_in_n ; ## FMCA_HPC_LA02_N +set_location_assignment PIN_C13 -to rx1_strobe_in_p ; ## FMCA_HPC_LA02_P +set_location_assignment PIN_G9 -to rx2_dclk_in_n ; ## FMCA_HPC_LA17_CC_N +set_location_assignment PIN_F9 -to rx2_dclk_in_p ; ## FMCA_HPC_LA17_CC_P +set_location_assignment PIN_C4 -to rx2_idata_in_n ; ## FMCA_HPC_LA20_N +set_location_assignment PIN_C3 -to rx2_idata_in_p ; ## FMCA_HPC_LA20_P +set_location_assignment PIN_G6 -to rx2_qdata_in_n ; ## FMCA_HPC_LA19_N +set_location_assignment PIN_G5 -to rx2_qdata_in_p ; ## FMCA_HPC_LA19_P +set_location_assignment PIN_D3 -to rx2_strobe_in_n ; ## FMCA_HPC_LA21_N +set_location_assignment PIN_C2 -to rx2_strobe_in_p ; ## FMCA_HPC_LA21_P +set_location_assignment PIN_B9 -to tx1_dclk_out_n ; ## FMCA_HPC_LA07_N +set_location_assignment PIN_A9 -to tx1_dclk_out_p ; ## FMCA_HPC_LA07_P +set_location_assignment PIN_E13 -to tx1_dclk_in_n ; ## FMCA_HPC_LA01_CC_N +set_location_assignment PIN_E12 -to tx1_dclk_in_p ; ## FMCA_HPC_LA01_CC_P +set_location_assignment PIN_B12 -to tx1_idata_out_n ; ## FMCA_HPC_LA08_N +set_location_assignment PIN_B11 -to tx1_idata_out_p ; ## FMCA_HPC_LA08_P +set_location_assignment PIN_F14 -to tx1_qdata_out_n ; ## FMCA_HPC_LA05_N +set_location_assignment PIN_F13 -to tx1_qdata_out_p ; ## FMCA_HPC_LA05_P +set_location_assignment PIN_B10 -to tx1_strobe_out_n ; ## FMCA_HPC_LA06_N +set_location_assignment PIN_A10 -to tx1_strobe_out_p ; ## FMCA_HPC_LA06_P +set_location_assignment PIN_G4 -to tx2_dclk_out_n ; ## FMCA_HPC_LA22_N +set_location_assignment PIN_F4 -to tx2_dclk_out_p ; ## FMCA_HPC_LA22_P +set_location_assignment PIN_H7 -to tx2_dclk_in_n ; ## FMCA_HPC_LA18_CC_N +set_location_assignment PIN_G7 -to tx2_dclk_in_p ; ## FMCA_HPC_LA18_CC_P +set_location_assignment PIN_D1 -to tx2_idata_out_n ; ## FMCA_HPC_LA23_N +set_location_assignment PIN_C1 -to tx2_idata_out_p ; ## FMCA_HPC_LA23_P +set_location_assignment PIN_F3 -to tx2_qdata_out_n ; ## FMCA_HPC_LA25_N +set_location_assignment PIN_E3 -to tx2_qdata_out_p ; ## FMCA_HPC_LA25_P +set_location_assignment PIN_E2 -to tx2_strobe_out_n ; ## FMCA_HPC_LA24_N +set_location_assignment PIN_E1 -to tx2_strobe_out_p ; ## FMCA_HPC_LA24_P + +execute_flow -compile + diff --git a/projects/adrv9001/a10soc/system_qsys.tcl b/projects/adrv9001/a10soc/system_qsys.tcl new file mode 100644 index 000000000..779ff9947 --- /dev/null +++ b/projects/adrv9001/a10soc/system_qsys.tcl @@ -0,0 +1,14 @@ +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source ../common/adrv9001_qsys.tcl + +set_instance_parameter_value sys_spi {clockPolarity} {1} + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +set sys_cstring "sys rom custom string placeholder"; +sysid_gen_sys_init_file $sys_cstring; diff --git a/projects/adrv9001/a10soc/system_top.v b/projects/adrv9001/a10soc/system_top.v new file mode 100644 index 000000000..d4ad92aac --- /dev/null +++ b/projects/adrv9001/a10soc/system_top.v @@ -0,0 +1,374 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // hps-ddr4 (32) + + input hps_ddr_ref_clk, + output [ 0:0] hps_ddr_clk_p, + output [ 0:0] hps_ddr_clk_n, + output [ 16:0] hps_ddr_a, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_reset_n, + output [ 0:0] hps_ddr_act_n, + output [ 0:0] hps_ddr_par, + input [ 0:0] hps_ddr_alert_n, + inout [ 3:0] hps_ddr_dqs_p, + inout [ 3:0] hps_ddr_dqs_n, + inout [ 31:0] hps_ddr_dq, + inout [ 3:0] hps_ddr_dbi_n, + input hps_ddr_rzq, + + // hps-ethernet + + input [ 0:0] hps_eth_rxclk, + input [ 0:0] hps_eth_rxctl, + input [ 3:0] hps_eth_rxd, + output [ 0:0] hps_eth_txclk, + output [ 0:0] hps_eth_txctl, + output [ 3:0] hps_eth_txd, + output [ 0:0] hps_eth_mdc, + inout [ 0:0] hps_eth_mdio, + + // hps-sdio + + output [ 0:0] hps_sdio_clk, + inout [ 0:0] hps_sdio_cmd, + inout [ 7:0] hps_sdio_d, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // hps-gpio (max-v-u16) + + inout [ 3:0] hps_gpio, + + // gpio (max-v-u21) + + input [ 7:0] gpio_bd_i, + output [ 3:0] gpio_bd_o, + + // adrv9001-interface + output spi_clk, + output spi_dio, + input spi_do, + output spi_en, + + input fpga_ref_clk_n, + input fpga_ref_clk_p, + // Device clock passed through 9001 + input dev_clk_in, + + input fpga_mcs_in_n, + input fpga_mcs_in_p, + output dev_mcs_fpga_out_n, + output dev_mcs_fpga_out_p, + + inout dgpio_0, + inout dgpio_1, + inout dgpio_2, + inout dgpio_3, + inout dgpio_4, + inout dgpio_5, + inout dgpio_6, + inout dgpio_7, + inout dgpio_8, + inout dgpio_9, + inout dgpio_10, + inout dgpio_11, + + inout gp_int, + inout mode, + inout reset_trx, + + // physical interface + input rx1_dclk_in_n, + input rx1_dclk_in_p, + output rx1_enable, + input rx1_idata_in_n, + input rx1_idata_in_p, + input rx1_qdata_in_n, + input rx1_qdata_in_p, + input rx1_strobe_in_n, + input rx1_strobe_in_p, + + input rx2_dclk_in_n, + input rx2_dclk_in_p, + output rx2_enable, + input rx2_idata_in_n, + input rx2_idata_in_p, + input rx2_qdata_in_n, + input rx2_qdata_in_p, + input rx2_strobe_in_n, + input rx2_strobe_in_p, + + output tx1_dclk_out_n, + output tx1_dclk_out_p, + input tx1_dclk_in_n, + input tx1_dclk_in_p, + output tx1_enable, + output tx1_idata_out_n, + output tx1_idata_out_p, + output tx1_qdata_out_n, + output tx1_qdata_out_p, + output tx1_strobe_out_n, + output tx1_strobe_out_p, + + output tx2_dclk_out_n, + output tx2_dclk_out_p, + input tx2_dclk_in_n, + input tx2_dclk_in_p, + output tx2_enable, + output tx2_idata_out_n, + output tx2_idata_out_p, + output tx2_qdata_out_n, + output tx2_qdata_out_p, + output tx2_strobe_out_n, + output tx2_strobe_out_p, + + input vadj_err, + output platform_status +); + + // internal signals + + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire gpio_rx1_enable_in; + wire gpio_rx2_enable_in; + wire gpio_tx1_enable_in; + wire gpio_tx2_enable_in; + wire mssi_sync; + + // assignments + + assign platform_status = vadj_err; + + // multi-ssi synchronization + // + assign mssi_sync = gpio_o[54]; + + assign gpio_i[54:32] = gpio_o[54:32]; + assign gpio_i[55] = vadj_err; + assign gpio_i[63:56] = gpio_o[63:56]; + + // board stuff (max-v-u21) + + assign gpio_i[31:12] = gpio_o[31:12]; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[ 3: 0]; + + assign gpio_bd_o = gpio_o[3:0]; + + // peripheral reset + + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + + // instantiations + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hps_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + + .sys_hps_rstn_reset_n (sys_resetn), + .sys_rstn_reset_n (sys_resetn_s), + + .adrv9001_if_rx1_dclk_in_p_dclk_in (rx1_dclk_in_p), + .adrv9001_if_rx1_idata_in_n_idata0 (rx1_idata_in_n), + .adrv9001_if_rx1_idata_in_p_idata1 (rx1_idata_in_p), + .adrv9001_if_rx1_qdata_in_n_qdata2 (rx1_qdata_in_n), + .adrv9001_if_rx1_qdata_in_p_qdata3 (rx1_qdata_in_p), + .adrv9001_if_rx1_strobe_in_p_strobe_in (rx1_strobe_in_p), + .adrv9001_if_rx2_dclk_in_p_dclk_in (rx2_dclk_in_p), + .adrv9001_if_rx2_idata_in_n_idata0 (rx2_idata_in_n), + .adrv9001_if_rx2_idata_in_p_idata1 (rx2_idata_in_p), + .adrv9001_if_rx2_qdata_in_n_qdata2 (rx2_qdata_in_n), + .adrv9001_if_rx2_qdata_in_p_qdata3 (rx2_qdata_in_p), + .adrv9001_if_rx2_strobe_in_p_strobe_in (rx2_strobe_in_p), + .adrv9001_if_tx1_dclk_out_p_dclk_out (tx1_dclk_out_p), + .adrv9001_if_tx1_dclk_in_p_dclk_in (tx1_dclk_in_p), + .adrv9001_if_tx1_idata_out_n_idata0 (tx1_idata_out_n), + .adrv9001_if_tx1_idata_out_p_idata1 (tx1_idata_out_p), + .adrv9001_if_tx1_qdata_out_n_qdata2 (tx1_qdata_out_n), + .adrv9001_if_tx1_qdata_out_p_qdata3 (tx1_qdata_out_p), + .adrv9001_if_tx1_strobe_out_p_strobe_out (tx1_strobe_out_p), + .adrv9001_if_tx2_dclk_out_p_dclk_out (tx2_dclk_out_p), + .adrv9001_if_tx2_dclk_in_p_dclk_in (tx2_dclk_in_p), + .adrv9001_if_tx2_idata_out_n_idata0 (tx2_idata_out_n), + .adrv9001_if_tx2_idata_out_p_idata1 (tx2_idata_out_p), + .adrv9001_if_tx2_qdata_out_n_qdata2 (tx2_qdata_out_n), + .adrv9001_if_tx2_qdata_out_p_qdata3 (tx2_qdata_out_p), + .adrv9001_if_tx2_strobe_out_p_strobe_out (tx2_strobe_out_p), + + .adrv9001_if_rx1_enable (rx1_enable), + .adrv9001_if_rx2_enable (rx2_enable), + .adrv9001_if_tx1_enable (tx1_enable), + .adrv9001_if_tx2_enable (tx2_enable), + + .adrv9001_tdd_if_rx1_enable_in (gpio_rx1_enable_in), + .adrv9001_tdd_if_rx2_enable_in (gpio_rx2_enable_in), + .adrv9001_tdd_if_tx1_enable_in (gpio_tx1_enable_in), + .adrv9001_tdd_if_tx2_enable_in (gpio_tx2_enable_in), + .adrv9001_tdd_if_tdd_sync_in (1'b0), + + .sys_spi_MISO (spi_do), + .sys_spi_MOSI (spi_dio), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_en), + + .adrv9001_gpio_export({gpio_tx2_enable_in, + gpio_tx1_enable_in, + gpio_rx2_enable_in, + gpio_rx1_enable_in, + reset_trx, + mode, + gp_int, + dgpio_11, + dgpio_10, + dgpio_9, + dgpio_8, + dgpio_7, + dgpio_6, + dgpio_5, + dgpio_4, + dgpio_3, + dgpio_2, + dgpio_1, + dgpio_0}) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/adrv9001/common/adrv9001_qsys.tcl b/projects/adrv9001/common/adrv9001_qsys.tcl new file mode 100644 index 000000000..cca88a5c9 --- /dev/null +++ b/projects/adrv9001/common/adrv9001_qsys.tcl @@ -0,0 +1,149 @@ + +# adrv9001 + +add_instance axi_adrv9001 axi_adrv9001 +set_instance_parameter_value axi_adrv9001 {ID} {0} +set_instance_parameter_value axi_adrv9001 {CMOS_LVDS_N} {1} +add_interface adrv9001_if conduit end +set_interface_property adrv9001_if EXPORT_OF axi_adrv9001.device_if +add_interface adrv9001_tdd_if conduit end +set_interface_property adrv9001_tdd_if EXPORT_OF axi_adrv9001.tdd_if +add_connection sys_clk.clk axi_adrv9001.s_axi_clock +add_connection sys_clk.clk_reset axi_adrv9001.s_axi_reset + +# adc-wfifo + +add_instance util_adc_wfifo util_wfifo +set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4} +set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16} +set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16} +set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5} +add_connection axi_adrv9001.if_adc_1_clk util_adc_wfifo.if_din_clk +add_connection axi_adrv9001.if_adc_1_rst util_adc_wfifo.if_din_rst +add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk +add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn +add_connection axi_adrv9001.adc_1_ch_0 util_adc_wfifo.din_0 +add_connection axi_adrv9001.adc_1_ch_1 util_adc_wfifo.din_1 +add_connection axi_adrv9001.adc_1_ch_2 util_adc_wfifo.din_2 +add_connection axi_adrv9001.adc_1_ch_3 util_adc_wfifo.din_3 +add_connection util_adc_wfifo.if_din_ovf axi_adrv9001.if_adc_1_dovf + +# dac-rfifo + +add_instance util_dac_rfifo util_rfifo +set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4} +set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16} +set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16} +set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5} +add_connection axi_adrv9001.if_dac_1_clk util_dac_rfifo.if_dout_clk +add_connection axi_adrv9001.if_dac_1_rst util_dac_rfifo.if_dout_rst +add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk +add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn +add_connection util_dac_rfifo.dout_0 axi_adrv9001.dac_1_ch_0 +add_connection util_dac_rfifo.dout_1 axi_adrv9001.dac_1_ch_1 +add_connection util_dac_rfifo.dout_2 axi_adrv9001.dac_1_ch_2 +add_connection util_dac_rfifo.dout_3 axi_adrv9001.dac_1_ch_3 +add_connection util_dac_rfifo.if_dout_unf axi_adrv9001.if_dac_1_dunf + +# adc-pack + +add_instance util_adc_pack util_cpack2 +set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value util_adc_pack {SAMPLE_DATA_WIDTH} {16} +add_connection sys_dma_clk.clk util_adc_pack.clk +add_connection sys_dma_clk.clk_reset util_adc_pack.reset +add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0 +add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1 +add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2 +add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3 +add_connection util_adc_pack.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf + +# dac-unpack + +add_instance util_dac_upack util_upack2 +set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value util_dac_upack {SAMPLE_DATA_WIDTH} {16} +add_connection sys_dma_clk.clk util_dac_upack.clk +add_connection sys_dma_clk.clk_reset util_dac_upack.reset +add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0 +add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1 +add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2 +add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3 +add_connection util_dac_upack.if_fifo_rd_underflow util_dac_rfifo.if_din_unf + +# adc-dma + +add_instance axi_adc_dma axi_dmac +set_instance_parameter_value axi_adc_dma {ID} {0} +set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_adc_dma {CYCLIC} {0} +set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4} +add_connection sys_clk.clk axi_adc_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset +add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk +add_connection util_adc_pack.if_packed_fifo_wr_en axi_adc_dma.if_fifo_wr_en +add_connection util_adc_pack.if_packed_fifo_wr_sync axi_adc_dma.if_fifo_wr_sync +add_connection util_adc_pack.if_packed_fifo_wr_data axi_adc_dma.if_fifo_wr_din +add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_pack.if_packed_fifo_wr_overflow + +# dac-dma + +add_instance axi_dac_dma axi_dmac +set_instance_parameter_value axi_dac_dma {ID} {0} +set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_dac_dma {CYCLIC} {1} +set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {1} +set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4} +add_connection sys_clk.clk axi_dac_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock +add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset +add_connection sys_dma_clk.clk axi_dac_dma.if_m_axis_aclk + +add_connection axi_dac_dma.m_axis util_dac_upack.s_axis + +# adrv9001 gpio + +add_instance avl_adrv9001_gpio altera_avalon_pio +set_instance_parameter_value avl_adrv9001_gpio {direction} {Bidir} +set_instance_parameter_value avl_adrv9001_gpio {generateIRQ} {1} +set_instance_parameter_value avl_adrv9001_gpio {width} {19} +add_connection sys_clk.clk avl_adrv9001_gpio.clk +add_connection sys_clk.clk_reset avl_adrv9001_gpio.reset +add_interface adrv9001_gpio conduit end +set_interface_property adrv9001_gpio EXPORT_OF avl_adrv9001_gpio.external_connection + +# interrupts + +ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender +ad_cpu_interrupt 3 axi_dac_dma.interrupt_sender +ad_cpu_interrupt 14 avl_adrv9001_gpio.irq + +# cpu interconnects + +ad_cpu_interconnect 0x00020000 axi_adrv9001.s_axi +ad_cpu_interconnect 0x00040000 axi_adc_dma.s_axi +ad_cpu_interconnect 0x00044000 axi_dac_dma.s_axi +ad_cpu_interconnect 0x00060000 avl_adrv9001_gpio.s1 + +# mem interconnects + +ad_dma_interconnect axi_adc_dma.m_dest_axi +ad_dma_interconnect axi_dac_dma.m_src_axi