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ad_mul.v: Add parameters for A and B input widths 

The out width will be A + B.
This change is backward compatible and it applies to both Altera and Xilinx.
main
AndreiGrozav 2018-04-03 14:09:47 +03:00 committed by AndreiGrozav
parent 3dc7be3eab
commit 568f2e180f
2 changed files with 17 additions and 13 deletions
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16
library/altera/common/ad_mul.v
View File

@ -37,14 +37,16 @@
module ad_mul #(
parameter A_DATA_WIDTH = 17,
parameter B_DATA_WIDTH = 17,
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
input clk,
input [16:0] data_a,
input [16:0] data_b,
output [33:0] data_p,
input clk,
input [ A_DATA_WIDTH-1:0] data_a,
input [ B_DATA_WIDTH-1:0] data_b,
output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
// delay interface
@ -67,9 +69,9 @@ module ad_mul #(
lpm_mult #(
.lpm_type ("lpm_mult"),
.lpm_widtha (17),
.lpm_widthb (17),
.lpm_widthp (34),
.lpm_widtha (A_DATA_WIDTH),
.lpm_widthb (B_DATA_WIDTH),
.lpm_widthp (A_DATA_WIDTH + B_DATA_WIDTH),
.lpm_representation ("SIGNED"),
.lpm_pipeline (3))
i_lpm_mult (

14
library/xilinx/common/ad_mul.v
View File

@ -37,14 +37,16 @@
module ad_mul #(
parameter A_DATA_WIDTH = 17,
parameter B_DATA_WIDTH = 17,
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
input clk,
input [16:0] data_a,
input [16:0] data_b,
output [33:0] data_p,
input clk,
input [ A_DATA_WIDTH-1:0] data_a,
input [ B_DATA_WIDTH-1:0] data_b,
output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
// delay interface
@ -67,8 +69,8 @@ module ad_mul #(
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (17),
.WIDTH_B (17))
.WIDTH_A (A_DATA_WIDTH),
.WIDTH_B (B_DATA_WIDTH))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),