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dmac: create fifo interface to avoid being treated as axi control stream

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Rejeesh Kutty 2014-05-27 10:25:14 -04:00
parent 0cd43e34f5
commit 56ddce1e8c
2 changed files with 28 additions and 0 deletions
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20
library/axi_dmac/axi_dmac_ip.tcl
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@ -60,5 +60,25 @@ adi_set_ports_dependency "fifo_wr" \
adi_set_ports_dependency "fifo_rd" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_DEST')) = 2)"
ipx::add_bus_interface {fifo_wr} [ipx::current_core]
set_property abstraction_type_vlnv {xilinx.com:interface:fifo_write_rtl:1.0} [ipx::get_bus_interface fifo_wr [ipx::current_core]]
set_property bus_type_vlnv {xilinx.com:interface:fifo_write:1.0} [ipx::get_bus_interface fifo_wr [ipx::current_core]]
set_property display_name {fifo_wr} [ipx::get_bus_interface fifo_wr [ipx::current_core]]
ipx::add_port_map {WR_DATA} [ipx::get_bus_interface fifo_wr [ipx::current_core]]
set_property physical_name {fifo_wr_din} [ipx::get_port_map WR_DATA [ipx::get_bus_interface fifo_wr [ipx::current_core]]]
ipx::add_port_map {WR_EN} [ipx::get_bus_interface fifo_wr [ipx::current_core]]
set_property physical_name {fifo_wr_en} [ipx::get_port_map WR_EN [ipx::get_bus_interface fifo_wr [ipx::current_core]]]
ipx::add_bus_interface {fifo_wr_clock} [ipx::current_core]
set_property abstraction_type_vlnv {xilinx.com:signal:clock_rtl:1.0} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]
set_property bus_type_vlnv {xilinx.com:signal:clock:1.0} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]
set_property display_name {fifo_wr_clock} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]
ipx::add_port_map {CLK} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]
set_property physical_name {fifo_wr_clk} [ipx::get_port_map CLK [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]]
ipx::add_bus_parameter {ASSOCIATED_BUSIF} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]
set_property value {fifo_wr} [ipx::get_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]]
ipx::save_core [ipx::current_core]

8
projects/common/zc706/zc706_system_mig_constr.xdc Normal file
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@ -0,0 +1,8 @@
# clocks
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVDS} [get_ports sys_clk_p]
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports sys_clk_n]
create_clock -name sys_clk -period 5.00 [get_ports sys_clk_p]