From 56ddce1e8c2cd795318c69e289a88819004e82a9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 27 May 2014 10:25:14 -0400 Subject: [PATCH] dmac: create fifo interface to avoid being treated as axi control stream --- library/axi_dmac/axi_dmac_ip.tcl | 20 +++++++++++++++++++ .../common/zc706/zc706_system_mig_constr.xdc | 8 ++++++++ 2 files changed, 28 insertions(+) create mode 100644 projects/common/zc706/zc706_system_mig_constr.xdc diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 94834df6d..bb4243d7d 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -60,5 +60,25 @@ adi_set_ports_dependency "fifo_wr" \ adi_set_ports_dependency "fifo_rd" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_DEST')) = 2)" +ipx::add_bus_interface {fifo_wr} [ipx::current_core] +set_property abstraction_type_vlnv {xilinx.com:interface:fifo_write_rtl:1.0} [ipx::get_bus_interface fifo_wr [ipx::current_core]] +set_property bus_type_vlnv {xilinx.com:interface:fifo_write:1.0} [ipx::get_bus_interface fifo_wr [ipx::current_core]] +set_property display_name {fifo_wr} [ipx::get_bus_interface fifo_wr [ipx::current_core]] + +ipx::add_port_map {WR_DATA} [ipx::get_bus_interface fifo_wr [ipx::current_core]] +set_property physical_name {fifo_wr_din} [ipx::get_port_map WR_DATA [ipx::get_bus_interface fifo_wr [ipx::current_core]]] +ipx::add_port_map {WR_EN} [ipx::get_bus_interface fifo_wr [ipx::current_core]] +set_property physical_name {fifo_wr_en} [ipx::get_port_map WR_EN [ipx::get_bus_interface fifo_wr [ipx::current_core]]] + +ipx::add_bus_interface {fifo_wr_clock} [ipx::current_core] +set_property abstraction_type_vlnv {xilinx.com:signal:clock_rtl:1.0} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]] +set_property bus_type_vlnv {xilinx.com:signal:clock:1.0} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]] +set_property display_name {fifo_wr_clock} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]] +ipx::add_port_map {CLK} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]] +set_property physical_name {fifo_wr_clk} [ipx::get_port_map CLK [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]] + +ipx::add_bus_parameter {ASSOCIATED_BUSIF} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]] +set_property value {fifo_wr} [ipx::get_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]] + ipx::save_core [ipx::current_core] diff --git a/projects/common/zc706/zc706_system_mig_constr.xdc b/projects/common/zc706/zc706_system_mig_constr.xdc new file mode 100644 index 000000000..5a8aa9c02 --- /dev/null +++ b/projects/common/zc706/zc706_system_mig_constr.xdc @@ -0,0 +1,8 @@ + +# clocks + +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVDS} [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports sys_clk_n] + +create_clock -name sys_clk -period 5.00 [get_ports sys_clk_p] +