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FMCOMMS2: Added sync option

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ATofan 2014-04-11 18:14:48 +03:00
parent 99ef34936f
commit 570ec26798
3 changed files with 35 additions and 31 deletions
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7
library/axi_ad9361/axi_ad9361.v
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@ -280,8 +280,7 @@ module axi_ad9361 (
axi_ad9361_dev_if #(
.PCORE_BUFTYPE (PCORE_BUFTYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP),
.PCORE_ID(PCORE_ID))
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_dev_if (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
@ -296,8 +295,6 @@ module axi_ad9361 (
.tx_data_out_p (tx_data_out_p),
.tx_data_out_n (tx_data_out_n),
.clk (clk),
.adc_start_in (adc_start_in),
.adc_start_out (adc_start_out),
.adc_valid (adc_valid_s),
.adc_data_i1 (adc_data_i1_s),
.adc_data_q1 (adc_data_q1_s),
@ -381,6 +378,8 @@ module axi_ad9361 (
.adc_data_q2 (adc_data_q2_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode_s),
.adc_start_in (adc_start_in),
.adc_start_out (adc_start_out),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel_s),

22
library/axi_ad9361/axi_ad9361_dev_if.v
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@ -74,10 +74,6 @@ module axi_ad9361_dev_if (
adc_data_q2,
adc_status,
adc_r1_mode,
// receive master/slave
adc_start_in,
adc_start_out,
// transmit data path interface
@ -109,7 +105,6 @@ module axi_ad9361_dev_if (
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter PCORE_ID = 0;
localparam PCORE_7SERIES = 0;
localparam PCORE_VIRTEX6 = 1;
@ -144,10 +139,6 @@ module axi_ad9361_dev_if (
output [11:0] adc_data_q2;
output adc_status;
input adc_r1_mode;
// receive master/slave
input adc_start_in;
output adc_start_out;
// transmit data path interface
@ -177,7 +168,6 @@ module axi_ad9361_dev_if (
// internal registers
reg adc_start_out;
reg [ 5:0] rx_data_n = 'd0;
reg rx_frame_n = 'd0;
reg [11:0] rx_data = 'd0;
@ -214,7 +204,6 @@ module axi_ad9361_dev_if (
// internal signals
wire adc_start_s;
wire [ 3:0] rx_frame_s;
wire [ 3:0] tx_data_sel_s;
wire [ 4:0] delay_rdata_s[6:0];
@ -284,13 +273,6 @@ module axi_ad9361_dev_if (
assign dev_dbg_data[285:274] = adc_data_i2;
assign dev_dbg_data[297:286] = adc_data_q2;
// multiple instances synchronization
assign adc_start_s = (PCORE_ID == 32'd0) ? adc_start_out : adc_start_in;
always @(posedge clk) begin
adc_start_out <= 1'b1;
end
// receive data path interface
assign rx_frame_s = {rx_frame_d, rx_frame};
@ -335,14 +317,14 @@ module axi_ad9361_dev_if (
always @(posedge clk) begin
if (adc_r1_mode == 1'b1) begin
adc_valid <= rx_valid_r1 & adc_start_s;
adc_valid <= rx_valid_r1;
adc_data_i1 <= rx_data_i_r1;
adc_data_q1 <= rx_data_q_r1;
adc_data_i2 <= 12'd0;
adc_data_q2 <= 12'd0;
adc_status <= ~rx_error_r1;
end else begin
adc_valid <= rx_valid_r2 & adc_start_s;
adc_valid <= rx_valid_r2;
adc_data_i1 <= rx_data_i1_r2;
adc_data_q1 <= rx_data_q1_r2;
adc_data_i2 <= rx_data_i2_r2;

37
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -60,6 +60,10 @@ module axi_ad9361_rx (
adc_data_q2,
adc_status,
adc_r1_mode,
// receive master/slave
adc_start_in,
adc_start_out,
// delay interface
@ -125,6 +129,10 @@ module axi_ad9361_rx (
input [11:0] adc_data_q2;
input adc_status;
output adc_r1_mode;
// receive master/slave
input adc_start_in;
output adc_start_out;
// delay interface
@ -189,6 +197,7 @@ module axi_ad9361_rx (
reg up_adc_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg adc_start_out;
// internal clocks and resets
@ -237,10 +246,24 @@ module axi_ad9361_rx (
wire up_ack_3_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire adc_start_cond;
wire adc_valid_cond;
assign adc_start_cond = (PCORE_ID == 32'd0) ? adc_start_out : adc_start_in;
always @(posedge adc_clk) begin
if(adc_rst == 1'b1) begin
adc_start_out <= 1'b0;
end else begin
adc_start_out <= 1'b1;
end
end
assign adc_valid_cond = adc_valid & adc_start_cond;
// monitor signals
assign adc_mon_valid = adc_valid;
assign adc_mon_valid = adc_valid_cond;
assign adc_mon_data[11: 0] = adc_data_i1;
assign adc_mon_data[23:12] = adc_data_q1;
assign adc_mon_data[35:24] = adc_data_i2;
@ -249,7 +272,7 @@ module axi_ad9361_rx (
// debug signals
assign adc_dbg_trigger[0] = adc_iqcor_valid_s;
assign adc_dbg_trigger[1] = adc_valid;
assign adc_dbg_trigger[1] = adc_valid_cond;
assign adc_dbg_data[ 15: 0] = adc_iqcor_data_0_s;
assign adc_dbg_data[ 31: 16] = adc_iqcor_data_1_s;
@ -263,7 +286,7 @@ module axi_ad9361_rx (
assign adc_dbg_data[ 91: 80] = adc_data_q1;
assign adc_dbg_data[103: 92] = adc_data_i2;
assign adc_dbg_data[115:104] = adc_data_q2;
assign adc_dbg_data[116:116] = adc_valid;
assign adc_dbg_data[116:116] = adc_valid_cond;
// adc channels - dma interface
@ -526,7 +549,7 @@ module axi_ad9361_rx (
i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_valid (adc_valid_cond),
.adc_pn_oos_pl (adc_pn_oos_i1),
.adc_pn_err_pl (adc_pn_err_i1),
.adc_data (adc_data_i1),
@ -562,7 +585,7 @@ module axi_ad9361_rx (
i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_valid (adc_valid_cond),
.adc_pn_oos_pl (adc_pn_oos_q1),
.adc_pn_err_pl (adc_pn_err_q1),
.adc_data (adc_data_q1),
@ -598,7 +621,7 @@ module axi_ad9361_rx (
i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_valid (adc_valid_cond),
.adc_pn_oos_pl (adc_pn_oos_i2),
.adc_pn_err_pl (adc_pn_err_i2),
.adc_data (adc_data_i2),
@ -634,7 +657,7 @@ module axi_ad9361_rx (
i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_valid (adc_valid_cond),
.adc_pn_oos_pl (adc_pn_oos_q2),
.adc_pn_err_pl (adc_pn_err_q2),
.adc_data (adc_data_q2),