util_upack- port updates
Rejeesh Kutty
parent
8a88d94553
commit
5751cd30dc
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@ -1,48 +1,22 @@
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME util_upack
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set_module_property DESCRIPTION "Channel Unpack Utility"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_upack
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set_module_property ELABORATION_CALLBACK p_util_upack
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL util_upack
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add_fileset_file util_upack_dmx.v VERILOG PATH util_upack_dmx.v
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add_fileset_file util_upack_dsf.v VERILOG PATH util_upack_dsf.v
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add_fileset_file util_upack.v VERILOG PATH util_upack.v TOP_LEVEL_FILE
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ad_ip_create util_upack {Channel Unpack Utility} util_upack_elab
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ad_ip_files util_upack [list\
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util_upack_dmx.v \
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util_upack_dsf.v \
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util_upack.v]
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# parameters
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add_parameter CHANNEL_DATA_WIDTH INTEGER 0
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set_parameter_property CHANNEL_DATA_WIDTH DEFAULT_VALUE 32
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set_parameter_property CHANNEL_DATA_WIDTH DISPLAY_NAME CHANNEL_DATA_WIDTH
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set_parameter_property CHANNEL_DATA_WIDTH TYPE INTEGER
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set_parameter_property CHANNEL_DATA_WIDTH UNITS None
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set_parameter_property CHANNEL_DATA_WIDTH HDL_PARAMETER true
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add_parameter NUM_OF_CHANNELS INTEGER 0
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set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8
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set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
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set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
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set_parameter_property NUM_OF_CHANNELS UNITS None
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set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
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ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 32
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ad_ip_parameter NUM_OF_CHANNELS INTEGER 8
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# defaults
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ad_alt_intf clock dac_clk input 1
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ad_alt_intf signal dma_xfer_in input 1 xfer_req
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ad_alt_intf signal dac_xfer_out output 1 xfer_req
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ad_alt_intf signal dac_valid output 1 valid
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ad_alt_intf signal dac_sync output 1 sync
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ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data
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@ -50,81 +24,23 @@ ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH
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add_interface dac_ch_0 conduit end
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add_interface_port dac_ch_0 dac_enable_0 enable Input 1
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add_interface_port dac_ch_0 dac_valid_0 valid Input 1
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add_interface_port dac_ch_0 dac_valid_out_0 valid_out Output 1
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add_interface_port dac_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_0 associatedClock if_dac_clk
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set_interface_property dac_ch_0 associatedReset none
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proc p_util_upack {} {
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proc util_upack_elab {} {
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if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
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add_interface dac_ch_1 conduit end
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add_interface_port dac_ch_1 dac_enable_1 enable Input 1
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add_interface_port dac_ch_1 dac_valid_1 valid Input 1
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add_interface_port dac_ch_1 dac_data_1 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_1 associatedClock if_dac_clk
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for {set n 1} {$n < 8} {incr n} {
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if {[get_parameter_value NUM_OF_CHANNELS] > n} {
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add_interface dac_ch_${n} conduit end
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add_interface_port dac_ch_${n} dac_enable_${n} enable Input 1
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add_interface_port dac_ch_${n} dac_valid_${n} valid Input 1
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add_interface_port dac_ch_${n} dac_valid_out_${n} valid_out Output 1
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add_interface_port dac_ch_${n} dac_data_${n} data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_${n} associatedClock if_dac_clk
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set_interface_property dac_ch_${n} associatedReset none
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}
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if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
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add_interface dac_ch_2 conduit end
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add_interface_port dac_ch_2 dac_enable_2 enable Input 1
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add_interface_port dac_ch_2 dac_valid_2 valid Input 1
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add_interface_port dac_ch_2 dac_data_2 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_2 associatedClock if_dac_clk
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}
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if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
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add_interface dac_ch_3 conduit end
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add_interface_port dac_ch_3 dac_enable_3 enable Input 1
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add_interface_port dac_ch_3 dac_valid_3 valid Input 1
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add_interface_port dac_ch_3 dac_data_3 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_3 associatedClock if_dac_clk
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}
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if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
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add_interface dac_ch_4 conduit end
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add_interface_port dac_ch_4 dac_enable_4 enable Input 1
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add_interface_port dac_ch_4 dac_valid_4 valid Input 1
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add_interface_port dac_ch_4 dac_data_4 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_4 associatedClock if_dac_clk
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}
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if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
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add_interface dac_ch_5 conduit end
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add_interface_port dac_ch_5 dac_enable_5 enable Input 1
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add_interface_port dac_ch_5 dac_valid_5 valid Input 1
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add_interface_port dac_ch_5 dac_data_5 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_5 associatedClock if_dac_clk
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}
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if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
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add_interface dac_ch_6 conduit end
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add_interface_port dac_ch_6 dac_enable_6 enable Input 1
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add_interface_port dac_ch_6 dac_valid_6 valid Input 1
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add_interface_port dac_ch_6 dac_data_6 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_6 associatedClock if_dac_clk
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}
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if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
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add_interface dac_ch_7 conduit end
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add_interface_port dac_ch_7 dac_enable_7 enable Input 1
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add_interface_port dac_ch_7 dac_valid_7 valid Input 1
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add_interface_port dac_ch_7 dac_data_7 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_7 associatedClock if_dac_clk
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}
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}
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@ -15,7 +15,6 @@ adi_ip_properties_lite util_upack
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set_property driver_value 0 [ipx::get_ports *dac_enable* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dac_valid* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dac_data* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dma_xfer_in* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
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[ipx::get_ports *_1* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
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