diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v index 1f31867df..d41b67e86 100755 --- a/library/axi_ad6676/axi_ad6676.v +++ b/library/axi_ad6676/axi_ad6676.v @@ -81,9 +81,9 @@ module axi_ad6676 ( s_axi_rdata, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is (line-rate/40) @@ -204,7 +204,7 @@ module axi_ad6676 ( // channel - axi_ad6676_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -227,7 +227,7 @@ module axi_ad6676 ( // channel - axi_ad6676_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), @@ -250,7 +250,7 @@ module axi_ad6676 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad6676/axi_ad6676_channel.v b/library/axi_ad6676/axi_ad6676_channel.v index 03ac0c627..69b4c273c 100755 --- a/library/axi_ad6676/axi_ad6676_channel.v +++ b/library/axi_ad6676/axi_ad6676_channel.v @@ -72,8 +72,8 @@ module axi_ad6676_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; // adc interface @@ -120,7 +120,7 @@ module axi_ad6676_channel ( assign adc_dfmt_data = adc_data; - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index 1639bf58b..4ac740ae0 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -91,12 +91,12 @@ module axi_ad9122 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_SERDES_DDR_N = 1; - parameter PCORE_MMCM_BUFIO_N = 1; - parameter PCORE_DAC_DP_DISABLE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter SERDES_OR_DDR_N = 1; + parameter MMCM_OR_BUFIO_N = 1; + parameter DAC_DATAPATH_DISABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; // dac interface @@ -198,9 +198,9 @@ module axi_ad9122 ( // device interface axi_ad9122_if #( - .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), - .PCORE_SERDES_DDR_N (PCORE_SERDES_DDR_N), - .PCORE_MMCM_BUFIO_N (PCORE_MMCM_BUFIO_N)) + .DEVICE_TYPE (DEVICE_TYPE), + .SERDES_OR_DDR_N (SERDES_OR_DDR_N), + .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N)) i_if ( .dac_clk_in_p (dac_clk_in_p), .dac_clk_in_n (dac_clk_in_n), @@ -243,7 +243,7 @@ module axi_ad9122 ( // core - axi_ad9122_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core ( + axi_ad9122_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core ( .dac_div_clk (dac_div_clk), .dac_rst (dac_rst), .dac_frame_i0 (dac_frame_i0_s), diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v index 6495b7d58..7b64d2d32 100644 --- a/library/axi_ad9122/axi_ad9122_channel.v +++ b/library/axi_ad9122/axi_ad9122_channel.v @@ -71,8 +71,8 @@ module axi_ad9122_channel ( // parameters - parameter CHID = 32'h0; - parameter DP_DISABLE = 0; + parameter CHANNEL_ID = 32'h0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -184,7 +184,7 @@ module axi_ad9122_channel ( end generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_0_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -199,7 +199,7 @@ module axi_ad9122_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_1_s = 16'd0; end else begin ad_dds i_dds_1 ( @@ -214,7 +214,7 @@ module axi_ad9122_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_2_s = 16'd0; end else begin ad_dds i_dds_2 ( @@ -229,7 +229,7 @@ module axi_ad9122_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_3_s = 16'd0; end else begin ad_dds i_dds_3 ( @@ -245,7 +245,7 @@ module axi_ad9122_channel ( // single channel processor - up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_div_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index 45e15ba08..e3c91a1e9 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -106,8 +106,8 @@ module axi_ad9122_core ( // parameters - parameter PCORE_ID = 0; - parameter DP_DISABLE = 0; + parameter ID = 0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -202,7 +202,7 @@ module axi_ad9122_core ( // master/slave (clocks must be synchronous) - assign dac_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in; + assign dac_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; // processor read interface @@ -221,8 +221,8 @@ module axi_ad9122_core ( // dac channel axi_ad9122_channel #( - .CHID(0), - .DP_DISABLE(DP_DISABLE)) + .CHANNEL_ID(0), + .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 ( .dac_div_clk (dac_div_clk), .dac_rst (dac_rst), @@ -247,8 +247,8 @@ module axi_ad9122_core ( // dac channel axi_ad9122_channel #( - .CHID(1), - .DP_DISABLE(DP_DISABLE)) + .CHANNEL_ID(1), + .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_1 ( .dac_div_clk (dac_div_clk), .dac_rst (dac_rst), @@ -272,7 +272,7 @@ module axi_ad9122_core ( // dac common processor interface - up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common ( + up_dac_common #(.ID(ID)) i_up_dac_common ( .mmcm_rst (mmcm_rst), .dac_clk (dac_div_clk), .dac_rst (dac_rst), diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index 90ef74988..cb7a437d7 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -97,10 +97,10 @@ module axi_ad9122_if ( // parameters - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_SERDES_DDR_N = 1; - parameter PCORE_MMCM_BUFIO_N = 1; - parameter PCORE_IODELAY_GROUP = "dac_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter SERDES_OR_DDR_N = 1; + parameter MMCM_OR_BUFIO_N = 1; + parameter IO_DELAY_GROUP = "dac_if_delay_group"; // dac interface @@ -176,8 +176,8 @@ module axi_ad9122_if ( // dac data output serdes(s) & buffers ad_serdes_out #( - .DEVICE_TYPE (PCORE_DEVICE_TYPE), - .SERDES(PCORE_SERDES_DDR_N), + .DEVICE_TYPE (DEVICE_TYPE), + .SERDES_OR_DDR_N(SERDES_OR_DDR_N), .DATA_WIDTH(16)) i_serdes_out_data ( .rst (dac_rst), @@ -197,8 +197,8 @@ module axi_ad9122_if ( // dac frame output serdes & buffer ad_serdes_out #( - .DEVICE_TYPE (PCORE_DEVICE_TYPE), - .SERDES(PCORE_SERDES_DDR_N), + .DEVICE_TYPE (DEVICE_TYPE), + .SERDES_OR_DDR_N(SERDES_OR_DDR_N), .DATA_WIDTH(1)) i_serdes_out_frame ( .rst (dac_rst), @@ -218,8 +218,8 @@ module axi_ad9122_if ( // dac clock output serdes & buffer ad_serdes_out #( - .DEVICE_TYPE (PCORE_DEVICE_TYPE), - .SERDES(PCORE_SERDES_DDR_N), + .DEVICE_TYPE (DEVICE_TYPE), + .SERDES_OR_DDR_N(SERDES_OR_DDR_N), .DATA_WIDTH(1)) i_serdes_out_clk ( .rst (dac_rst), @@ -239,9 +239,9 @@ module axi_ad9122_if ( // dac clock input buffers ad_serdes_clk #( - .SERDES (PCORE_SERDES_DDR_N), - .MMCM (PCORE_MMCM_BUFIO_N), - .MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE), + .SERDES_OR_DDR_N (SERDES_OR_DDR_N), + .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N), + .MMCM_DEVICE_TYPE (DEVICE_TYPE), .MMCM_CLKIN_PERIOD (1.667), .MMCM_VCO_DIV (6), .MMCM_VCO_MUL (12), diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v index c2ede0273..aace45040 100644 --- a/library/axi_ad9144/axi_ad9144.v +++ b/library/axi_ad9144/axi_ad9144.v @@ -91,15 +91,15 @@ module axi_ad9144 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_QUAD_DUAL_N = 1; - parameter PCORE_DAC_DP_DISABLE = 0; + parameter ID = 0; + parameter QUAD_OR_DUAL_N = 1; + parameter DAC_DATAPATH_DISABLE = 0; // jesd interface // tx_clk is (line-rate/40) input tx_clk; - output [(128*PCORE_QUAD_DUAL_N)+127:0] tx_data; + output [(128*QUAD_OR_DUAL_N)+127:0] tx_data; // dma interface @@ -184,7 +184,7 @@ module axi_ad9144 ( // dual/quad cores - assign tx_data = (PCORE_QUAD_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0]; + assign tx_data = (QUAD_OR_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0]; // device interface @@ -212,7 +212,7 @@ module axi_ad9144 ( // core - axi_ad9144_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core ( + axi_ad9144_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_data_0_0 (dac_data_0_0_s), diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v index a8ebf182a..d079f0707 100644 --- a/library/axi_ad9144/axi_ad9144_channel.v +++ b/library/axi_ad9144/axi_ad9144_channel.v @@ -69,8 +69,8 @@ module axi_ad9144_channel ( // parameters - parameter CHID = 32'h0; - parameter DP_DISABLE = 0; + parameter CHANNEL_ID = 32'h0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -495,7 +495,7 @@ module axi_ad9144_channel ( end generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_0_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -510,7 +510,7 @@ module axi_ad9144_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_1_s = 16'd0; end else begin ad_dds i_dds_1 ( @@ -525,7 +525,7 @@ module axi_ad9144_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_2_s = 16'd0; end else begin ad_dds i_dds_2 ( @@ -540,7 +540,7 @@ module axi_ad9144_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_3_s = 16'd0; end else begin ad_dds i_dds_3 ( @@ -556,7 +556,7 @@ module axi_ad9144_channel ( // single channel processor - up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v index e662bfe00..a4a12afc7 100644 --- a/library/axi_ad9144/axi_ad9144_core.v +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -94,8 +94,8 @@ module axi_ad9144_core ( // parameters - parameter PCORE_ID = 0; - parameter DP_DISABLE = 0; + parameter ID = 0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -197,7 +197,7 @@ module axi_ad9144_core ( // dac channel - axi_ad9144_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 ( + axi_ad9144_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_enable (dac_enable_0), @@ -218,7 +218,7 @@ module axi_ad9144_core ( // dac channel - axi_ad9144_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 ( + axi_ad9144_channel #(.CHANNEL_ID(1), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_1 ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_enable (dac_enable_1), @@ -239,7 +239,7 @@ module axi_ad9144_core ( // dac channel - axi_ad9144_channel #(.CHID(2), .DP_DISABLE(DP_DISABLE)) i_channel_2 ( + axi_ad9144_channel #(.CHANNEL_ID(2), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_2 ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_enable (dac_enable_2), @@ -260,7 +260,7 @@ module axi_ad9144_core ( // dac channel - axi_ad9144_channel #(.CHID(3), .DP_DISABLE(DP_DISABLE)) i_channel_3 ( + axi_ad9144_channel #(.CHANNEL_ID(3), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_3 ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_enable (dac_enable_3), @@ -281,7 +281,7 @@ module axi_ad9144_core ( // dac common processor interface - up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common ( + up_dac_common #(.ID(ID)) i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_clk), .dac_rst (dac_rst), diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index 2e06c03aa..4acb64b93 100755 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -36,19 +36,19 @@ add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true -add_parameter PCORE_QUAD_DUAL_N INTEGER 0 -set_parameter_property PCORE_QUAD_DUAL_N DEFAULT_VALUE 0 -set_parameter_property PCORE_QUAD_DUAL_N DISPLAY_NAME PCORE_QUAD_DUAL_N -set_parameter_property PCORE_QUAD_DUAL_N TYPE INTEGER -set_parameter_property PCORE_QUAD_DUAL_N UNITS None -set_parameter_property PCORE_QUAD_DUAL_N HDL_PARAMETER true +add_parameter QUAD_OR_DUAL_N INTEGER 0 +set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0 +set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N +set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER +set_parameter_property QUAD_OR_DUAL_N UNITS None +set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true # axi4 slave @@ -85,7 +85,7 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface ad_alt_intf clock tx_clk input 1 -ad_alt_intf signal tx_data output 128*(PCORE_QUAD_DUAL_N+1) data +ad_alt_intf signal tx_data output 128*(QUAD_OR_DUAL_N+1) data # dma interface @@ -101,9 +101,9 @@ ad_alt_intf signal dac_dunf input 1 proc p_axi_ad9144 {} { - set p_pcore_quad_dual_n [get_parameter_value "PCORE_QUAD_DUAL_N"] + set p_pcore_quad_dual_n [get_parameter_value "QUAD_OR_DUAL_N"] - if {[get_parameter_value PCORE_QUAD_DUAL_N] == 1} { + if {[get_parameter_value QUAD_OR_DUAL_N] == 1} { ad_alt_intf signal dac_valid_2 output 1 ad_alt_intf signal dac_enable_2 output 1 ad_alt_intf signal dac_ddata_2 input 64 dac_data_2 diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 5b162583c..2ab69a0ee 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -83,8 +83,8 @@ module axi_ad9152 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DAC_DP_DISABLE = 0; + parameter ID = 0; + parameter DAC_DATAPATH_DISABLE = 0; // jesd interface // tx_clk is (line-rate/40) @@ -174,7 +174,7 @@ module axi_ad9152 ( // core - axi_ad9152_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core ( + axi_ad9152_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_data_0_0 (dac_data_0_0_s), diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v index 362b2953e..dd5c0d1b0 100644 --- a/library/axi_ad9152/axi_ad9152_channel.v +++ b/library/axi_ad9152/axi_ad9152_channel.v @@ -69,8 +69,8 @@ module axi_ad9152_channel ( // parameters - parameter CHID = 32'h0; - parameter DP_DISABLE = 0; + parameter CHANNEL_ID = 32'h0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -495,7 +495,7 @@ module axi_ad9152_channel ( end generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_0_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -510,7 +510,7 @@ module axi_ad9152_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_1_s = 16'd0; end else begin ad_dds i_dds_1 ( @@ -525,7 +525,7 @@ module axi_ad9152_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_2_s = 16'd0; end else begin ad_dds i_dds_2 ( @@ -540,7 +540,7 @@ module axi_ad9152_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_3_s = 16'd0; end else begin ad_dds i_dds_3 ( @@ -556,7 +556,7 @@ module axi_ad9152_channel ( // single channel processor - up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v index ae91a3cc1..8feca465b 100644 --- a/library/axi_ad9152/axi_ad9152_core.v +++ b/library/axi_ad9152/axi_ad9152_core.v @@ -80,8 +80,8 @@ module axi_ad9152_core ( // parameters - parameter PCORE_ID = 0; - parameter DP_DISABLE = 0; + parameter ID = 0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -163,7 +163,7 @@ module axi_ad9152_core ( // dac channel - axi_ad9152_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 ( + axi_ad9152_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_enable (dac_enable_0), @@ -184,7 +184,7 @@ module axi_ad9152_core ( // dac channel - axi_ad9152_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 ( + axi_ad9152_channel #(.CHANNEL_ID(1), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_1 ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_enable (dac_enable_1), @@ -205,7 +205,7 @@ module axi_ad9152_core ( // dac common processor interface - up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common ( + up_dac_common #(.ID(ID)) i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_clk), .dac_rst (dac_rst), diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v index 1148a07b4..ca13a5715 100644 --- a/library/axi_ad9234/axi_ad9234.v +++ b/library/axi_ad9234/axi_ad9234.v @@ -81,9 +81,9 @@ module axi_ad9234 ( s_axi_rdata, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is (line-rate/40) @@ -204,7 +204,7 @@ module axi_ad9234 ( // channel - axi_ad9234_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + axi_ad9234_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -227,7 +227,7 @@ module axi_ad9234 ( // channel - axi_ad9234_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + axi_ad9234_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), @@ -250,7 +250,7 @@ module axi_ad9234 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v index 9de3fb6da..0c3878127 100644 --- a/library/axi_ad9234/axi_ad9234_channel.v +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -72,8 +72,8 @@ module axi_ad9234_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; // adc interface @@ -120,7 +120,7 @@ module axi_ad9234_channel ( assign adc_dfmt_data = adc_data; - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index b434f1a15..a88f95ad6 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -83,9 +83,9 @@ module axi_ad9250 ( s_axi_rresp, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is (line-rate/40) @@ -208,7 +208,7 @@ module axi_ad9250 ( // channel - axi_ad9250_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + axi_ad9250_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -231,7 +231,7 @@ module axi_ad9250 ( // channel - axi_ad9250_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + axi_ad9250_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), @@ -254,7 +254,7 @@ module axi_ad9250 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9250/axi_ad9250_channel.v b/library/axi_ad9250/axi_ad9250_channel.v index fd0717154..c5e6b2e6b 100644 --- a/library/axi_ad9250/axi_ad9250_channel.v +++ b/library/axi_ad9250/axi_ad9250_channel.v @@ -72,8 +72,8 @@ module axi_ad9250_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; // adc interface @@ -136,7 +136,7 @@ module axi_ad9250_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl index 018c78ada..c3bceb42e 100755 --- a/library/axi_ad9250/axi_ad9250_hw.tcl +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -32,19 +32,19 @@ add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true -add_parameter PCORE_DEVICE_TYPE INTEGER 0 -set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE -set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER -set_parameter_property PCORE_DEVICE_TYPE UNITS None -set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true # axi4 slave diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index 58a471406..0e00ddbaa 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -88,10 +88,10 @@ module axi_ad9265 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_ADC_DP_DISABLE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter ADC_DATAPATH_DISABLE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // adc interface (clk, data, over-range) @@ -203,8 +203,8 @@ module axi_ad9265 ( // channel axi_ad9265_channel #( - .CHID(0), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + .CHANNEL_ID(0), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -230,8 +230,8 @@ module axi_ad9265 ( // main (device interface) axi_ad9265_if #( - .PCORE_BUFTYPE (PCORE_DEVICE_TYPE), - .PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .DEVICE_TYPE (DEVICE_TYPE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_if ( .adc_clk_in_p (adc_clk_in_p), .adc_clk_in_n (adc_clk_in_n), @@ -253,7 +253,7 @@ module axi_ad9265 ( // adc delay control - up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked_s), @@ -273,7 +273,7 @@ module axi_ad9265 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v index 8f6f7590b..7c4504b0f 100644 --- a/library/axi_ad9265/axi_ad9265_channel.v +++ b/library/axi_ad9265/axi_ad9265_channel.v @@ -73,8 +73,8 @@ module axi_ad9265_channel ( // parameters - parameter CHID = 0; - parameter DP_DISABLE = 0; + parameter CHANNEL_ID = 0; + parameter DATAPATH_DISABLE = 0; // adc interface @@ -128,7 +128,7 @@ module axi_ad9265_channel ( .adc_pnseq_sel (adc_pnseq_sel_s)); generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dfmt_data_s = adc_data; end else begin ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt ( @@ -144,7 +144,7 @@ module axi_ad9265_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dcfilter_data_out = adc_dfmt_data_s; end else begin ad_dcfilter i_ad_dcfilter ( @@ -159,7 +159,7 @@ module axi_ad9265_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v index b02790d35..ad6d41025 100644 --- a/library/axi_ad9265/axi_ad9265_if.v +++ b/library/axi_ad9265/axi_ad9265_if.v @@ -70,8 +70,8 @@ module axi_ad9265_if ( // This parameter controls the buffer type based on the target device. - parameter PCORE_BUFTYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // adc interface (clk, data, over-range) // nominal clock 125 MHz, up to 300 MHz @@ -131,9 +131,9 @@ module axi_ad9265_if ( generate for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_data ( .rx_clk (adc_clk), .rx_data_in_p (adc_data_in_p[l_inst]), @@ -153,9 +153,9 @@ module axi_ad9265_if ( // over-range interface ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (1), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_or ( .rx_clk (adc_clk), .rx_data_in_p (adc_or_in_p), @@ -173,7 +173,7 @@ module axi_ad9265_if ( // clock ad_lvds_clk #( - .BUFTYPE (PCORE_BUFTYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 4a6957596..09fdacce6 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -153,12 +153,12 @@ module axi_ad9361 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_DAC_IODELAY_ENABLE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; - parameter PCORE_DAC_DP_DISABLE = 0; - parameter PCORE_ADC_DP_DISABLE = 0; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter DAC_IODELAY_ENABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; + parameter DAC_DATAPATH_DISABLE = 0; + parameter ADC_DATAPATH_DISABLE = 0; // physical interface (receive) @@ -346,9 +346,9 @@ module axi_ad9361 ( // device interface axi_ad9361_dev_if #( - .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), - .PCORE_DAC_IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE), - .PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .DEVICE_TYPE (DEVICE_TYPE), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_dev_if ( .rx_clk_in_p (rx_clk_in_p), .rx_clk_in_n (rx_clk_in_n), @@ -386,7 +386,7 @@ module axi_ad9361 ( // TDD interface - axi_ad9361_tdd_if #(.MODE_OF_ENABLE(1)) i_tdd_if( + axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if( .clk(clk), .rst(rst), .tdd_rx_vco_en(tdd_rx_vco_en_s), @@ -444,8 +444,8 @@ module axi_ad9361 ( // receive axi_ad9361_rx #( - .PCORE_ID (PCORE_ID), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + .ID (ID), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_rx ( .adc_rst (rst), .adc_clk (clk), @@ -491,8 +491,8 @@ module axi_ad9361 ( // transmit axi_ad9361_tx #( - .PCORE_ID (PCORE_ID), - .DP_DISABLE (PCORE_DAC_DP_DISABLE)) + .ID (ID), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) i_tx ( .dac_clk (clk), .dac_valid (dac_valid_s), diff --git a/library/axi_ad9361/axi_ad9361_dev_if.v b/library/axi_ad9361/axi_ad9361_dev_if.v index 62bf8530a..74155bb89 100644 --- a/library/axi_ad9361/axi_ad9361_dev_if.v +++ b/library/axi_ad9361/axi_ad9361_dev_if.v @@ -94,9 +94,9 @@ module axi_ad9361_dev_if ( // this parameter controls the buffer type based on the target device. - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_DAC_IODELAY_ENABLE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter DAC_IODELAY_ENABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; localparam PCORE_7SERIES = 0; localparam PCORE_VIRTEX6 = 1; @@ -377,9 +377,9 @@ module axi_ad9361_dev_if ( generate for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data ad_lvds_in #( - .BUFTYPE (PCORE_DEVICE_TYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_data ( .rx_clk (l_clk), .rx_data_in_p (rx_data_in_p[l_inst]), @@ -399,9 +399,9 @@ module axi_ad9361_dev_if ( // receive frame interface, ibuf -> idelay -> iddr ad_lvds_in #( - .BUFTYPE (PCORE_DEVICE_TYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (1), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_frame ( .rx_clk (l_clk), .rx_data_in_p (rx_frame_in_p), @@ -421,10 +421,10 @@ module axi_ad9361_dev_if ( generate for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data ad_lvds_out #( - .BUFTYPE (PCORE_DEVICE_TYPE), - .IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_tx_data ( .tx_clk (l_clk), .tx_data_p (tx_p_data_p[l_inst]), @@ -444,10 +444,10 @@ module axi_ad9361_dev_if ( // transmit frame interface, oddr -> obuf ad_lvds_out #( - .BUFTYPE (PCORE_DEVICE_TYPE), - .IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_tx_frame ( .tx_clk (l_clk), .tx_data_p (tx_p_frame), @@ -465,10 +465,10 @@ module axi_ad9361_dev_if ( // transmit clock interface, oddr -> obuf ad_lvds_out #( - .BUFTYPE (PCORE_DEVICE_TYPE), - .IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_tx_clk ( .tx_clk (l_clk), .tx_data_p (1'b0), @@ -486,7 +486,7 @@ module axi_ad9361_dev_if ( // device clock interface (receive clock) ad_lvds_clk #( - .BUFTYPE (PCORE_DEVICE_TYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_clk ( .clk_in_p (rx_clk_in_p), .clk_in_n (rx_clk_in_n), diff --git a/library/axi_ad9361/axi_ad9361_dev_if_alt.v b/library/axi_ad9361/axi_ad9361_dev_if_alt.v index 6164368ff..120b1820f 100644 --- a/library/axi_ad9361/axi_ad9361_dev_if_alt.v +++ b/library/axi_ad9361/axi_ad9361_dev_if_alt.v @@ -96,9 +96,9 @@ module axi_ad9361_dev_if ( // this parameter controls the buffer type based on the target device. - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_DAC_IODELAY_ENABLE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter DAC_IODELAY_ENABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; localparam PCORE_7SERIES = 0; localparam PCORE_VIRTEX6 = 1; diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index 9e80cc563..292830a8f 100755 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -53,19 +53,19 @@ add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FI # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true -add_parameter PCORE_DEVICE_TYPE INTEGER 0 -set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE -set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER -set_parameter_property PCORE_DEVICE_TYPE UNITS None -set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true # axi4 slave diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index 4a34e0147..e28ee0978 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -99,8 +99,8 @@ module axi_ad9361_rx ( // parameters - parameter DP_DISABLE = 0; - parameter PCORE_ID = 0; + parameter DATAPATH_DISABLE = 0; + parameter ID = 0; // adc interface @@ -205,9 +205,9 @@ module axi_ad9361_rx ( // channel 0 (i) axi_ad9361_rx_channel #( - .IQSEL(0), - .CHID(0), - .DP_DISABLE (DP_DISABLE)) + .Q_OR_I_N(0), + .CHANNEL_ID(0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_rx_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -238,9 +238,9 @@ module axi_ad9361_rx ( // channel 1 (q) axi_ad9361_rx_channel #( - .IQSEL(1), - .CHID(1), - .DP_DISABLE (DP_DISABLE)) + .Q_OR_I_N(1), + .CHANNEL_ID(1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_rx_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -271,9 +271,9 @@ module axi_ad9361_rx ( // channel 2 (i) axi_ad9361_rx_channel #( - .IQSEL(0), - .CHID(2), - .DP_DISABLE (DP_DISABLE)) + .Q_OR_I_N(0), + .CHANNEL_ID(2), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_rx_channel_2 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -304,9 +304,9 @@ module axi_ad9361_rx ( // channel 3 (q) axi_ad9361_rx_channel #( - .IQSEL(1), - .CHID(3), - .DP_DISABLE (DP_DISABLE)) + .Q_OR_I_N(1), + .CHANNEL_ID(3), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_rx_channel_3 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -336,7 +336,7 @@ module axi_ad9361_rx ( // common processor control - up_adc_common #(.PCORE_ID (PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID (ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -377,7 +377,7 @@ module axi_ad9361_rx ( // adc delay control - up_delay_cntrl #(.IO_WIDTH(7), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(7), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked), diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v index 197ebf967..558ea2a80 100644 --- a/library/axi_ad9361/axi_ad9361_rx_channel.v +++ b/library/axi_ad9361/axi_ad9361_rx_channel.v @@ -78,9 +78,9 @@ module axi_ad9361_rx_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; - parameter DP_DISABLE = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; + parameter DATAPATH_DISABLE = 0; // adc interface @@ -142,7 +142,7 @@ module axi_ad9361_rx_channel ( assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data; assign adc_dcfilter_data_out = adc_dcfilter_data_s; - axi_ad9361_rx_pnmon #(.IQSEL (IQSEL), .PRBS_SEL (CHID)) i_rx_pnmon ( + axi_ad9361_rx_pnmon #(.Q_OR_I_N (Q_OR_I_N), .PRBS_SEL (CHANNEL_ID)) i_rx_pnmon ( .adc_clk (adc_clk), .adc_valid (adc_valid), .adc_data_i (adc_data), @@ -152,7 +152,7 @@ module axi_ad9361_rx_channel ( .adc_pn_err (adc_pn_err_s)); generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dfmt_valid_s = adc_valid; assign adc_dfmt_data_s = {4'd0, adc_data_s}; end else begin @@ -169,7 +169,7 @@ module axi_ad9361_rx_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dcfilter_valid_s = adc_dfmt_valid_s; assign adc_dcfilter_data_s = adc_dfmt_data_s; end else begin @@ -186,11 +186,11 @@ module axi_ad9361_rx_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_iqcor_valid = adc_dcfilter_valid_s; assign adc_iqcor_data = adc_dcfilter_data_s; end else begin - ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor ( + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( .clk (adc_clk), .valid (adc_dcfilter_valid_s), .data_in (adc_dcfilter_data_s), @@ -203,7 +203,7 @@ module axi_ad9361_rx_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID (CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9361/axi_ad9361_rx_pnmon.v b/library/axi_ad9361/axi_ad9361_rx_pnmon.v index 9dfdab940..d69320178 100644 --- a/library/axi_ad9361/axi_ad9361_rx_pnmon.v +++ b/library/axi_ad9361/axi_ad9361_rx_pnmon.v @@ -57,7 +57,7 @@ module axi_ad9361_rx_pnmon ( // parameters - parameter IQSEL = 0; + parameter Q_OR_I_N = 0; parameter PRBS_SEL = 0; localparam PRBS_P09 = 0; localparam PRBS_P11 = 1; @@ -255,8 +255,8 @@ module axi_ad9361_rx_pnmon ( // device specific, assuming lower nibble is lost- - assign adc_pn0_data_i_s = (IQSEL == 1) ? adc_data_q : adc_data_i; - assign adc_pn0_data_q_s = (IQSEL == 1) ? adc_data_i : adc_data_q; + assign adc_pn0_data_i_s = (Q_OR_I_N == 1) ? adc_data_q : adc_data_i; + assign adc_pn0_data_q_s = (Q_OR_I_N == 1) ? adc_data_i : adc_data_q; assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s); assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]}; assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0; diff --git a/library/axi_ad9361/axi_ad9361_tdd_if.v b/library/axi_ad9361/axi_ad9361_tdd_if.v index a2c8df508..c7fcb7d8d 100644 --- a/library/axi_ad9361/axi_ad9361_tdd_if.v +++ b/library/axi_ad9361/axi_ad9361_tdd_if.v @@ -65,7 +65,7 @@ module axi_ad9361_tdd_if( // parameters - parameter MODE_OF_ENABLE = 0; + parameter LEVEL_OR_PULSE_N = 0; // the control signals are edge (pulse) or level sensitive localparam PULSE_MODE = 0; localparam LEVEL_MODE = 1; @@ -111,7 +111,7 @@ module axi_ad9361_tdd_if( tdd_tx_rf_en_d <= tdd_tx_rf_en; end - assign ad9361_enable_s = (MODE_OF_ENABLE == PULSE_MODE) ? + assign ad9361_enable_s = (LEVEL_OR_PULSE_N == PULSE_MODE) ? ((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) | (~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) : (tdd_rx_rf_en | tdd_tx_rf_en); diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index d302f4f9d..3924e3528 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -100,8 +100,8 @@ module axi_ad9361_tx ( // parameters - parameter DP_DISABLE = 0; - parameter PCORE_ID = 0; + parameter DATAPATH_DISABLE = 0; + parameter ID = 0; // dac interface @@ -189,7 +189,7 @@ module axi_ad9361_tx ( // master/slave - assign dac_data_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in; + assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; always @(posedge dac_clk) begin dac_data_sync <= dac_data_sync_s; @@ -235,9 +235,9 @@ module axi_ad9361_tx ( // dac channel axi_ad9361_tx_channel #( - .CHID (0), - .IQSEL (0), - .DP_DISABLE (DP_DISABLE)) + .CHANNEL_ID (0), + .Q_OR_I_N (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_tx_channel_0 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -264,9 +264,9 @@ module axi_ad9361_tx ( // dac channel axi_ad9361_tx_channel #( - .CHID (1), - .IQSEL (1), - .DP_DISABLE (DP_DISABLE)) + .CHANNEL_ID (1), + .Q_OR_I_N (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_tx_channel_1 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -293,9 +293,9 @@ module axi_ad9361_tx ( // dac channel axi_ad9361_tx_channel #( - .CHID (2), - .IQSEL (0), - .DP_DISABLE (DP_DISABLE)) + .CHANNEL_ID (2), + .Q_OR_I_N (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_tx_channel_2 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -322,9 +322,9 @@ module axi_ad9361_tx ( // dac channel axi_ad9361_tx_channel #( - .CHID (3), - .IQSEL (1), - .DP_DISABLE (DP_DISABLE)) + .CHANNEL_ID (3), + .Q_OR_I_N (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) i_tx_channel_3 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -350,7 +350,7 @@ module axi_ad9361_tx ( // dac common processor interface - up_dac_common #(.PCORE_ID (PCORE_ID)) i_up_dac_common ( + up_dac_common #(.ID (ID)) i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -389,7 +389,7 @@ module axi_ad9361_tx ( // dac delay control - up_delay_cntrl #(.IO_WIDTH(8), .IO_BASEADDR(6'h12)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(8), .BASE_ADDRESS(6'h12)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked), diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v index e424595fd..f64859640 100644 --- a/library/axi_ad9361/axi_ad9361_tx_channel.v +++ b/library/axi_ad9361/axi_ad9361_tx_channel.v @@ -73,10 +73,10 @@ module axi_ad9361_tx_channel ( // parameters - parameter CHID = 32'h0; - parameter IQSEL = 0; - parameter DP_DISABLE = 0; - localparam PRBS_SEL = CHID; + parameter CHANNEL_ID = 32'h0; + parameter Q_OR_I_N = 0; + parameter DATAPATH_DISABLE = 0; + localparam PRBS_SEL = CHANNEL_ID; localparam PRBS_P09 = 0; localparam PRBS_P11 = 1; localparam PRBS_P15 = 2; @@ -281,11 +281,11 @@ module axi_ad9361_tx_channel ( end generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_iqcor_valid_s = dac_valid; assign dac_iqcor_data_s = {dac_data_out, 4'd0}; end else begin - ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor ( + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( .clk (dac_clk), .valid (dac_valid), .data_in ({dac_data_out, 4'd0}), @@ -361,7 +361,7 @@ module axi_ad9361_tx_channel ( // dds generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_s = 16'd0; end else begin ad_dds i_dds ( @@ -377,7 +377,7 @@ module axi_ad9361_tx_channel ( // single channel processor - up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v index 53d4f0031..2a226e5e9 100644 --- a/library/axi_ad9434/axi_ad9434.v +++ b/library/axi_ad9434/axi_ad9434.v @@ -86,9 +86,9 @@ module axi_ad9434 ( localparam SERIES7 = 0; localparam SERIES6 = 1; - parameter PCORE_ID = 0; - parameter PCORE_DEVTYPE = SERIES7; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = SERIES7; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; // physical interface input adc_clk_in_p; @@ -178,8 +178,8 @@ module axi_ad9434 ( assign adc_enable = 1'b1; axi_ad9434_if #( - .PCORE_DEVTYPE(PCORE_DEVTYPE), - .PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP)) + .DEVICE_TYPE(DEVICE_TYPE), + .IO_DELAY_GROUP(IO_DELAY_GROUP)) i_if( .adc_clk_in_p(adc_clk_in_p), .adc_clk_in_n(adc_clk_in_n), @@ -210,7 +210,7 @@ module axi_ad9434 ( .up_drp_locked(up_drp_locked_s)); // common processor control - axi_ad9434_core #(.PCORE_ID(PCORE_ID)) + axi_ad9434_core #(.ID(ID)) i_core ( .adc_clk(adc_clk), .adc_data(adc_data_if_s), diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v index 0ac49b74e..a0d94d6af 100644 --- a/library/axi_ad9434/axi_ad9434_core.v +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -93,7 +93,7 @@ module axi_ad9434_core ( adc_status); // parameters - parameter PCORE_ID = 0; + parameter ID = 0; // device interface input adc_clk; @@ -200,7 +200,7 @@ module axi_ad9434_core ( end up_adc_common #( - .PCORE_ID(PCORE_ID)) + .ID(ID)) i_adc_common( .mmcm_rst (mmcm_rst), @@ -246,7 +246,7 @@ module axi_ad9434_core ( .up_rack (up_rack_s[0])); up_adc_channel #( - .PCORE_ADC_CHID(0)) + .ADC_CHANNEL_ID(0)) i_adc_channel( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -295,7 +295,7 @@ module axi_ad9434_core ( // adc delay control - up_delay_cntrl #(.IO_WIDTH(13), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked), diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index 57c3a7722..06970a67a 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -71,7 +71,7 @@ module axi_ad9434_if ( // mmcm reset mmcm_rst, - // drp interface for MMCM + // drp interface for MMCM_OR_BUFR_N up_rstn, up_drp_sel, up_drp_wr, @@ -82,11 +82,11 @@ module axi_ad9434_if ( up_drp_locked); // parameters - parameter PCORE_DEVTYPE = 0; // 0 - 7Series / 1 - 6Series - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series + parameter IO_DELAY_GROUP = "dev_if_delay_group"; // buffer type based on the target device. - localparam PCORE_BUFTYPE = PCORE_DEVTYPE; + localparam DEVICE_TYPE = DEVICE_TYPE; localparam SDR = 0; // adc interface (clk, data, over-range) @@ -151,11 +151,11 @@ module axi_ad9434_if ( generate for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if ad_serdes_in #( - .DEVICE_TYPE(PCORE_DEVTYPE), + .DEVICE_TYPE(DEVICE_TYPE), .IODELAY_CTRL(0), - .IODELAY_GROUP(PCORE_IODELAY_GROUP), - .IF_TYPE(SDR), - .PARALLEL_WIDTH(4)) + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(SDR), + .DATA_WIDTH(4)) i_adc_data ( .rst(adc_rst), .clk(adc_clk_in), @@ -182,11 +182,11 @@ module axi_ad9434_if ( // over-range interface ad_serdes_in #( - .DEVICE_TYPE(PCORE_DEVTYPE), + .DEVICE_TYPE(DEVICE_TYPE), .IODELAY_CTRL(1), - .IODELAY_GROUP(PCORE_IODELAY_GROUP), - .IF_TYPE(SDR), - .PARALLEL_WIDTH(4)) + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(SDR), + .DATA_WIDTH(4)) i_adc_data ( .rst(adc_rst), .clk(adc_clk_in), @@ -209,9 +209,9 @@ module axi_ad9434_if ( .delay_rst(delay_rst), .delay_locked(delay_locked)); - // clock input buffers and MMCM + // clock input buffers and MMCM_OR_BUFR_N ad_serdes_clk #( - .MMCM_DEVICE_TYPE (PCORE_DEVTYPE), + .MMCM_DEVICE_TYPE (DEVICE_TYPE), .MMCM_CLKIN_PERIOD (2), .MMCM_VCO_DIV (6), .MMCM_VCO_MUL (12), @@ -236,7 +236,7 @@ module axi_ad9434_if ( // adc overange assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3]; - // adc status: adc is up, if both the MMCM and DELAY blocks are up + // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up always @(posedge adc_div_clk) begin if(adc_rst == 1'b1) begin adc_status_m1 <= 1'b0; diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index 79725317b..63b1d4cbc 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -87,9 +87,9 @@ module axi_ad9467( // parameters - parameter PCORE_ID = 0; - parameter PCORE_BUFTYPE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; // physical interface @@ -192,8 +192,8 @@ module axi_ad9467( // main (device interface) axi_ad9467_if #( - .PCORE_BUFTYPE (PCORE_BUFTYPE), - .PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .DEVICE_TYPE (DEVICE_TYPE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_if ( .adc_clk_in_p (adc_clk_in_p), .adc_clk_in_n (adc_clk_in_n), @@ -215,7 +215,7 @@ module axi_ad9467( // channel - axi_ad9467_channel #(.CHID(0)) i_channel ( + axi_ad9467_channel #(.CHANNEL_ID(0)) i_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_s), @@ -238,7 +238,7 @@ module axi_ad9467( // adc delay control - up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked_s), @@ -258,7 +258,7 @@ module axi_ad9467( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9467/axi_ad9467_channel.v b/library/axi_ad9467/axi_ad9467_channel.v index 899453c51..75eb42672 100644 --- a/library/axi_ad9467/axi_ad9467_channel.v +++ b/library/axi_ad9467/axi_ad9467_channel.v @@ -69,7 +69,7 @@ module axi_ad9467_channel( // parameters - parameter CHID = 0; + parameter CHANNEL_ID = 0; // adc interface @@ -127,7 +127,7 @@ module axi_ad9467_channel( .dfmt_type(adc_dfmt_type_s), .dfmt_se(adc_dfmt_se_s)); - up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v index f7c9a7b56..d4379eb3c 100644 --- a/library/axi_ad9467/axi_ad9467_if.v +++ b/library/axi_ad9467/axi_ad9467_if.v @@ -74,8 +74,8 @@ module axi_ad9467_if ( // buffer type based on the target device. - parameter PCORE_BUFTYPE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; // adc interface (clk, data, over-range) @@ -165,9 +165,9 @@ module axi_ad9467_if ( generate for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_data ( .rx_clk (adc_clk), .rx_data_in_p (adc_data_in_p[l_inst]), @@ -187,9 +187,9 @@ module axi_ad9467_if ( // over-range interface ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (1), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_or ( .rx_clk (adc_clk), .rx_data_in_p (adc_or_in_p), @@ -207,7 +207,7 @@ module axi_ad9467_if ( // clock ad_lvds_clk #( - .BUFTYPE (PCORE_BUFTYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 3a78e37b8..4c6689c02 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -81,9 +81,9 @@ module axi_ad9625 ( s_axi_rdata, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is (line-rate/40) @@ -177,7 +177,7 @@ module axi_ad9625 ( assign adc_valid = 1'b1; - axi_ad9625_if #(.PCORE_ID(PCORE_ID)) i_if ( + axi_ad9625_if #(.ID(ID)) i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .adc_clk (adc_clk), @@ -214,7 +214,7 @@ module axi_ad9625 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v index 472f8b235..1b9c38960 100644 --- a/library/axi_ad9625/axi_ad9625_channel.v +++ b/library/axi_ad9625/axi_ad9625_channel.v @@ -131,7 +131,7 @@ module axi_ad9625_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v index 2fa69d411..51d2827ac 100644 --- a/library/axi_ad9625/axi_ad9625_if.v +++ b/library/axi_ad9625/axi_ad9625_if.v @@ -59,7 +59,7 @@ module axi_ad9625_if ( adc_raddr_in, adc_raddr_out); - parameter PCORE_ID = 0; + parameter ID = 0; // jesd interface // rx_clk is ref_clk/4 @@ -127,7 +127,7 @@ module axi_ad9625_if ( // synchronization mode, multiple instances - assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in; + assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in; always @(posedge rx_clk) begin adc_data <= adc_rdata_s; @@ -219,7 +219,7 @@ module axi_ad9625_if ( // alignment fifo - ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(192)) i_mem ( + ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(192)) i_mem ( .clka (rx_clk), .wea (1'b1), .addra (adc_waddr), diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v index b5cebb650..58aba5e54 100644 --- a/library/axi_ad9643/axi_ad9643.v +++ b/library/axi_ad9643/axi_ad9643.v @@ -91,10 +91,10 @@ module axi_ad9643 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_ADC_DP_DISABLE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter ADC_DATAPATH_DISABLE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // adc interface (clk, data, over-range) @@ -224,9 +224,9 @@ module axi_ad9643 ( // channel axi_ad9643_channel #( - .IQSEL(0), - .CHID(0), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + .Q_OR_I_N(0), + .CHANNEL_ID(0), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -253,9 +253,9 @@ module axi_ad9643 ( // channel axi_ad9643_channel #( - .IQSEL(1), - .CHID(1), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + .Q_OR_I_N(1), + .CHANNEL_ID(1), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -282,8 +282,8 @@ module axi_ad9643 ( // main (device interface) axi_ad9643_if #( - .PCORE_BUFTYPE (PCORE_DEVICE_TYPE), - .PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .DEVICE_TYPE (DEVICE_TYPE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_if ( .adc_clk_in_p (adc_clk_in_p), .adc_clk_in_n (adc_clk_in_n), @@ -309,7 +309,7 @@ module axi_ad9643 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -350,7 +350,7 @@ module axi_ad9643 ( // adc delay control - up_delay_cntrl #(.IO_WIDTH(15), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(15), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked_s), diff --git a/library/axi_ad9643/axi_ad9643_channel.v b/library/axi_ad9643/axi_ad9643_channel.v index 49758a309..093e05da1 100644 --- a/library/axi_ad9643/axi_ad9643_channel.v +++ b/library/axi_ad9643/axi_ad9643_channel.v @@ -72,9 +72,9 @@ module axi_ad9643_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; - parameter DP_DISABLE = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; + parameter DATAPATH_DISABLE = 0; // adc interface @@ -133,7 +133,7 @@ module axi_ad9643_channel ( .adc_pnseq_sel (adc_pnseq_sel_s)); generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dfmt_data_s = {2'd0, adc_data}; end else begin ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( @@ -149,7 +149,7 @@ module axi_ad9643_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dcfilter_data_out = adc_dfmt_data_s; end else begin ad_dcfilter i_ad_dcfilter ( @@ -167,10 +167,10 @@ module axi_ad9643_channel ( assign adc_dcfilter_data_out = adc_dcfilter_data_s; generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_iqcor_data = adc_dcfilter_data_s; end else begin - ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor ( + ad_iqcor #(.Q_OR_I_N(Q_OR_I_N)) i_ad_iqcor ( .clk (adc_clk), .valid (1'b1), .data_in (adc_dcfilter_data_s), @@ -183,7 +183,7 @@ module axi_ad9643_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9643/axi_ad9643_if.v b/library/axi_ad9643/axi_ad9643_if.v index 67d0b4457..fd6600489 100644 --- a/library/axi_ad9643/axi_ad9643_if.v +++ b/library/axi_ad9643/axi_ad9643_if.v @@ -79,8 +79,8 @@ module axi_ad9643_if ( // This parameter controls the buffer type based on the target device. - parameter PCORE_BUFTYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // adc interface (clk, data, over-range) @@ -201,9 +201,9 @@ module axi_ad9643_if ( generate for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_data ( .rx_clk (adc_clk), .rx_data_in_p (adc_data_in_p[l_inst]), @@ -223,9 +223,9 @@ module axi_ad9643_if ( // over-range interface ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (1), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_or ( .rx_clk (adc_clk), .rx_data_in_p (adc_or_in_p), @@ -243,7 +243,7 @@ module axi_ad9643_if ( // clock ad_lvds_clk #( - .BUFTYPE (PCORE_BUFTYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v index 61586a57a..d40c3d389 100644 --- a/library/axi_ad9652/axi_ad9652.v +++ b/library/axi_ad9652/axi_ad9652.v @@ -90,10 +90,10 @@ module axi_ad9652 ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_ADC_DP_DISABLE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter ADC_DATAPATH_DISABLE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // adc interface (clk, data, over-range) @@ -221,9 +221,9 @@ module axi_ad9652 ( // channel axi_ad9652_channel #( - .IQSEL(0), - .CHID(0), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + .Q_OR_I_N(0), + .CHANNEL_ID(0), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -250,9 +250,9 @@ module axi_ad9652 ( // channel axi_ad9652_channel #( - .IQSEL(1), - .CHID(1), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + .Q_OR_I_N(1), + .CHANNEL_ID(1), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -279,8 +279,8 @@ module axi_ad9652 ( // main (device interface) axi_ad9652_if #( - .PCORE_BUFTYPE (PCORE_DEVICE_TYPE), - .PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .DEVICE_TYPE (DEVICE_TYPE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_if ( .adc_clk_in_p (adc_clk_in_p), .adc_clk_in_n (adc_clk_in_n), @@ -305,7 +305,7 @@ module axi_ad9652 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -346,7 +346,7 @@ module axi_ad9652 ( // adc delay control - up_delay_cntrl #(.IO_WIDTH(17), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(17), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked_s), diff --git a/library/axi_ad9652/axi_ad9652_channel.v b/library/axi_ad9652/axi_ad9652_channel.v index fd7e61550..1c3f5adb5 100644 --- a/library/axi_ad9652/axi_ad9652_channel.v +++ b/library/axi_ad9652/axi_ad9652_channel.v @@ -74,9 +74,9 @@ module axi_ad9652_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; - parameter DP_DISABLE = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; + parameter DATAPATH_DISABLE = 0; // adc interface @@ -131,7 +131,7 @@ module axi_ad9652_channel ( .adc_pnseq_sel (adc_pnseq_sel_s)); generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_dcfilter_data_out = adc_data; end else begin ad_dcfilter i_ad_dcfilter ( @@ -149,10 +149,10 @@ module axi_ad9652_channel ( assign adc_dcfilter_data_out = adc_dcfilter_data_s; generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign adc_iqcor_data = adc_dcfilter_data_s; end else begin - ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor ( + ad_iqcor #(.Q_OR_I_N(Q_OR_I_N)) i_ad_iqcor ( .clk (adc_clk), .valid (1'b1), .data_in (adc_dcfilter_data_s), @@ -165,7 +165,7 @@ module axi_ad9652_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9652/axi_ad9652_if.v b/library/axi_ad9652/axi_ad9652_if.v index 11bdb0210..86075ddd6 100644 --- a/library/axi_ad9652/axi_ad9652_if.v +++ b/library/axi_ad9652/axi_ad9652_if.v @@ -78,8 +78,8 @@ module axi_ad9652_if ( // This parameter controls the buffer type based on the target device. - parameter PCORE_BUFTYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // adc interface (clk, data, over-range) @@ -170,9 +170,9 @@ module axi_ad9652_if ( generate for (l_inst = 0; l_inst <= 15; l_inst = l_inst + 1) begin : g_adc_if ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (0), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_data ( .rx_clk (adc_clk), .rx_data_in_p (adc_data_in_p[l_inst]), @@ -192,9 +192,9 @@ module axi_ad9652_if ( // over-range interface ad_lvds_in #( - .BUFTYPE (PCORE_BUFTYPE), + .DEVICE_TYPE (DEVICE_TYPE), .IODELAY_CTRL (1), - .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_or ( .rx_clk (adc_clk), .rx_data_in_p (adc_or_in_p), @@ -212,7 +212,7 @@ module axi_ad9652_if ( // clock ad_lvds_clk #( - .BUFTYPE (PCORE_BUFTYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 3128a4993..46406cfab 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -85,16 +85,16 @@ module axi_ad9671 ( s_axi_rdata, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_4L_2L_N = 1; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter QUAD_OR_DUAL_N = 1; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is the jesd clock (ref_clk/2) input rx_clk; - input [(64*PCORE_4L_2L_N)+63:0] rx_data; + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; input rx_sof; // dma interface @@ -201,8 +201,8 @@ module axi_ad9671 ( // main (device interface) axi_ad9671_if #( - .PCORE_4L_2L_N(PCORE_4L_2L_N), - .PCORE_ID(PCORE_ID) + .QUAD_OR_DUAL_N(QUAD_OR_DUAL_N), + .ID(ID) ) i_if ( .rx_clk (rx_clk), .rx_data (rx_data), @@ -240,7 +240,7 @@ module axi_ad9671 ( genvar n; generate for (n = 0; n < 8; n = n + 1) begin: g_channel - axi_ad9671_channel #(.CHID(n)) i_channel ( + axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_valid (adc_valid_s), @@ -268,7 +268,7 @@ module axi_ad9671 ( // common processor control up_adc_common #( - .PCORE_ID(PCORE_ID) + .ID(ID) ) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), @@ -311,7 +311,7 @@ module axi_ad9671 ( // up bus interface up_axi #( - .PCORE_ADDR_WIDTH (14) + .ADDRESS_WIDTH (14) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_ad9671/axi_ad9671_channel.v b/library/axi_ad9671/axi_ad9671_channel.v index 17af19de1..939fe8cdf 100644 --- a/library/axi_ad9671/axi_ad9671_channel.v +++ b/library/axi_ad9671/axi_ad9671_channel.v @@ -74,7 +74,7 @@ module axi_ad9671_channel ( // parameters - parameter CHID = 0; + parameter CHANNEL_ID = 0; // adc interface @@ -135,7 +135,7 @@ module axi_ad9671_channel ( .dfmt_type (adc_dfmt_type_s), .dfmt_se (adc_dfmt_se_s)); - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl index 4f8e04a5e..4d03ba575 100644 --- a/library/axi_ad9671/axi_ad9671_hw.tcl +++ b/library/axi_ad9671/axi_ad9671_hw.tcl @@ -31,26 +31,26 @@ add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true -add_parameter PCORE_DEVICE_TYPE INTEGER 0 -set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE -set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER -set_parameter_property PCORE_DEVICE_TYPE UNITS None -set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true -add_parameter PCORE_4L_2L_N INTEGER 0 -set_parameter_property PCORE_4L_2L_N DEFAULT_VALUE 1 -set_parameter_property PCORE_4L_2L_N DISPLAY_NAME PCORE_4L_2L_N -set_parameter_property PCORE_4L_2L_N TYPE INTEGER -set_parameter_property PCORE_4L_2L_N UNITS None -set_parameter_property PCORE_4L_2L_N HDL_PARAMETER true +add_parameter QUAD_OR_DUAL_N INTEGER 0 +set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 1 +set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N +set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER +set_parameter_property QUAD_OR_DUAL_N UNITS None +set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true # axi4 slave @@ -91,7 +91,7 @@ add_interface_port xcvr_clk rx_clk clk Input 1 add_interface xcvr_data conduit end set_interface_property xcvr_data associatedClock xcvr_clk -add_interface_port xcvr_data rx_data data Input 64*PCORE_4L_2L_N+64 +add_interface_port xcvr_data rx_data data Input 64*QUAD_OR_DUAL_N+64 add_interface_port xcvr_data rx_sof data_sof Input 1 add_interface xcvr_sync conduit end diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index dccb5669d..eb1bb2717 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -80,15 +80,15 @@ module axi_ad9671_if ( // parameters - parameter PCORE_4L_2L_N = 1; - parameter PCORE_ID = 0; + parameter QUAD_OR_DUAL_N = 1; + parameter ID = 0; // jesd interface // rx_clk is (line-rate/40) input rx_clk; input rx_sof; - input [(64*PCORE_4L_2L_N)+63:0] rx_data; + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; // adc data output @@ -181,8 +181,8 @@ module axi_ad9671_if ( assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s, adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s}; - assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in; - assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in; + assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in; + assign adc_sync_s = (ID == 0) ? adc_sync_out : adc_sync_in; always @(posedge rx_clk) begin adc_data_a <= adc_rdata[ 15: 0]; @@ -217,7 +217,7 @@ module axi_ad9671_if ( end always @(posedge rx_clk) begin - if (PCORE_4L_2L_N == 1'b1) begin + if (QUAD_OR_DUAL_N == 1'b1) begin int_valid <= 1'b1; int_data <= rx_data; end else begin @@ -236,7 +236,7 @@ module axi_ad9671_if ( end end - ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(128)) i_mem ( + ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem ( .clka(rx_clk), .wea(int_valid), .addra(adc_waddr), diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 6abbf52a1..2b1b8ed96 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -81,9 +81,9 @@ module axi_ad9680 ( s_axi_rdata, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is (line-rate/40) @@ -206,7 +206,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + axi_ad9680_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -229,7 +229,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + axi_ad9680_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), @@ -252,7 +252,7 @@ module axi_ad9680 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9680/axi_ad9680_channel.v b/library/axi_ad9680/axi_ad9680_channel.v index d3915750b..0192f7e61 100644 --- a/library/axi_ad9680/axi_ad9680_channel.v +++ b/library/axi_ad9680/axi_ad9680_channel.v @@ -72,8 +72,8 @@ module axi_ad9680_channel ( // parameters - parameter IQSEL = 0; - parameter CHID = 0; + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; // adc interface @@ -136,7 +136,7 @@ module axi_ad9680_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl index e00995b12..9a0103b86 100755 --- a/library/axi_ad9680/axi_ad9680_hw.tcl +++ b/library/axi_ad9680/axi_ad9680_hw.tcl @@ -32,12 +32,12 @@ add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true # axi4 slave diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v index 7f82708c5..e357648a5 100644 --- a/library/axi_ad9739a/axi_ad9739a.v +++ b/library/axi_ad9739a/axi_ad9739a.v @@ -85,12 +85,12 @@ module axi_ad9739a ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_SERDES_DDR_N = 1; - parameter PCORE_MMCM_BUFIO_N = 1; - parameter PCORE_DAC_DP_DISABLE = 0; - parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter SERDES_OR_DDR_N = 1; + parameter MMCM_OR_BUFIO_N = 1; + parameter DAC_DATAPATH_DISABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; // dac interface @@ -175,7 +175,7 @@ module axi_ad9739a ( // device interface - axi_ad9739a_if #(.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE)) i_if ( + axi_ad9739a_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .dac_clk_in_p (dac_clk_in_p), .dac_clk_in_n (dac_clk_in_n), .dac_clk_out_p (dac_clk_out_p), @@ -207,7 +207,7 @@ module axi_ad9739a ( // core - axi_ad9739a_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core ( + axi_ad9739a_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core ( .dac_div_clk (dac_div_clk), .dac_rst (dac_rst), .dac_data_00 (dac_data_00_s), diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v index 588f3edc0..3e8605054 100644 --- a/library/axi_ad9739a/axi_ad9739a_channel.v +++ b/library/axi_ad9739a/axi_ad9739a_channel.v @@ -84,8 +84,8 @@ module axi_ad9739a_channel ( // parameters - parameter CHID = 32'h0; - parameter DP_DISABLE = 0; + parameter CHANNEL_ID = 32'h0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -397,7 +397,7 @@ module axi_ad9739a_channel ( end generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_00_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -412,7 +412,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_01_s = 16'd0; end else begin ad_dds i_dds_1 ( @@ -427,7 +427,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_02_s = 16'd0; end else begin ad_dds i_dds_2 ( @@ -442,7 +442,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_03_s = 16'd0; end else begin ad_dds i_dds_3 ( @@ -457,7 +457,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_04_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -472,7 +472,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_05_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -487,7 +487,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_06_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -502,7 +502,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_07_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -517,7 +517,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_08_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -532,7 +532,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_09_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -547,7 +547,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_10_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -562,7 +562,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_11_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -577,7 +577,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_12_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -592,7 +592,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_13_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -607,7 +607,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_14_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -622,7 +622,7 @@ module axi_ad9739a_channel ( endgenerate generate - if (DP_DISABLE == 1) begin + if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_15_s = 16'd0; end else begin ad_dds i_dds_0 ( @@ -638,7 +638,7 @@ module axi_ad9739a_channel ( // single channel processor - up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_div_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v index fe416b302..12a2a34bc 100644 --- a/library/axi_ad9739a/axi_ad9739a_core.v +++ b/library/axi_ad9739a/axi_ad9739a_core.v @@ -86,8 +86,8 @@ module axi_ad9739a_core ( // parameters - parameter PCORE_ID = 0; - parameter DP_DISABLE = 0; + parameter ID = 0; + parameter DATAPATH_DISABLE = 0; // dac interface @@ -170,8 +170,8 @@ module axi_ad9739a_core ( // dac channel axi_ad9739a_channel #( - .CHID(0), - .DP_DISABLE(DP_DISABLE)) + .CHANNEL_ID(0), + .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 ( .dac_div_clk (dac_div_clk), .dac_rst (dac_rst), @@ -208,7 +208,7 @@ module axi_ad9739a_core ( // dac common processor interface - up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common ( + up_dac_common #(.ID(ID)) i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_div_clk), .dac_rst (dac_rst), diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index e71bf4930..f84187f69 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -82,7 +82,7 @@ module axi_ad9739a_if ( // parameters - parameter PCORE_DEVICE_TYPE = 0; + parameter DEVICE_TYPE = 0; // dac interface @@ -143,9 +143,9 @@ module axi_ad9739a_if ( // dac data output serdes(s) & buffers ad_serdes_out #( - .SERDES(1), + .SERDES_OR_DDR_N(1), .DATA_WIDTH(14), - .DEVICE_TYPE (PCORE_DEVICE_TYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_serdes_out_data_a ( .rst (dac_rst), .clk (dac_clk), @@ -164,9 +164,9 @@ module axi_ad9739a_if ( // dac data output serdes(s) & buffers ad_serdes_out #( - .SERDES(1), + .SERDES_OR_DDR_N(1), .DATA_WIDTH(14), - .DEVICE_TYPE (PCORE_DEVICE_TYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_serdes_out_data_b ( .rst (dac_rst), .clk (dac_clk), @@ -185,9 +185,9 @@ module axi_ad9739a_if ( // dac clock output serdes & buffer ad_serdes_out #( - .SERDES(1), + .SERDES_OR_DDR_N(1), .DATA_WIDTH(1), - .DEVICE_TYPE (PCORE_DEVICE_TYPE)) + .DEVICE_TYPE (DEVICE_TYPE)) i_serdes_out_clk ( .rst (dac_rst), .clk (dac_clk), diff --git a/library/axi_adcfifo/axi_adcfifo.v b/library/axi_adcfifo/axi_adcfifo.v index 5a7faaad3..99b1f2a1b 100644 --- a/library/axi_adcfifo/axi_adcfifo.v +++ b/library/axi_adcfifo/axi_adcfifo.v @@ -114,7 +114,7 @@ module axi_adcfifo ( parameter AXI_SIZE = 2; parameter AXI_LENGTH = 16; parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRLIMIT = 32'hffffffff; + parameter AXI_ADDRESS_LIMIT = 32'hffffffff; parameter AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; // adc interface @@ -215,7 +215,7 @@ module axi_adcfifo ( .AXI_SIZE (AXI_SIZE), .AXI_LENGTH (AXI_LENGTH), .AXI_ADDRESS (AXI_ADDRESS), - .AXI_ADDRLIMIT (AXI_ADDRLIMIT)) + .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)) i_wr ( .dma_xfer_req (dma_xfer_req), .axi_rd_req (axi_rd_req_s), @@ -258,7 +258,7 @@ module axi_adcfifo ( .AXI_SIZE (AXI_SIZE), .AXI_LENGTH (AXI_LENGTH), .AXI_ADDRESS (AXI_ADDRESS), - .AXI_ADDRLIMIT (AXI_ADDRLIMIT)) + .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)) i_rd ( .dma_xfer_req (dma_xfer_req), .axi_rd_req (axi_rd_req_s), diff --git a/library/axi_adcfifo/axi_adcfifo_dma.v b/library/axi_adcfifo/axi_adcfifo_dma.v index 7de6c3d87..5ebdd0c0a 100644 --- a/library/axi_adcfifo/axi_adcfifo_dma.v +++ b/library/axi_adcfifo/axi_adcfifo_dma.v @@ -62,9 +62,9 @@ module axi_adcfifo_dma ( parameter DMA_READY_ENABLE = 1; localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; - localparam DMA_ADDR_WIDTH = 8; - localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) : - ((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3)); + localparam DMA_ADDRESS_WIDTH = 8; + localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : + ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3)); // adc write @@ -86,32 +86,32 @@ module axi_adcfifo_dma ( // internal registers - reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0; + reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0; reg [ 2:0] axi_waddr_rel_count = 'd0; reg axi_waddr_rel_t = 'd0; - reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0; + reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0; reg [ 2:0] axi_raddr_rel_t_m = 'd0; - reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0; - reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0; reg axi_dready = 'd0; reg dma_rst = 'd0; reg [ 2:0] dma_waddr_rel_t_m = 'd0; - reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0; + reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0; reg dma_rd = 'd0; reg dma_rd_d = 'd0; reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0; - reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0; reg [ 2:0] dma_raddr_rel_count = 'd0; reg dma_raddr_rel_t = 'd0; - reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0; // internal signals - wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s; + wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s; wire axi_raddr_rel_t_s; - wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s; + wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s; wire dma_waddr_rel_t_s; - wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s; + wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s; wire dma_wready_s; wire dma_rd_s; wire [DMA_DATA_WIDTH-1:0] dma_rdata_s; @@ -152,7 +152,7 @@ module axi_adcfifo_dma ( if (axi_raddr_rel_t_s == 1'b1) begin axi_raddr_rel <= dma_raddr_rel; end - axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0]; + axi_addr_diff <= axi_addr_diff_s[DMA_ADDRESS_WIDTH-1:0]; if (axi_addr_diff >= 180) begin axi_dready <= 1'b0; end else if (axi_addr_diff <= 8) begin @@ -211,10 +211,10 @@ module axi_adcfifo_dma ( // instantiations ad_mem_asym #( - .ADDR_WIDTH_A (AXI_ADDR_WIDTH), - .DATA_WIDTH_A (AXI_DATA_WIDTH), - .ADDR_WIDTH_B (DMA_ADDR_WIDTH), - .DATA_WIDTH_B (DMA_DATA_WIDTH)) + .A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH), + .A_DATA_WIDTH (AXI_DATA_WIDTH), + .B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), + .B_DATA_WIDTH (DMA_DATA_WIDTH)) i_mem_asym ( .clka (axi_clk), .wea (axi_dvalid), diff --git a/library/axi_adcfifo/axi_adcfifo_rd.v b/library/axi_adcfifo/axi_adcfifo_rd.v index 9069e3ffb..8018d4678 100644 --- a/library/axi_adcfifo/axi_adcfifo_rd.v +++ b/library/axi_adcfifo/axi_adcfifo_rd.v @@ -91,7 +91,7 @@ module axi_adcfifo_rd ( parameter AXI_SIZE = 2; parameter AXI_LENGTH = 16; parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRLIMIT = 32'h00000000; + parameter AXI_ADDRESS_LIMIT = 32'h00000000; localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH; localparam BUF_THRESHOLD_LO = 6'd3; diff --git a/library/axi_adcfifo/axi_adcfifo_wr.v b/library/axi_adcfifo/axi_adcfifo_wr.v index d34cf430d..7a21dc8fe 100644 --- a/library/axi_adcfifo/axi_adcfifo_wr.v +++ b/library/axi_adcfifo/axi_adcfifo_wr.v @@ -97,7 +97,7 @@ module axi_adcfifo_wr ( parameter AXI_SIZE = 2; parameter AXI_LENGTH = 16; parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRLIMIT = 32'h00000000; + parameter AXI_ADDRESS_LIMIT = 32'h00000000; localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH; localparam BUF_THRESHOLD_LO = 8'd6; @@ -259,7 +259,7 @@ module axi_adcfifo_wr ( adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2]; if (adc_xfer_init == 1'b1) begin adc_xfer_limit <= 1'd1; - end else if ((adc_xfer_addr >= AXI_ADDRLIMIT) || (adc_xfer_enable == 1'b0)) begin + end else if ((adc_xfer_addr >= AXI_ADDRESS_LIMIT) || (adc_xfer_enable == 1'b0)) begin adc_xfer_limit <= 1'd0; end if (adc_xfer_init == 1'b1) begin @@ -464,7 +464,7 @@ module axi_adcfifo_wr ( // buffer - ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDR_WIDTH(8)) i_mem ( + ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDRESS_WIDTH(8)) i_mem ( .clka (adc_clk), .wea (adc_wr), .addra (adc_waddr), diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index 92caa870b..bd09aa4b1 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -68,13 +68,13 @@ module axi_clkgen ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_CLKIN_PERIOD = 5.0; - parameter PCORE_VCO_DIV = 11; - parameter PCORE_VCO_MUL = 49; - parameter PCORE_CLK0_DIV = 6; - parameter PCORE_CLK1_DIV = 6; + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter CLKIN_PERIOD = 5.0; + parameter VCO_DIV = 11; + parameter VCO_MUL = 49; + parameter CLK0_DIV = 6; + parameter CLK1_DIV = 6; // clocks @@ -189,12 +189,12 @@ module axi_clkgen ( // mmcm instantiations ad_mmcm_drp #( - .MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE), - .MMCM_CLKIN_PERIOD (PCORE_CLKIN_PERIOD), - .MMCM_VCO_DIV (PCORE_VCO_DIV), - .MMCM_VCO_MUL (PCORE_VCO_MUL), - .MMCM_CLK0_DIV (PCORE_CLK0_DIV), - .MMCM_CLK1_DIV (PCORE_CLK1_DIV)) + .MMCM_DEVICE_TYPE (DEVICE_TYPE), + .MMCM_CLKIN_PERIOD (CLKIN_PERIOD), + .MMCM_VCO_DIV (VCO_DIV), + .MMCM_VCO_MUL (VCO_MUL), + .MMCM_CLK0_DIV (CLK0_DIV), + .MMCM_CLK1_DIV (CLK1_DIV)) i_mmcm_drp ( .clk (clk), .mmcm_rst (mmcm_rst), diff --git a/library/axi_dmac/2d_transfer.v b/library/axi_dmac/2d_transfer.v index 3bc22f617..6f9c25549 100644 --- a/library/axi_dmac/2d_transfer.v +++ b/library/axi_dmac/2d_transfer.v @@ -43,34 +43,34 @@ module dmac_2d_transfer ( input req_valid, output reg req_ready, - input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, - input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address, - input [C_DMA_LENGTH_WIDTH-1:0] req_x_length, - input [C_DMA_LENGTH_WIDTH-1:0] req_y_length, - input [C_DMA_LENGTH_WIDTH-1:0] req_dest_stride, - input [C_DMA_LENGTH_WIDTH-1:0] req_src_stride, + input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_x_length, + input [DMA_LENGTH_WIDTH-1:0] req_y_length, + input [DMA_LENGTH_WIDTH-1:0] req_dest_stride, + input [DMA_LENGTH_WIDTH-1:0] req_src_stride, input req_sync_transfer_start, output reg req_eot, output reg out_req_valid, input out_req_ready, - output [31:C_BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, - output [31:C_BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address, - output [C_DMA_LENGTH_WIDTH-1:0] out_req_length, + output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, + output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address, + output [DMA_LENGTH_WIDTH-1:0] out_req_length, output reg out_req_sync_transfer_start, input out_eot ); -parameter C_DMA_LENGTH_WIDTH = 24; -parameter C_BYTES_PER_BEAT_WIDTH_SRC = 3; -parameter C_BYTES_PER_BEAT_WIDTH_DEST = 3; +parameter DMA_LENGTH_WIDTH = 24; +parameter BYTES_PER_BEAT_WIDTH_SRC = 3; +parameter BYTES_PER_BEAT_WIDTH_DEST = 3; -reg [31:C_BYTES_PER_BEAT_WIDTH_DEST] dest_address; -reg [31:C_BYTES_PER_BEAT_WIDTH_SRC] src_address; -reg [C_DMA_LENGTH_WIDTH-1:0] x_length; -reg [C_DMA_LENGTH_WIDTH-1:0] y_length; -reg [C_DMA_LENGTH_WIDTH-1:0] dest_stride; -reg [C_DMA_LENGTH_WIDTH-1:0] src_stride; +reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address; +reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address; +reg [DMA_LENGTH_WIDTH-1:0] x_length; +reg [DMA_LENGTH_WIDTH-1:0] y_length; +reg [DMA_LENGTH_WIDTH-1:0] dest_stride; +reg [DMA_LENGTH_WIDTH-1:0] src_stride; reg [1:0] req_id; reg [1:0] eot_id; @@ -126,8 +126,8 @@ begin end end else begin if (out_req_valid && out_req_ready) begin - dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST]; - src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC]; + dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; + src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; y_length <= y_length - 1'b1; out_req_sync_transfer_start <= 1'b0; if (y_length == 0) begin diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 9fcce1ba3..56320b605 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -41,11 +41,11 @@ module dmac_address_generator ( input req_valid, output reg req_ready, - input [31:C_BYTES_PER_BEAT_WIDTH] req_address, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - output reg [C_ID_WIDTH-1:0] id, - input [C_ID_WIDTH-1:0] request_id, + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, input sync_id, input eot, @@ -65,11 +65,11 @@ module dmac_address_generator ( ); -parameter C_ID_WIDTH = 3; -parameter C_DMA_DATA_WIDTH = 64; -parameter C_BEATS_PER_BURST_WIDTH = 4; -parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8); -localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH); +parameter ID_WIDTH = 3; +parameter DMA_DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; +parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8); +localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH); `include "inc_id.h" @@ -77,12 +77,12 @@ assign burst = 2'b01; assign prot = 3'b000; assign cache = 4'b0011; assign len = length; -assign size = $clog2(C_DMA_DATA_WIDTH/8); +assign size = $clog2(DMA_DATA_WIDTH/8); reg [7:0] length = 'h0; -reg [31-C_BYTES_PER_BEAT_WIDTH:0] address = 'h00; -reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00; -assign addr = {address, {C_BYTES_PER_BEAT_WIDTH{1'b0}}}; +reg [31-BYTES_PER_BEAT_WIDTH:0] address = 'h00; +reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00; +assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}}; reg addr_valid_d1; reg last = 1'b0; diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 5c1ebac81..fb36a65b3 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -72,7 +72,7 @@ module axi_dmac ( // Write address output [31:0] m_dest_axi_awaddr, - output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen, output [ 2:0] m_dest_axi_awsize, output [ 1:0] m_dest_axi_awburst, output [ 2:0] m_dest_axi_awprot, @@ -81,8 +81,8 @@ module axi_dmac ( input m_dest_axi_awready, // Write data - output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata, - output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb, + output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb, input m_dest_axi_wready, output m_dest_axi_wvalid, output m_dest_axi_wlast, @@ -95,7 +95,7 @@ module axi_dmac ( // Unused read interface output m_dest_axi_arvalid, output [31:0] m_dest_axi_araddr, - output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, output [ 2:0] m_dest_axi_arsize, output [ 1:0] m_dest_axi_arburst, output [ 3:0] m_dest_axi_arcache, @@ -103,21 +103,21 @@ module axi_dmac ( input m_dest_axi_arready, input m_dest_axi_rvalid, input [ 1:0] m_dest_axi_rresp, - input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata, + input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata, output m_dest_axi_rready, // Read address input m_src_axi_arready, output m_src_axi_arvalid, output [31:0] m_src_axi_araddr, - output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen, output [ 2:0] m_src_axi_arsize, output [ 1:0] m_src_axi_arburst, output [ 2:0] m_src_axi_arprot, output [ 3:0] m_src_axi_arcache, // Read data and response - input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata, + input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata, output m_src_axi_rready, input m_src_axi_rvalid, input [ 1:0] m_src_axi_rresp, @@ -125,15 +125,15 @@ module axi_dmac ( // Unused write interface output m_src_axi_awvalid, output [31:0] m_src_axi_awaddr, - output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, output [ 2:0] m_src_axi_awsize, output [ 1:0] m_src_axi_awburst, output [ 3:0] m_src_axi_awcache, output [ 2:0] m_src_axi_awprot, input m_src_axi_awready, output m_src_axi_wvalid, - output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata, - output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb, + output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata, + output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb, output m_src_axi_wlast, input m_src_axi_wready, input m_src_axi_bvalid, @@ -144,7 +144,7 @@ module axi_dmac ( input s_axis_aclk, output s_axis_ready, input s_axis_valid, - input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, input [0:0] s_axis_user, output s_axis_xfer_req, @@ -152,14 +152,14 @@ module axi_dmac ( input m_axis_aclk, input m_axis_ready, output m_axis_valid, - output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, output m_axis_last, output m_axis_xfer_req, // Input FIFO interface input fifo_wr_clk, input fifo_wr_en, - input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, output fifo_wr_overflow, input fifo_wr_sync, output fifo_wr_xfer_req, @@ -168,34 +168,34 @@ module axi_dmac ( input fifo_rd_clk, input fifo_rd_en, output fifo_rd_valid, - output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, output fifo_rd_underflow, output fifo_rd_xfer_req ); -parameter PCORE_ID = 0; +parameter ID = 0; -parameter C_DMA_DATA_WIDTH_SRC = 64; -parameter C_DMA_DATA_WIDTH_DEST = 64; -parameter C_DMA_LENGTH_WIDTH = 24; -parameter C_2D_TRANSFER = 1; +parameter DMA_DATA_WIDTH_SRC = 64; +parameter DMA_DATA_WIDTH_DEST = 64; +parameter DMA_LENGTH_WIDTH = 24; +parameter 2D_TRANSFER = 1; -parameter C_CLKS_ASYNC_REQ_SRC = 1; -parameter C_CLKS_ASYNC_SRC_DEST = 1; -parameter C_CLKS_ASYNC_DEST_REQ = 1; +parameter ASYNC_CLK_REQ_SRC = 1; +parameter ASYNC_CLK_SRC_DEST = 1; +parameter ASYNC_CLK_DEST_REQ = 1; -parameter C_AXI_SLICE_DEST = 0; -parameter C_AXI_SLICE_SRC = 0; -parameter C_SYNC_TRANSFER_START = 0; -parameter C_CYCLIC = 1; +parameter AXI_SLICE_DEST = 0; +parameter AXI_SLICE_SRC = 0; +parameter SYNC_TRANSFER_START = 0; +parameter CYCLIC = 1; -parameter C_DMA_AXI_PROTOCOL_DEST = 0; -parameter C_DMA_AXI_PROTOCOL_SRC = 0; -parameter C_DMA_TYPE_DEST = 0; -parameter C_DMA_TYPE_SRC = 2; +parameter DMA_AXI_PROTOCOL_DEST = 0; +parameter DMA_AXI_PROTOCOL_SRC = 0; +parameter DMA_TYPE_DEST = 0; +parameter DMA_TYPE_SRC = 2; -parameter C_MAX_BYTES_PER_BURST = 128; -parameter C_FIFO_SIZE = 4; // In bursts +parameter MAX_BYTES_PER_BURST = 128; +parameter FIFO_SIZE = 4; // In bursts localparam DMA_TYPE_AXI_MM = 0; localparam DMA_TYPE_AXI_STREAM = 1; @@ -203,26 +203,26 @@ localparam DMA_TYPE_FIFO = 2; localparam PCORE_VERSION = 'h00040062; -localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM; -localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM; +localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM; +localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM; // Argh... "[Synth 8-2722] system function call clog2 is not allowed here" -localparam BYTES_PER_BEAT_WIDTH_DEST = C_DMA_DATA_WIDTH_DEST > 1024 ? 8 : - C_DMA_DATA_WIDTH_DEST > 512 ? 7 : - C_DMA_DATA_WIDTH_DEST > 256 ? 6 : - C_DMA_DATA_WIDTH_DEST > 128 ? 5 : - C_DMA_DATA_WIDTH_DEST > 64 ? 4 : - C_DMA_DATA_WIDTH_DEST > 32 ? 3 : - C_DMA_DATA_WIDTH_DEST > 16 ? 2 : - C_DMA_DATA_WIDTH_DEST > 8 ? 1 : 0; -localparam BYTES_PER_BEAT_WIDTH_SRC = C_DMA_DATA_WIDTH_SRC > 1024 ? 8 : - C_DMA_DATA_WIDTH_SRC > 512 ? 7 : - C_DMA_DATA_WIDTH_SRC > 256 ? 6 : - C_DMA_DATA_WIDTH_SRC > 128 ? 5 : - C_DMA_DATA_WIDTH_SRC > 64 ? 4 : - C_DMA_DATA_WIDTH_SRC > 32 ? 3 : - C_DMA_DATA_WIDTH_SRC > 16 ? 2 : - C_DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; +localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 : + DMA_DATA_WIDTH_DEST > 512 ? 7 : + DMA_DATA_WIDTH_DEST > 256 ? 6 : + DMA_DATA_WIDTH_DEST > 128 ? 5 : + DMA_DATA_WIDTH_DEST > 64 ? 4 : + DMA_DATA_WIDTH_DEST > 32 ? 3 : + DMA_DATA_WIDTH_DEST > 16 ? 2 : + DMA_DATA_WIDTH_DEST > 8 ? 1 : 0; +localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 : + DMA_DATA_WIDTH_SRC > 512 ? 7 : + DMA_DATA_WIDTH_SRC > 256 ? 6 : + DMA_DATA_WIDTH_SRC > 128 ? 5 : + DMA_DATA_WIDTH_SRC > 64 ? 4 : + DMA_DATA_WIDTH_SRC > 32 ? 3 : + DMA_DATA_WIDTH_SRC > 16 ? 2 : + DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; // Register interface signals reg [31:0] up_rdata = 'd0; @@ -263,12 +263,12 @@ reg up_axis_xlast = 1'b1; reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00; reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00; -reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00; -reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00; -reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00; -reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00; -reg up_dma_cyclic = C_CYCLIC; -wire up_dma_sync_transfer_start = C_SYNC_TRANSFER_START ? 1'b1 : 1'b0; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00; +reg up_dma_cyclic = CYCLIC; +wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0; // ID signals from the DMAC, just for debugging wire [2:0] dest_request_id; @@ -298,7 +298,7 @@ assign m_src_axi_wstrb = 'd0; assign m_src_axi_wlast = 'd0; up_axi #( - .PCORE_ADDR_WIDTH (12) + .ADDRESS_WIDTH (12) ) i_up_axi ( .up_rstn(s_axi_aresetn), .up_clk(s_axi_aclk), @@ -386,15 +386,15 @@ begin 12'h020: up_irq_mask <= up_wdata; 12'h100: {up_pause, up_enable} <= up_wdata[1:0]; 12'h103: begin - if (C_CYCLIC) up_dma_cyclic <= up_wdata[0]; + if (CYCLIC) up_dma_cyclic <= up_wdata[0]; up_axis_xlast <= up_wdata[1]; end 12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST]; 12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC]; - 12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0]; - 12'h107: up_dma_y_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0]; - 12'h108: up_dma_dest_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0]; - 12'h109: up_dma_src_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0]; + 12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; endcase end end @@ -409,7 +409,7 @@ begin up_rack <= up_rreq; case (up_raddr) 12'h000: up_rdata <= PCORE_VERSION; - 12'h001: up_rdata <= PCORE_ID; + 12'h001: up_rdata <= ID; 12'h002: up_rdata <= up_scratch; 12'h020: up_rdata <= up_irq_mask; 12'h021: up_rdata <= up_irq_pending; @@ -421,9 +421,9 @@ begin 12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00; 12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00; 12'h106: up_rdata <= up_dma_x_length; - 12'h107: up_rdata <= C_2D_TRANSFER ? up_dma_y_length : 'h00; - 12'h108: up_rdata <= C_2D_TRANSFER ? up_dma_dest_stride : 'h00; - 12'h109: up_rdata <= C_2D_TRANSFER ? up_dma_src_stride : 'h00; + 12'h107: up_rdata <= 2D_TRANSFER ? up_dma_y_length : 'h00; + 12'h108: up_rdata <= 2D_TRANSFER ? up_dma_dest_stride : 'h00; + 12'h109: up_rdata <= 2D_TRANSFER ? up_dma_src_stride : 'h00; 12'h10a: up_rdata <= up_transfer_done_bitmap; 12'h10b: up_rdata <= up_transfer_id_eot; 12'h10c: up_rdata <= 'h00; // Status @@ -460,7 +460,7 @@ wire dma_req_valid; wire dma_req_ready; wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address; wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address; -wire [C_DMA_LENGTH_WIDTH-1:0] dma_req_length; +wire [DMA_LENGTH_WIDTH-1:0] dma_req_length; wire dma_req_eot; wire dma_req_sync_transfer_start; wire up_req_eot; @@ -469,12 +469,12 @@ assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready; assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot; -generate if (C_2D_TRANSFER == 1) begin +generate if (2D_TRANSFER == 1) begin dmac_2d_transfer #( - .C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH), - .C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), - .C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC) + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC) ) i_2d_transfer ( .req_aclk(s_axi_aclk), .req_aresetn(s_axi_aresetn), @@ -513,20 +513,20 @@ assign up_req_eot = dma_req_eot; end endgenerate dmac_request_arb #( - .C_DMA_DATA_WIDTH_SRC(C_DMA_DATA_WIDTH_SRC), - .C_DMA_DATA_WIDTH_DEST(C_DMA_DATA_WIDTH_DEST), - .C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH), - .C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), - .C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), - .C_DMA_TYPE_DEST(C_DMA_TYPE_DEST), - .C_DMA_TYPE_SRC(C_DMA_TYPE_SRC), - .C_CLKS_ASYNC_REQ_SRC(C_CLKS_ASYNC_REQ_SRC), - .C_CLKS_ASYNC_SRC_DEST(C_CLKS_ASYNC_SRC_DEST), - .C_CLKS_ASYNC_DEST_REQ(C_CLKS_ASYNC_DEST_REQ), - .C_AXI_SLICE_DEST(C_AXI_SLICE_DEST), - .C_AXI_SLICE_SRC(C_AXI_SLICE_SRC), - .C_MAX_BYTES_PER_BURST(C_MAX_BYTES_PER_BURST), - .C_FIFO_SIZE(C_FIFO_SIZE) + .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .DMA_TYPE_DEST(DMA_TYPE_DEST), + .DMA_TYPE_SRC(DMA_TYPE_SRC), + .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC), + .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST), + .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ), + .AXI_SLICE_DEST(AXI_SLICE_DEST), + .AXI_SLICE_SRC(AXI_SLICE_SRC), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST), + .FIFO_SIZE(FIFO_SIZE) ) i_request_arb ( .req_aclk(s_axi_aclk), .req_aresetn(s_axi_aresetn), diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl index accc99347..2d0732dc8 100755 --- a/library/axi_dmac/axi_dmac_hw.tcl +++ b/library/axi_dmac/axi_dmac_hw.tcl @@ -45,12 +45,12 @@ add_fileset_file axi_dmac_constr.sdc SDC PATH axi_dmac_constr.sdc # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0 set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64 @@ -80,26 +80,26 @@ set_parameter_property C_2D_TRANSFER TYPE INTEGER set_parameter_property C_2D_TRANSFER UNITS None set_parameter_property C_2D_TRANSFER HDL_PARAMETER true -add_parameter C_CLKS_ASYNC_REQ_SRC INTEGER 0 -set_parameter_property C_CLKS_ASYNC_REQ_SRC DEFAULT_VALUE 1 -set_parameter_property C_CLKS_ASYNC_REQ_SRC DISPLAY_NAME C_CLKS_ASYNC_REQ_SRC -set_parameter_property C_CLKS_ASYNC_REQ_SRC TYPE INTEGER -set_parameter_property C_CLKS_ASYNC_REQ_SRC UNITS None -set_parameter_property C_CLKS_ASYNC_REQ_SRC HDL_PARAMETER true +add_parameter ASYNC_CLK_REQ_SRC INTEGER 0 +set_parameter_property ASYNC_CLK_REQ_SRC DEFAULT_VALUE 1 +set_parameter_property ASYNC_CLK_REQ_SRC DISPLAY_NAME ASYNC_CLK_REQ_SRC +set_parameter_property ASYNC_CLK_REQ_SRC TYPE INTEGER +set_parameter_property ASYNC_CLK_REQ_SRC UNITS None +set_parameter_property ASYNC_CLK_REQ_SRC HDL_PARAMETER true -add_parameter C_CLKS_ASYNC_SRC_DEST INTEGER 0 -set_parameter_property C_CLKS_ASYNC_SRC_DEST DEFAULT_VALUE 1 -set_parameter_property C_CLKS_ASYNC_SRC_DEST DISPLAY_NAME C_CLKS_ASYNC_SRC_DEST -set_parameter_property C_CLKS_ASYNC_SRC_DEST TYPE INTEGER -set_parameter_property C_CLKS_ASYNC_SRC_DEST UNITS None -set_parameter_property C_CLKS_ASYNC_SRC_DEST HDL_PARAMETER true +add_parameter ASYNC_CLK_SRC_DEST INTEGER 0 +set_parameter_property ASYNC_CLK_SRC_DEST DEFAULT_VALUE 1 +set_parameter_property ASYNC_CLK_SRC_DEST DISPLAY_NAME ASYNC_CLK_SRC_DEST +set_parameter_property ASYNC_CLK_SRC_DEST TYPE INTEGER +set_parameter_property ASYNC_CLK_SRC_DEST UNITS None +set_parameter_property ASYNC_CLK_SRC_DEST HDL_PARAMETER true -add_parameter C_CLKS_ASYNC_DEST_REQ INTEGER 0 -set_parameter_property C_CLKS_ASYNC_DEST_REQ DEFAULT_VALUE 1 -set_parameter_property C_CLKS_ASYNC_DEST_REQ DISPLAY_NAME C_CLKS_ASYNC_DEST_REQ -set_parameter_property C_CLKS_ASYNC_DEST_REQ TYPE INTEGER -set_parameter_property C_CLKS_ASYNC_DEST_REQ UNITS None -set_parameter_property C_CLKS_ASYNC_DEST_REQ HDL_PARAMETER true +add_parameter ASYNC_CLK_DEST_REQ INTEGER 0 +set_parameter_property ASYNC_CLK_DEST_REQ DEFAULT_VALUE 1 +set_parameter_property ASYNC_CLK_DEST_REQ DISPLAY_NAME ASYNC_CLK_DEST_REQ +set_parameter_property ASYNC_CLK_DEST_REQ TYPE INTEGER +set_parameter_property ASYNC_CLK_DEST_REQ UNITS None +set_parameter_property ASYNC_CLK_DEST_REQ HDL_PARAMETER true add_parameter C_AXI_SLICE_DEST INTEGER 0 set_parameter_property C_AXI_SLICE_DEST DEFAULT_VALUE 0 diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index bf87afe88..0c883d5fd 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -40,8 +40,8 @@ module dmac_data_mover ( input clk, input resetn, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, input sync_id, input eot, @@ -52,30 +52,30 @@ module dmac_data_mover ( output s_axi_ready, input s_axi_valid, - input [C_DATA_WIDTH-1:0] s_axi_data, + input [DATA_WIDTH-1:0] s_axi_data, input m_axi_ready, output m_axi_valid, - output [C_DATA_WIDTH-1:0] m_axi_data, + output [DATA_WIDTH-1:0] m_axi_data, output m_axi_last, input req_valid, output req_ready, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length ); -parameter C_ID_WIDTH = 3; -parameter C_DATA_WIDTH = 64; -parameter C_DISABLE_WAIT_FOR_ID = 1; -parameter C_BEATS_PER_BURST_WIDTH = 4; -localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH); +parameter ID_WIDTH = 3; +parameter DATA_WIDTH = 64; +parameter DISABLE_WAIT_FOR_ID = 1; +parameter BEATS_PER_BURST_WIDTH = 4; +localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH); `include "inc_id.h" -reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00; -reg [C_BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00; -reg [C_ID_WIDTH-1:0] id = 'h00; -reg [C_ID_WIDTH-1:0] id_next = 'h00; +reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00; +reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00; +reg [ID_WIDTH-1:0] id = 'h00; +reg [ID_WIDTH-1:0] id_next = 'h00; reg pending_burst = 1'b0; reg active = 1'b0; @@ -108,7 +108,7 @@ always @(posedge clk) begin if (enable) begin enabled <= 1'b1; end else begin - if (C_DISABLE_WAIT_FOR_ID == 0) begin + if (DISABLE_WAIT_FOR_ID == 0) begin // We are not allowed to just deassert valid, so wait until the // current beat has been accepted if (~s_axi_valid || m_axi_ready) diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v index b07cfdf13..fd5101324 100644 --- a/library/axi_dmac/dest_axi_mm.v +++ b/library/axi_dmac/dest_axi_mm.v @@ -42,9 +42,9 @@ module dmac_dest_mm_axi ( input req_valid, output req_ready, - input [31:C_BYTES_PER_BEAT_WIDTH] req_address, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - input [C_BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, input enable, output enabled, @@ -57,18 +57,18 @@ module dmac_dest_mm_axi ( output [1:0] response_resp, output response_resp_eot, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, - output [C_ID_WIDTH-1:0] data_id, - output [C_ID_WIDTH-1:0] address_id, + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, input data_eot, input address_eot, input response_eot, input fifo_valid, output fifo_ready, - input [C_DMA_DATA_WIDTH-1:0] fifo_data, + input [DMA_DATA_WIDTH-1:0] fifo_data, // Write address input m_axi_awready, @@ -81,8 +81,8 @@ module dmac_dest_mm_axi ( output [ 3:0] m_axi_awcache, // Write data - output [C_DMA_DATA_WIDTH-1:0] m_axi_wdata, - output [(C_DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, + output [DMA_DATA_WIDTH-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, input m_axi_wready, output m_axi_wvalid, output m_axi_wlast, @@ -93,12 +93,12 @@ module dmac_dest_mm_axi ( output m_axi_bready ); -parameter C_ID_WIDTH = 3; -parameter C_DMA_DATA_WIDTH = 64; -parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8); -parameter C_BEATS_PER_BURST_WIDTH = 4; +parameter ID_WIDTH = 3; +parameter DMA_DATA_WIDTH = 64; +parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8); +parameter BEATS_PER_BURST_WIDTH = 4; -reg [(C_DMA_DATA_WIDTH/8)-1:0] wstrb; +reg [(DMA_DATA_WIDTH/8)-1:0] wstrb; wire address_req_valid; wire address_req_ready; @@ -113,7 +113,7 @@ wire _fifo_ready; assign fifo_ready = _fifo_ready | ~enabled; splitter #( - .C_NUM_M(2) + .NUM_M(2) ) i_req_splitter ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), @@ -130,10 +130,10 @@ splitter #( ); dmac_address_generator #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH), - .C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH), - .C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH) + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH) ) i_addr_gen ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), @@ -164,9 +164,9 @@ dmac_address_generator #( ); dmac_data_mover # ( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_DMA_DATA_WIDTH), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), @@ -197,14 +197,14 @@ begin if (data_eot & m_axi_wlast) begin wstrb <= (1 << (req_last_beat_bytes + 1)) - 1; end else begin - wstrb <= {(C_DMA_DATA_WIDTH/8){1'b1}}; + wstrb <= {(DMA_DATA_WIDTH/8){1'b1}}; end end assign m_axi_wstrb = wstrb; dmac_response_handler #( - .C_ID_WIDTH(C_ID_WIDTH) + .ID_WIDTH(ID_WIDTH) ) i_response_handler ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index b263e5222..a72a24e80 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -46,24 +46,24 @@ module dmac_dest_axi_stream ( output sync_id_ret, output xfer_req, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, - output [C_ID_WIDTH-1:0] data_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, input data_eot, input response_eot, input m_axis_ready, output m_axis_valid, - output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data, + output [S_AXIS_DATA_WIDTH-1:0] m_axis_data, output m_axis_last, output fifo_ready, input fifo_valid, - input [C_S_AXIS_DATA_WIDTH-1:0] fifo_data, + input [S_AXIS_DATA_WIDTH-1:0] fifo_data, input req_valid, output req_ready, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input req_xlast, output response_valid, @@ -72,9 +72,9 @@ module dmac_dest_axi_stream ( output [1:0] response_resp ); -parameter C_ID_WIDTH = 3; -parameter C_S_AXIS_DATA_WIDTH = 64; -parameter C_BEATS_PER_BURST_WIDTH = 4; +parameter ID_WIDTH = 3; +parameter S_AXIS_DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; reg req_xlast_d = 1'b0; @@ -97,10 +97,10 @@ end assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0; dmac_data_mover # ( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH), - .C_DISABLE_WAIT_FOR_ID(0) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .DISABLE_WAIT_FOR_ID(0) ) i_data_mover ( .clk(s_axis_aclk), .resetn(s_axis_aresetn), @@ -128,7 +128,7 @@ dmac_data_mover # ( ); dmac_response_generator # ( - .C_ID_WIDTH(C_ID_WIDTH) + .ID_WIDTH(ID_WIDTH) ) i_response_generator ( .clk(s_axis_aclk), .resetn(s_axis_aresetn), diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index ae8a9e78a..3e5c1d0eb 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -45,14 +45,14 @@ module dmac_dest_fifo_inf ( input sync_id, output sync_id_ret, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, - output [C_ID_WIDTH-1:0] data_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, input data_eot, input response_eot, input en, - output [C_DATA_WIDTH-1:0] dout, + output [DATA_WIDTH-1:0] dout, output valid, output underflow, @@ -60,11 +60,11 @@ module dmac_dest_fifo_inf ( output fifo_ready, input fifo_valid, - input [C_DATA_WIDTH-1:0] fifo_data, + input [DATA_WIDTH-1:0] fifo_data, input req_valid, output req_ready, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, output response_valid, input response_ready, @@ -72,9 +72,9 @@ module dmac_dest_fifo_inf ( output [1:0] response_resp ); -parameter C_ID_WIDTH = 3; -parameter C_DATA_WIDTH = 64; -parameter C_BEATS_PER_BURST_WIDTH = 4; +parameter ID_WIDTH = 3; +parameter DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; assign sync_id_ret = sync_id; wire data_enabled; @@ -100,10 +100,10 @@ assign data_ready = en_d1 & (data_valid | ~enable); assign valid = en_d1 & data_valid & enable; dmac_data_mover # ( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_DATA_WIDTH), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH), - .C_DISABLE_WAIT_FOR_ID(0) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .DISABLE_WAIT_FOR_ID(0) ) i_data_mover ( .clk(clk), .resetn(resetn), @@ -131,7 +131,7 @@ dmac_data_mover # ( ); dmac_response_generator # ( - .C_ID_WIDTH(C_ID_WIDTH) + .ID_WIDTH(ID_WIDTH) ) i_response_generator ( .clk(clk), .resetn(resetn), diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 4a2b68874..a6f7afd93 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -2,9 +2,9 @@ // *************************************************************************** // Copyright 2013(c) Analog Devices, Inc. // Author: Lars-Peter Clausen -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -22,16 +22,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -42,9 +42,9 @@ module dmac_request_arb ( input req_valid, output req_ready, - input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, - input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address, - input [C_DMA_LENGTH_WIDTH-1:0] req_length, + input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_length, input req_xlast, input req_sync_transfer_start, @@ -70,8 +70,8 @@ module dmac_request_arb ( input m_axi_awready, // Write data - output [C_DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, - output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, + output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, input m_axi_wready, output m_axi_wvalid, output m_axi_wlast, @@ -92,7 +92,7 @@ module dmac_request_arb ( output [ 3:0] m_axi_arcache, // Read data and response - input [C_DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, + input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, output m_axi_rready, input m_axi_rvalid, input [ 1:0] m_axi_rresp, @@ -101,7 +101,7 @@ module dmac_request_arb ( input s_axis_aclk, output s_axis_ready, input s_axis_valid, - input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, input [0:0] s_axis_user, output s_axis_xfer_req, @@ -109,14 +109,14 @@ module dmac_request_arb ( input m_axis_aclk, input m_axis_ready, output m_axis_valid, - output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, output m_axis_last, output m_axis_xfer_req, // Input FIFO interface input fifo_wr_clk, input fifo_wr_en, - input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, output fifo_wr_overflow, input fifo_wr_sync, output fifo_wr_xfer_req, @@ -125,69 +125,69 @@ module dmac_request_arb ( input fifo_rd_clk, input fifo_rd_en, output fifo_rd_valid, - output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, output fifo_rd_underflow, output fifo_rd_xfer_req, - output [C_ID_WIDTH-1:0] dbg_dest_request_id, - output [C_ID_WIDTH-1:0] dbg_dest_address_id, - output [C_ID_WIDTH-1:0] dbg_dest_data_id, - output [C_ID_WIDTH-1:0] dbg_dest_response_id, - output [C_ID_WIDTH-1:0] dbg_src_request_id, - output [C_ID_WIDTH-1:0] dbg_src_address_id, - output [C_ID_WIDTH-1:0] dbg_src_data_id, - output [C_ID_WIDTH-1:0] dbg_src_response_id, + output [ID_WIDTH-1:0] dbg_dest_request_id, + output [ID_WIDTH-1:0] dbg_dest_address_id, + output [ID_WIDTH-1:0] dbg_dest_data_id, + output [ID_WIDTH-1:0] dbg_dest_response_id, + output [ID_WIDTH-1:0] dbg_src_request_id, + output [ID_WIDTH-1:0] dbg_src_address_id, + output [ID_WIDTH-1:0] dbg_src_data_id, + output [ID_WIDTH-1:0] dbg_src_response_id, output [7:0] dbg_status ); -parameter C_DMA_DATA_WIDTH_SRC = 64; -parameter C_DMA_DATA_WIDTH_DEST = 64; -parameter C_DMA_LENGTH_WIDTH = 24; +parameter DMA_DATA_WIDTH_SRC = 64; +parameter DMA_DATA_WIDTH_DEST = 64; +parameter DMA_LENGTH_WIDTH = 24; -parameter C_BYTES_PER_BEAT_WIDTH_DEST = $clog2(C_DMA_DATA_WIDTH_DEST/8); -parameter C_BYTES_PER_BEAT_WIDTH_SRC = $clog2(C_DMA_DATA_WIDTH_SRC/8); +parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8); +parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8); -parameter C_DMA_TYPE_DEST = DMA_TYPE_MM_AXI; -parameter C_DMA_TYPE_SRC = DMA_TYPE_FIFO; +parameter DMA_TYPE_DEST = DMA_TYPE_MM_AXI; +parameter DMA_TYPE_SRC = DMA_TYPE_FIFO; -parameter C_CLKS_ASYNC_REQ_SRC = 1; -parameter C_CLKS_ASYNC_SRC_DEST = 1; -parameter C_CLKS_ASYNC_DEST_REQ = 1; +parameter ASYNC_CLK_REQ_SRC = 1; +parameter ASYNC_CLK_SRC_DEST = 1; +parameter ASYNC_CLK_DEST_REQ = 1; -parameter C_AXI_SLICE_DEST = 0; -parameter C_AXI_SLICE_SRC = 0; +parameter AXI_SLICE_DEST = 0; +parameter AXI_SLICE_SRC = 0; -parameter C_MAX_BYTES_PER_BURST = 128; -parameter C_FIFO_SIZE = 4; +parameter MAX_BYTES_PER_BURST = 128; +parameter FIFO_SIZE = 4; -parameter C_ID_WIDTH = $clog2(C_FIFO_SIZE * 2); +parameter ID_WIDTH = $clog2(FIFO_SIZE*2); localparam DMA_TYPE_MM_AXI = 0; localparam DMA_TYPE_STREAM_AXI = 1; localparam DMA_TYPE_FIFO = 2; -localparam DMA_ADDR_WIDTH_DEST = 32 - C_BYTES_PER_BEAT_WIDTH_DEST; -localparam DMA_ADDR_WIDTH_SRC = 32 - C_BYTES_PER_BEAT_WIDTH_SRC; +localparam DMA_ADDRESS_WIDTH_DEST = 32 - BYTES_PER_BEAT_WIDTH_DEST; +localparam DMA_ADDRESS_WIDTH_SRC = 32 - BYTES_PER_BEAT_WIDTH_SRC; -localparam DMA_DATA_WIDTH = C_DMA_DATA_WIDTH_SRC < C_DMA_DATA_WIDTH_DEST ? - C_DMA_DATA_WIDTH_DEST : C_DMA_DATA_WIDTH_SRC; +localparam DMA_DATA_WIDTH = DMA_DATA_WIDTH_SRC < DMA_DATA_WIDTH_DEST ? + DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC; // Bytes per burst is the same for both dest and src, but bytes per beat may // differ, so beats per burst may also differ -parameter BYTES_PER_BURST_WIDTH = $clog2(C_MAX_BYTES_PER_BURST); -localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_SRC; -localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_DEST; +parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST); +localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC; +localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST; -localparam BURSTS_PER_TRANSFER_WIDTH = C_DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH; +localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH; -reg [0:2**C_ID_WIDTH-1] eot_mem; +reg [0:2**ID_WIDTH-1] eot_mem; wire request_eot; -wire [C_ID_WIDTH-1:0] request_id; -wire [C_ID_WIDTH-1:0] response_id; +wire [ID_WIDTH-1:0] request_id; +wire [ID_WIDTH-1:0] response_id; wire enabled_src; wire enabled_dest; @@ -217,9 +217,9 @@ wire dest_clk; wire dest_resetn; wire dest_req_valid; wire dest_req_ready; -wire [DMA_ADDR_WIDTH_DEST-1:0] dest_req_address; +wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_address; wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length; -wire [C_BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes; +wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes; wire dest_req_xlast; wire dest_response_valid; @@ -228,15 +228,15 @@ wire dest_response_empty; wire [1:0] dest_response_resp; wire dest_response_resp_eot; -wire [C_ID_WIDTH-1:0] dest_request_id; -wire [C_ID_WIDTH-1:0] dest_response_id; +wire [ID_WIDTH-1:0] dest_request_id; +wire [ID_WIDTH-1:0] dest_response_id; wire dest_valid; wire dest_ready; -wire [C_DMA_DATA_WIDTH_DEST-1:0] dest_data; +wire [DMA_DATA_WIDTH_DEST-1:0] dest_data; wire dest_fifo_repacked_valid; wire dest_fifo_repacked_ready; -wire [C_DMA_DATA_WIDTH_DEST-1:0] dest_fifo_repacked_data; +wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_repacked_data; wire dest_fifo_valid; wire dest_fifo_ready; wire [DMA_DATA_WIDTH-1:0] dest_fifo_data; @@ -245,7 +245,7 @@ wire src_clk; wire src_resetn; wire src_req_valid; wire src_req_ready; -wire [DMA_ADDR_WIDTH_SRC-1:0] src_req_address; +wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_address; wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length; wire src_req_sync_transfer_start; @@ -254,15 +254,15 @@ wire src_response_ready; wire src_response_empty; wire [1:0] src_response_resp; -wire [C_ID_WIDTH-1:0] src_request_id; -wire [C_ID_WIDTH-1:0] src_response_id; +wire [ID_WIDTH-1:0] src_request_id; +wire [ID_WIDTH-1:0] src_response_id; wire src_valid; wire src_ready; -wire [C_DMA_DATA_WIDTH_SRC-1:0] src_data; +wire [DMA_DATA_WIDTH_SRC-1:0] src_data; wire src_fifo_valid; wire src_fifo_ready; -wire [C_DMA_DATA_WIDTH_SRC-1:0] src_fifo_data; +wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data; wire src_fifo_repacked_valid; wire src_fifo_repacked_ready; wire [DMA_DATA_WIDTH-1:0] src_fifo_repacked_data; @@ -339,11 +339,11 @@ begin end end -generate if (C_CLKS_ASYNC_REQ_SRC) begin +generate if (ASYNC_CLK_REQ_SRC) begin wire src_async_resetn_source; -if (C_DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin +if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin assign src_async_resetn_source = m_src_axi_aresetn; end else begin assign src_async_resetn_source = req_aresetn; @@ -363,10 +363,10 @@ end else begin assign src_resetn = req_aresetn; end endgenerate -generate if (C_CLKS_ASYNC_DEST_REQ) begin +generate if (ASYNC_CLK_DEST_REQ) begin wire dest_async_resetn_source; -if (C_DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin +if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin assign dest_async_resetn_source = m_dest_axi_aresetn; end else begin assign dest_async_resetn_source = req_aresetn; @@ -386,12 +386,12 @@ end else begin assign dest_resetn = req_aresetn; end endgenerate -generate if (C_DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin +generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin assign dest_clk = m_dest_axi_aclk; -wire [C_ID_WIDTH-1:0] dest_data_id; -wire [C_ID_WIDTH-1:0] dest_address_id; +wire [ID_WIDTH-1:0] dest_data_id; +wire [ID_WIDTH-1:0] dest_address_id; wire dest_address_eot = eot_mem[dest_address_id]; wire dest_data_eot = eot_mem[dest_data_id]; wire dest_response_eot = eot_mem[dest_response_id]; @@ -400,10 +400,10 @@ assign dbg_dest_address_id = dest_address_id; assign dbg_dest_data_id = dest_data_id; dmac_dest_mm_axi #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST), - .C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST), - .C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_DEST) + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST) ) i_dest_dma_mm ( .m_axi_aclk(m_dest_axi_aclk), .m_axi_aresetn(dest_resetn), @@ -477,11 +477,11 @@ assign m_axi_bready = 1'b0; end -if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin +if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin assign dest_clk = m_axis_aclk; -wire [C_ID_WIDTH-1:0] data_id; +wire [ID_WIDTH-1:0] data_id; wire data_eot = eot_mem[data_id]; wire response_eot = eot_mem[dest_response_id]; @@ -490,9 +490,9 @@ assign dbg_dest_address_id = 'h00; assign dbg_dest_data_id = data_id; dmac_dest_axi_stream #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_S_AXIS_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST), - .C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) ) i_dest_dma_stream ( .s_axis_aclk(m_axis_aclk), .s_axis_aresetn(dest_resetn), @@ -535,13 +535,13 @@ end else begin assign m_axis_valid = 1'b0; assign m_axis_data = 'h00; -end +end -if (C_DMA_TYPE_DEST == DMA_TYPE_FIFO) begin +if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin assign dest_clk = fifo_rd_clk; -wire [C_ID_WIDTH-1:0] data_id; +wire [ID_WIDTH-1:0] data_id; wire data_eot = eot_mem[data_id]; wire response_eot = eot_mem[dest_response_id]; @@ -550,9 +550,9 @@ assign dbg_dest_address_id = 'h00; assign dbg_dest_data_id = data_id; dmac_dest_fifo_inf #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST), - .C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) ) i_dest_dma_fifo ( .clk(fifo_rd_clk), .resetn(dest_resetn), @@ -597,12 +597,12 @@ assign fifo_rd_underflow = 1'b0; end endgenerate -generate if (C_DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin +generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin assign src_clk = m_src_axi_aclk; -wire [C_ID_WIDTH-1:0] src_data_id; -wire [C_ID_WIDTH-1:0] src_address_id; +wire [ID_WIDTH-1:0] src_data_id; +wire [ID_WIDTH-1:0] src_address_id; wire src_address_eot = eot_mem[src_address_id]; wire src_data_eot = eot_mem[src_data_id]; @@ -610,10 +610,10 @@ assign dbg_src_address_id = src_address_id; assign dbg_src_data_id = src_data_id; dmac_src_mm_axi #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC), - .C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC), - .C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_SRC) + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC) ) i_src_dma_mm ( .m_axi_aclk(m_src_axi_aclk), .m_axi_aresetn(src_resetn), @@ -671,9 +671,9 @@ assign m_axi_arcache = 'h00; assign m_axi_arprot = 'h00; assign m_axi_rready = 1'b0; -end +end -if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin +if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin assign src_clk = s_axis_aclk; @@ -687,9 +687,9 @@ assign src_response_valid = 1'b0; assign src_response_resp = 2'b0; dmac_src_axi_stream #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_S_AXIS_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC), - .C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) ) i_src_dma_stream ( .s_axis_aclk(s_axis_aclk), .s_axis_aresetn(src_resetn), @@ -726,7 +726,7 @@ assign s_axis_ready = 1'b0; end -if (C_DMA_TYPE_SRC == DMA_TYPE_FIFO) begin +if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin assign src_clk = fifo_wr_clk; @@ -740,9 +740,9 @@ assign src_response_valid = 1'b0; assign src_response_resp = 2'b0; dmac_src_fifo_inf #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC), - .C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) ) i_src_dma_fifo ( .clk(fifo_wr_clk), .resetn(src_resetn), @@ -781,8 +781,8 @@ assign fifo_wr_xfer_req = 1'b0; end endgenerate sync_bits #( - .NUM_BITS(C_ID_WIDTH), - .CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC) + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_sync_src_request_id ( .out_clk(src_clk), .out_resetn(src_resetn), @@ -791,8 +791,8 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(C_ID_WIDTH), - .CLK_ASYNC(C_CLKS_ASYNC_SRC_DEST) + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) ) i_sync_dest_request_id ( .out_clk(dest_clk), .out_resetn(dest_resetn), @@ -801,8 +801,8 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(C_ID_WIDTH), - .CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ) + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_sync_req_response_id ( .out_clk(req_aclk), .out_resetn(req_aresetn), @@ -811,9 +811,9 @@ sync_bits #( ); axi_register_slice #( - .DATA_WIDTH(C_DMA_DATA_WIDTH_SRC), - .FORWARD_REGISTERED(C_AXI_SLICE_SRC), - .BACKWARD_REGISTERED(C_AXI_SLICE_SRC) + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .FORWARD_REGISTERED(AXI_SLICE_SRC), + .BACKWARD_REGISTERED(AXI_SLICE_SRC) ) i_src_slice ( .clk(src_clk), .resetn(src_resetn), @@ -826,8 +826,8 @@ axi_register_slice #( ); util_axis_resize #( - .C_S_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC), - .C_M_DATA_WIDTH(DMA_DATA_WIDTH) + .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .MASTER_DATA_WIDTH(DMA_DATA_WIDTH) ) i_src_repack ( .clk(src_clk), .resetn(src_resetn & src_enable), @@ -840,9 +840,9 @@ util_axis_resize #( ); util_axis_fifo #( - .C_DATA_WIDTH(DMA_DATA_WIDTH), - .C_ADDRESS_WIDTH($clog2(C_MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * C_FIFO_SIZE)), - .C_CLKS_ASYNC(C_CLKS_ASYNC_SRC_DEST) + .DATA_WIDTH(DMA_DATA_WIDTH), + .ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) ) i_fifo ( .s_axis_aclk(src_clk), .s_axis_aresetn(src_resetn), @@ -859,8 +859,8 @@ util_axis_fifo #( ); util_axis_resize #( - .C_S_DATA_WIDTH(DMA_DATA_WIDTH), - .C_M_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST) + .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH), + .MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST) ) i_dest_repack ( .clk(dest_clk), .resetn(dest_resetn & dest_enable), @@ -874,11 +874,11 @@ util_axis_resize #( wire _dest_valid; wire _dest_ready; -wire [C_DMA_DATA_WIDTH_DEST-1:0] _dest_data; +wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data; axi_register_slice #( - .DATA_WIDTH(C_DMA_DATA_WIDTH_DEST), - .FORWARD_REGISTERED(C_AXI_SLICE_DEST) + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .FORWARD_REGISTERED(AXI_SLICE_DEST) ) i_dest_slice2 ( .clk(dest_clk), .resetn(dest_resetn), @@ -891,9 +891,9 @@ axi_register_slice #( ); axi_register_slice #( - .DATA_WIDTH(C_DMA_DATA_WIDTH_DEST), - .FORWARD_REGISTERED(C_AXI_SLICE_DEST), - .BACKWARD_REGISTERED(C_AXI_SLICE_DEST) + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .FORWARD_REGISTERED(AXI_SLICE_DEST), + .BACKWARD_REGISTERED(AXI_SLICE_DEST) ) i_dest_slice ( .clk(dest_clk), .resetn(dest_resetn), @@ -926,7 +926,7 @@ end assign req_ready = _req_ready & _req_valid & enable; splitter #( - .C_NUM_M(3) + .NUM_M(3) ) i_req_splitter ( .clk(req_aclk), .resetn(req_aresetn), @@ -945,9 +945,9 @@ splitter #( ); util_axis_fifo #( - .C_DATA_WIDTH(DMA_ADDR_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + C_BYTES_PER_BEAT_WIDTH_DEST + 1), - .C_ADDRESS_WIDTH(0), - .C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ) + .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_dest_req_fifo ( .s_axis_aclk(req_aclk), .s_axis_aresetn(req_aresetn), @@ -956,8 +956,8 @@ util_axis_fifo #( .s_axis_empty(req_dest_empty), .s_axis_data({ req_dest_address, - req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST], - req_length[C_BYTES_PER_BEAT_WIDTH_DEST-1:0], + req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST], + req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0], req_xlast }), .m_axis_aclk(dest_clk), @@ -973,9 +973,9 @@ util_axis_fifo #( ); util_axis_fifo #( - .C_DATA_WIDTH(DMA_ADDR_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1), - .C_ADDRESS_WIDTH(0), - .C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC) + .DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_src_req_fifo ( .s_axis_aclk(req_aclk), .s_axis_aresetn(req_aresetn), @@ -984,7 +984,7 @@ util_axis_fifo #( .s_axis_empty(req_src_empty), .s_axis_data({ req_src_address, - req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC], + req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC], req_sync_transfer_start }), .m_axis_aclk(src_clk), @@ -999,9 +999,9 @@ util_axis_fifo #( ); util_axis_fifo #( - .C_DATA_WIDTH(3), - .C_ADDRESS_WIDTH(0), - .C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ) + .DATA_WIDTH(3), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_dest_response_fifo ( .s_axis_aclk(dest_clk), .s_axis_aresetn(dest_resetn), @@ -1018,9 +1018,9 @@ util_axis_fifo #( /* Unused for now util_axis_fifo #( - .C_DATA_WIDTH(2), - .C_ADDRESS_WIDTH(0), - .C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC) + .DATA_WIDTH(2), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_src_response_fifo ( .s_axis_aclk(src_clk), .s_axis_aresetn(src_resetn), @@ -1038,8 +1038,8 @@ assign src_response_empty = 1'b1; assign src_response_ready = 1'b1; dmac_request_generator #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) + .ID_WIDTH(ID_WIDTH), + .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) ) i_req_gen ( .req_aclk(req_aclk), .req_aresetn(req_aresetn), @@ -1049,7 +1049,7 @@ dmac_request_generator #( .req_valid(req_gen_valid), .req_ready(req_gen_ready), - .req_burst_count(req_length[C_DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), + .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), .enable(do_enable), .pause(pause), @@ -1058,8 +1058,8 @@ dmac_request_generator #( ); sync_bits #( - .NUM_BITS(3), - .CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ) + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_sync_control_dest ( .out_clk(dest_clk), .out_resetn(dest_resetn), @@ -1068,8 +1068,8 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(2), - .CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ) + .NUM_OF_BITS(2), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_sync_status_dest ( .out_clk(req_aclk), .out_resetn(req_aresetn), @@ -1078,8 +1078,8 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(3), - .CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC) + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_sync_control_src ( .out_clk(src_clk), .out_resetn(src_resetn), @@ -1088,8 +1088,8 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(3), - .CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC) + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_sync_status_src ( .out_clk(req_aclk), .out_resetn(req_aresetn), diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index e02232891..7a6df253d 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -40,12 +40,12 @@ module dmac_request_generator ( input req_aclk, input req_aresetn, - output [C_ID_WIDTH-1:0] request_id, - input [C_ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] request_id, + input [ID_WIDTH-1:0] response_id, input req_valid, output reg req_ready, - input [C_BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count, + input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count, input enable, input pause, @@ -53,8 +53,8 @@ module dmac_request_generator ( output eot ); -parameter C_ID_WIDTH = 3; -parameter C_BURSTS_PER_TRANSFER_WIDTH = 17; +parameter ID_WIDTH = 3; +parameter BURSTS_PER_TRANSFER_WIDTH = 17; `include "inc_id.h" @@ -65,9 +65,9 @@ parameter C_BURSTS_PER_TRANSFER_WIDTH = 17; * care that only the requested ammount of bytes is transfered. */ -reg [C_BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00; -reg [C_ID_WIDTH-1:0] id; -wire [C_ID_WIDTH-1:0] id_next = inc_id(id); +reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00; +reg [ID_WIDTH-1:0] id; +wire [ID_WIDTH-1:0] id_next = inc_id(id); assign eot = burst_count == 'h00; assign request_id = id; diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v index 0e84989e4..1ed4aae02 100644 --- a/library/axi_dmac/response_generator.v +++ b/library/axi_dmac/response_generator.v @@ -43,8 +43,8 @@ module dmac_response_generator ( input enable, output reg enabled, - input [C_ID_WIDTH-1:0] request_id, - output reg [C_ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output reg [ID_WIDTH-1:0] response_id, input sync_id, input eot, @@ -55,7 +55,7 @@ module dmac_response_generator ( output [1:0] resp_resp ); -parameter C_ID_WIDTH = 3; +parameter ID_WIDTH = 3; `include "inc_id.h" `include "resp.h" diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v index 816a33f49..3c62915f6 100644 --- a/library/axi_dmac/response_handler.v +++ b/library/axi_dmac/response_handler.v @@ -44,8 +44,8 @@ module dmac_response_handler ( output bready, input [1:0] bresp, - output reg [C_ID_WIDTH-1:0] id, - input [C_ID_WIDTH-1:0] request_id, + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, input sync_id, input enable, @@ -59,7 +59,7 @@ module dmac_response_handler ( output [1:0] resp_resp ); -parameter C_ID_WIDTH = 3; +parameter ID_WIDTH = 3; `include "resp.h" `include "inc_id.h" diff --git a/library/axi_dmac/splitter.v b/library/axi_dmac/splitter.v index 2487d43ea..3d262c54e 100644 --- a/library/axi_dmac/splitter.v +++ b/library/axi_dmac/splitter.v @@ -43,24 +43,24 @@ module splitter ( input s_valid, output s_ready, - output [C_NUM_M-1:0] m_valid, - input [C_NUM_M-1:0] m_ready + output [NUM_M-1:0] m_valid, + input [NUM_M-1:0] m_ready ); -parameter C_NUM_M = 2; +parameter NUM_M = 2; -reg [C_NUM_M-1:0] acked; +reg [NUM_M-1:0] acked; assign s_ready = &(m_ready | acked); -assign m_valid = s_valid ? ~acked : {C_NUM_M{1'b0}}; +assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}}; always @(posedge clk) begin if (resetn == 1'b0) begin - acked <= {C_NUM_M{1'b0}}; + acked <= {NUM_M{1'b0}}; end else begin if (s_valid & s_ready) - acked <= {C_NUM_M{1'b0}}; + acked <= {NUM_M{1'b0}}; else acked <= acked | (m_ready & m_valid); end diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v index c35641528..60121b559 100644 --- a/library/axi_dmac/src_axi_mm.v +++ b/library/axi_dmac/src_axi_mm.v @@ -42,8 +42,8 @@ module dmac_src_mm_axi ( input req_valid, output req_ready, - input [31:C_BYTES_PER_BEAT_WIDTH] req_address, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input enable, output enabled, @@ -55,17 +55,17 @@ module dmac_src_mm_axi ( input response_ready, output [1:0] response_resp, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, - output [C_ID_WIDTH-1:0] data_id, - output [C_ID_WIDTH-1:0] address_id, + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, input data_eot, input address_eot, output fifo_valid, input fifo_ready, - output [C_DMA_DATA_WIDTH-1:0] fifo_data, + output [DMA_DATA_WIDTH-1:0] fifo_data, // Read address input m_axi_arready, @@ -78,16 +78,16 @@ module dmac_src_mm_axi ( output [ 3:0] m_axi_arcache, // Read data and response - input [C_DMA_DATA_WIDTH-1:0] m_axi_rdata, + input [DMA_DATA_WIDTH-1:0] m_axi_rdata, output m_axi_rready, input m_axi_rvalid, input [ 1:0] m_axi_rresp ); -parameter C_ID_WIDTH = 3; -parameter C_DMA_DATA_WIDTH = 64; -parameter C_BYTES_PER_BEAT_WIDTH = 3; -parameter C_BEATS_PER_BURST_WIDTH = 4; +parameter ID_WIDTH = 3; +parameter DMA_DATA_WIDTH = 64; +parameter BYTES_PER_BEAT_WIDTH = 3; +parameter BEATS_PER_BURST_WIDTH = 4; `include "resp.h" @@ -105,7 +105,7 @@ assign response_valid = 1'b0; assign response_resp = RESP_OKAY; splitter #( - .C_NUM_M(2) + .NUM_M(2) ) i_req_splitter ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), @@ -122,10 +122,10 @@ splitter #( ); dmac_address_generator #( - .C_ID_WIDTH(C_ID_WIDTH), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH), - .C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH), - .C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH) + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH) ) i_addr_gen ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), @@ -156,9 +156,9 @@ dmac_address_generator #( ); dmac_data_mover # ( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_DMA_DATA_WIDTH), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( .clk(m_axi_aclk), .resetn(m_axi_aresetn), diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v index 21bbfebed..4d281f7e1 100644 --- a/library/axi_dmac/src_axi_stream.v +++ b/library/axi_dmac/src_axi_stream.v @@ -45,30 +45,30 @@ module dmac_src_axi_stream ( input sync_id, output sync_id_ret, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, input eot, output s_axis_ready, input s_axis_valid, - input [C_S_AXIS_DATA_WIDTH-1:0] s_axis_data, + input [S_AXIS_DATA_WIDTH-1:0] s_axis_data, input [0:0] s_axis_user, output s_axis_xfer_req, input fifo_ready, output fifo_valid, - output [C_S_AXIS_DATA_WIDTH-1:0] fifo_data, + output [S_AXIS_DATA_WIDTH-1:0] fifo_data, input req_valid, output req_ready, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input req_sync_transfer_start ); -parameter C_ID_WIDTH = 3; -parameter C_S_AXIS_DATA_WIDTH = 64; -parameter C_LENGTH_WIDTH = 24; -parameter C_BEATS_PER_BURST_WIDTH = 4; +parameter ID_WIDTH = 3; +parameter S_AXIS_DATA_WIDTH = 64; +parameter LENGTH_WIDTH = 24; +parameter BEATS_PER_BURST_WIDTH = 4; reg needs_sync = 1'b0; wire sync = s_axis_user[0]; @@ -90,10 +90,10 @@ begin end dmac_data_mover # ( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH), - .C_DISABLE_WAIT_FOR_ID(0), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( .clk(s_axis_aclk), .resetn(s_axis_aresetn), diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index 449e064a0..bb28ce421 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -45,29 +45,29 @@ module dmac_src_fifo_inf ( input sync_id, output sync_id_ret, - input [C_ID_WIDTH-1:0] request_id, - output [C_ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, input eot, input en, - input [C_DATA_WIDTH-1:0] din, + input [DATA_WIDTH-1:0] din, output reg overflow, input sync, output xfer_req, input fifo_ready, output fifo_valid, - output [C_DATA_WIDTH-1:0] fifo_data, + output [DATA_WIDTH-1:0] fifo_data, input req_valid, output req_ready, - input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input req_sync_transfer_start ); -parameter C_ID_WIDTH = 3; -parameter C_DATA_WIDTH = 64; -parameter C_BEATS_PER_BURST_WIDTH = 4; +parameter ID_WIDTH = 3; +parameter DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; wire ready; @@ -104,10 +104,10 @@ end assign sync_id_ret = sync_id; dmac_data_mover # ( - .C_ID_WIDTH(C_ID_WIDTH), - .C_DATA_WIDTH(C_DATA_WIDTH), - .C_DISABLE_WAIT_FOR_ID(0), - .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( .clk(clk), .resetn(resetn), diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v index d0922916d..7e747eb04 100644 --- a/library/axi_generic_adc/axi_generic_adc.v +++ b/library/axi_generic_adc/axi_generic_adc.v @@ -1,6 +1,6 @@ module axi_generic_adc ( input adc_clk, - output [NUM_CHANNELS-1:0] adc_enable, + output [NUM_OF_CHANNELS-1:0] adc_enable, input adc_dovf, input s_axi_aclk, @@ -24,8 +24,8 @@ module axi_generic_adc ( input s_axi_rready ); -parameter NUM_CHANNELS = 2; -parameter PCORE_ID = 0; +parameter NUM_OF_CHANNELS = 2; +parameter ID = 0; reg [31:0] up_rdata = 'd0; reg up_rack = 'd0; @@ -43,9 +43,9 @@ wire up_sel_s; wire up_wr_s; wire [13:0] up_addr_s; wire [31:0] up_wdata_s; -wire [31:0] up_rdata_s[0:NUM_CHANNELS]; -wire up_rack_s[0:NUM_CHANNELS]; -wire up_wack_s[0:NUM_CHANNELS]; +wire [31:0] up_rdata_s[0:NUM_OF_CHANNELS]; +wire up_rack_s[0:NUM_OF_CHANNELS]; +wire up_wack_s[0:NUM_OF_CHANNELS]; reg [31:0] up_rdata_r; reg up_rack_r; @@ -60,7 +60,7 @@ begin up_rdata_r = 'h00; up_rack_r = 'h00; up_wack_r = 'h00; - for (j = 0; j <= NUM_CHANNELS; j=j+1) begin + for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin up_rack_r = up_rack_r | up_rack_s[j]; up_wack_r = up_wack_r | up_wack_s[j]; up_rdata_r = up_rdata_r | up_rdata_s[j]; @@ -79,7 +79,7 @@ always @(negedge up_rstn or posedge up_clk) begin end end -up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( +up_adc_common #(.ID(ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -110,11 +110,11 @@ up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( .up_wreq (up_wreq_s), .up_waddr (up_waddr_s), .up_wdata (up_wdata_s), - .up_wack (up_wack_s[NUM_CHANNELS]), + .up_wack (up_wack_s[NUM_OF_CHANNELS]), .up_rreq (up_rreq_s), .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[NUM_CHANNELS]), - .up_rack (up_rack_s[NUM_CHANNELS])); + .up_rdata (up_rdata_s[NUM_OF_CHANNELS]), + .up_rack (up_rack_s[NUM_OF_CHANNELS])); // up bus interface @@ -150,8 +150,8 @@ up_axi i_up_axi ( generate genvar i; -for (i = 0; i < NUM_CHANNELS; i=i+1) begin - up_adc_channel #(.PCORE_ADC_CHID(i)) i_up_adc_channel ( +for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin + up_adc_channel #(.ADC_CHANNEL_ID(i)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable[i]), diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v index 75139b38b..afc20774e 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx.v @@ -77,7 +77,7 @@ module axi_hdmi_rx ( // parameters - parameter PCORE_ID = 0; + parameter ID = 0; // hdmi interface diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v index f4484b35d..c1df3ab67 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v @@ -321,7 +321,7 @@ module axi_hdmi_rx_core ( // super sampling, 422 to 444 - ad_ss_422to444 #(.Cr_Cb_N(0), .DELAY_DATA_WIDTH(2)) i_ss ( + ad_ss_422to444 #(.CR_CB_N(0), .DELAY_DATA_WIDTH(2)) i_ss ( .clk (hdmi_clk), .s422_de (hdmi_de_422), .s422_sync ({hdmi_sof_422, hdmi_de_422}), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index eeb0d71cc..b477de4c5 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -101,10 +101,10 @@ module axi_hdmi_tx ( // parameters - parameter PCORE_ID = 0; - parameter PCORE_Cr_Cb_N = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_EMBEDDED_SYNC = 0; + parameter ID = 0; + parameter CR_CB_N = 0; + parameter DEVICE_TYPE = 0; + parameter EMBEDDED_SYNC = 0; localparam XILINX_7SERIES = 0; localparam XILINX_ULTRASCALE = 1; @@ -326,8 +326,8 @@ module axi_hdmi_tx ( // hdmi interface axi_hdmi_tx_core #( - .Cr_Cb_N(PCORE_Cr_Cb_N), - .EMBEDDED_SYNC(PCORE_EMBEDDED_SYNC)) + .CR_CB_N(CR_CB_N), + .EMBEDDED_SYNC(EMBEDDED_SYNC)) i_tx_core ( .hdmi_clk (hdmi_clk), .hdmi_rst (hdmi_rst), @@ -373,7 +373,7 @@ module axi_hdmi_tx ( // hdmi output clock generate - if (PCORE_DEVICE_TYPE == XILINX_ULTRASCALE) begin + if (DEVICE_TYPE == XILINX_ULTRASCALE) begin ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr ( .SR (1'b0), .D1 (1'b1), @@ -381,7 +381,7 @@ module axi_hdmi_tx ( .C (hdmi_clk), .Q (hdmi_out_clk)); end - if (PCORE_DEVICE_TYPE == ALTERA_5SERIES) begin + if (DEVICE_TYPE == ALTERA_5SERIES) begin altddio_out #(.WIDTH(1)) i_clk_oddr ( .aclr (1'b0), .aset (1'b0), @@ -395,7 +395,7 @@ module axi_hdmi_tx ( .oe_out (), .dataout (hdmi_out_clk)); end - if (PCORE_DEVICE_TYPE == XILINX_7SERIES) begin + if (DEVICE_TYPE == XILINX_7SERIES) begin ODDR #(.INIT(1'b0)) i_clk_oddr ( .R (1'b0), .S (1'b0), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_alt.v b/library/axi_hdmi_tx/axi_hdmi_tx_alt.v index b41a74ea1..6968e00e8 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_alt.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_alt.v @@ -118,11 +118,11 @@ module axi_hdmi_tx_alt ( s_axi_rlast, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_AXI_ID_WIDTH = 3; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_Cr_Cb_N = 0; - parameter PCORE_EMBEDDED_SYNC = 0; + parameter ID = 0; + parameter AXI_ID_WIDTH = 3; + parameter DEVICE_TYPE = 0; + parameter CR_CB_N = 0; + parameter EMBEDDED_SYNC = 0; // hdmi interface @@ -167,7 +167,7 @@ module axi_hdmi_tx_alt ( input s_axi_aresetn; input s_axi_awvalid; input [13:0] s_axi_awaddr; - input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid; + input [(AXI_ID_WIDTH-1):0] s_axi_awid; input [ 7:0] s_axi_awlen; input [ 2:0] s_axi_awsize; input [ 1:0] s_axi_awburst; @@ -182,11 +182,11 @@ module axi_hdmi_tx_alt ( output s_axi_wready; output s_axi_bvalid; output [ 1:0] s_axi_bresp; - output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid; + output [(AXI_ID_WIDTH-1):0] s_axi_bid; input s_axi_bready; input s_axi_arvalid; input [13:0] s_axi_araddr; - input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid; + input [(AXI_ID_WIDTH-1):0] s_axi_arid; input [ 7:0] s_axi_arlen; input [ 2:0] s_axi_arsize; input [ 1:0] s_axi_arburst; @@ -197,7 +197,7 @@ module axi_hdmi_tx_alt ( output s_axi_rvalid; output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; - output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid; + output [(AXI_ID_WIDTH-1):0] s_axi_rid; output s_axi_rlast; input s_axi_rready; @@ -214,10 +214,10 @@ module axi_hdmi_tx_alt ( // hdmi tx lite version axi_hdmi_tx #( - .PCORE_ID (PCORE_ID), - .PCORE_Cr_Cb_N (PCORE_Cr_Cb_N), - .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), - .PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC)) + .ID (ID), + .CR_CB_N (CR_CB_N), + .DEVICE_TYPE (DEVICE_TYPE), + .EMBEDDED_SYNC (EMBEDDED_SYNC)) i_hdmi_tx ( .hdmi_clk (hdmi_clk), .hdmi_out_clk (hdmi_out_clk), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index a2af6275b..3831a821e 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -101,7 +101,7 @@ module axi_hdmi_tx_core ( // parameters - parameter Cr_Cb_N = 0; + parameter CR_CB_N = 0; parameter EMBEDDED_SYNC = 0; // hdmi interface @@ -539,7 +539,7 @@ module axi_hdmi_tx_core ( // data memory - ad_mem #(.DATA_WIDTH(48), .ADDR_WIDTH(9)) i_mem ( + ad_mem #(.DATA_WIDTH(48), .ADDRESS_WIDTH(9)) i_mem ( .clka (vdma_clk), .wea (vdma_wr), .addra (vdma_waddr), @@ -567,7 +567,7 @@ module axi_hdmi_tx_core ( // sub sampling, 444 to 422 - ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .Cr_Cb_N(Cr_Cb_N)) i_ss_444to422 ( + ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 ( .clk (hdmi_clk), .s444_de (hdmi_24_data_e), .s444_sync ({hdmi_24_hsync, diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl index f860233ea..34296c5ca 100755 --- a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl +++ b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl @@ -33,40 +33,40 @@ add_fileset_file axi_hdmi_tx_alt.v VERILOG PATH axi_hdmi_tx_alt.v TOP_LEVEL_F # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true -add_parameter PCORE_DEVICE_TYPE INTEGER 0 -set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 16 -set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE -set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER -set_parameter_property PCORE_DEVICE_TYPE UNITS None -set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 16 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true -add_parameter PCORE_AXI_ID_WIDTH INTEGER 0 -set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3 -set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH -set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER -set_parameter_property PCORE_AXI_ID_WIDTH UNITS None -set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true +add_parameter AXI_ID_WIDTH INTEGER 0 +set_parameter_property AXI_ID_WIDTH DEFAULT_VALUE 3 +set_parameter_property AXI_ID_WIDTH DISPLAY_NAME AXI_ID_WIDTH +set_parameter_property AXI_ID_WIDTH TYPE INTEGER +set_parameter_property AXI_ID_WIDTH UNITS None +set_parameter_property AXI_ID_WIDTH HDL_PARAMETER true -add_parameter PCORE_Cr_Cb_N INTEGER 0 -set_parameter_property PCORE_Cr_Cb_N DEFAULT_VALUE 0 -set_parameter_property PCORE_Cr_Cb_N DISPLAY_NAME PCORE_Cr_Cb_N -set_parameter_property PCORE_Cr_Cb_N TYPE INTEGER -set_parameter_property PCORE_Cr_Cb_N UNITS None -set_parameter_property PCORE_Cr_Cb_N HDL_PARAMETER true +add_parameter CR_CB_N INTEGER 0 +set_parameter_property CR_CB_N DEFAULT_VALUE 0 +set_parameter_property CR_CB_N DISPLAY_NAME CR_CB_N +set_parameter_property CR_CB_N TYPE INTEGER +set_parameter_property CR_CB_N UNITS None +set_parameter_property CR_CB_N HDL_PARAMETER true -add_parameter PCORE_EMBEDDED_SYNC INTEGER 0 -set_parameter_property PCORE_EMBEDDED_SYNC DEFAULT_VALUE 0 -set_parameter_property PCORE_EMBEDDED_SYNC DISPLAY_NAME PCORE_EMBEDDED_SYNC -set_parameter_property PCORE_EMBEDDED_SYNC TYPE INTEGER -set_parameter_property PCORE_EMBEDDED_SYNC UNITS None -set_parameter_property PCORE_EMBEDDED_SYNC HDL_PARAMETER true +add_parameter EMBEDDED_SYNC INTEGER 0 +set_parameter_property EMBEDDED_SYNC DEFAULT_VALUE 0 +set_parameter_property EMBEDDED_SYNC DISPLAY_NAME EMBEDDED_SYNC +set_parameter_property EMBEDDED_SYNC TYPE INTEGER +set_parameter_property EMBEDDED_SYNC UNITS None +set_parameter_property EMBEDDED_SYNC HDL_PARAMETER true # axi4 slave @@ -97,7 +97,7 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1 add_interface_port s_axi s_axi_rresp rresp Output 2 add_interface_port s_axi s_axi_rdata rdata Output 32 add_interface_port s_axi s_axi_rready rready Input 1 -add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH +add_interface_port s_axi s_axi_awid awid Input AXI_ID_WIDTH add_interface_port s_axi s_axi_awlen awlen Input 8 add_interface_port s_axi s_axi_awsize awsize Input 3 add_interface_port s_axi s_axi_awburst awburst Input 2 @@ -105,15 +105,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1 add_interface_port s_axi s_axi_awcache awcache Input 4 add_interface_port s_axi s_axi_awprot awprot Input 3 add_interface_port s_axi s_axi_wlast wlast Input 1 -add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH -add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH +add_interface_port s_axi s_axi_bid bid Output AXI_ID_WIDTH +add_interface_port s_axi s_axi_arid arid Input AXI_ID_WIDTH add_interface_port s_axi s_axi_arlen arlen Input 8 add_interface_port s_axi s_axi_arsize arsize Input 3 add_interface_port s_axi s_axi_arburst arburst Input 2 add_interface_port s_axi s_axi_arlock arlock Input 1 add_interface_port s_axi s_axi_arcache arcache Input 4 add_interface_port s_axi s_axi_arprot arprot Input 3 -add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH +add_interface_port s_axi s_axi_rid rid Output AXI_ID_WIDTH add_interface_port s_axi s_axi_rlast rlast Output 1 # hdmi interface diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 91b9f3dfd..5032725a6 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -41,7 +41,7 @@ module axi_jesd_gt #( parameter integer ID = 0, parameter integer NUM_OF_LANES = 8, - parameter integer GTH_GTX_N = 0, + parameter integer GTH_OR_GTX_N = 0, parameter integer QPLL0_ENABLE = 1, parameter integer QPLL0_REFCLK_DIV = 1, parameter [26:0] QPLL0_CFG = 27'h0680181, @@ -1445,7 +1445,7 @@ module axi_jesd_gt #( for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane_1 ad_gt_channel_1 #( .ID (n), - .GTH_GTX_N (GTH_GTX_N), + .GTH_OR_GTX_N (GTH_OR_GTX_N), .PMA_RSV (PMA_RSV[n]), .CPLL_FBDIV (CPLL_FBDIV[n]), .RX_OUT_DIV (RX_OUT_DIV[n]), @@ -1540,7 +1540,7 @@ module axi_jesd_gt #( ad_gt_common_1 #( .ID (0), - .GTH_GTX_N (GTH_GTX_N), + .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL0_ENABLE (QPLL0_ENABLE), .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV), .QPLL0_CFG (QPLL0_CFG), diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr.v b/library/axi_jesd_xcvr/axi_jesd_xcvr.v index 05cff747b..25758e064 100644 --- a/library/axi_jesd_xcvr/axi_jesd_xcvr.v +++ b/library/axi_jesd_xcvr/axi_jesd_xcvr.v @@ -97,8 +97,8 @@ module axi_jesd_xcvr ( s_axi_rresp, s_axi_rready); - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; + parameter ID = 0; + parameter DEVICE_TYPE = 0; parameter PCORE_NUM_OF_TX_LANES = 4; parameter PCORE_NUM_OF_RX_LANES = 4; @@ -249,8 +249,8 @@ module axi_jesd_xcvr ( // processor up_xcvr #( - .PCORE_ID(PCORE_ID), - .PCORE_DEVICE_TYPE(PCORE_DEVICE_TYPE)) + .ID(ID), + .DEVICE_TYPE(DEVICE_TYPE)) i_up_xcvr ( .rst (rst), .rx_clk (rx_clk), diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl b/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl index 2d00aecf5..167be1cc7 100755 --- a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl +++ b/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl @@ -24,19 +24,19 @@ add_fileset_file axi_jesd_xcvr_constr.sdc SDC PATH axi_jesd_xcvr_constr.sdc # parameters -add_parameter PCORE_ID INTEGER 0 -set_parameter_property PCORE_ID DEFAULT_VALUE 0 -set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID -set_parameter_property PCORE_ID TYPE INTEGER -set_parameter_property PCORE_ID UNITS None -set_parameter_property PCORE_ID HDL_PARAMETER true +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true -add_parameter PCORE_DEVICE_TYPE INTEGER 0 -set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE -set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER -set_parameter_property PCORE_DEVICE_TYPE UNITS None -set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true add_parameter PCORE_NUM_OF_TX_LANES INTEGER 0 set_parameter_property PCORE_NUM_OF_TX_LANES DEFAULT_VALUE 4 diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v index 59358cc52..29ba0fabe 100644 --- a/library/axi_mc_controller/axi_mc_controller.v +++ b/library/axi_mc_controller/axi_mc_controller.v @@ -309,7 +309,7 @@ control_registers control_reg_inst( .calibrate_adcs_o(), .pwm_open_o(pwm_open_s)); -up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0( +up_adc_channel #(.ADC_CHANNEL_ID(0)) adc_channel0( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c0), @@ -355,7 +355,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0( .up_rdata (rdata_c0_s), .up_rack (rack_c0_s)); -up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1( +up_adc_channel #(.ADC_CHANNEL_ID(1)) adc_channel1( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c1), @@ -401,7 +401,7 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1( .up_rdata (rdata_c1_s), .up_rack (rack_c1_s)); -up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2( +up_adc_channel #(.ADC_CHANNEL_ID(2)) adc_channel2( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c2), @@ -447,7 +447,7 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2( .up_rdata (rdata_c2_s), .up_rack (rack_c2_s)); -up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3( +up_adc_channel #(.ADC_CHANNEL_ID(3)) adc_channel3( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c3), @@ -493,7 +493,7 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3( .up_rdata (rdata_c3_s), .up_rack (rack_c3_s)); -up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4( +up_adc_channel #(.ADC_CHANNEL_ID(4)) adc_channel4( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c4), @@ -539,7 +539,7 @@ up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4( .up_rdata (rdata_c4_s), .up_rack (rack_c4_s)); -up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5( +up_adc_channel #(.ADC_CHANNEL_ID(5)) adc_channel5( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c5), @@ -585,7 +585,7 @@ up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5( .up_rdata (rdata_c5_s), .up_rack (rack_c5_s)); -up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6( +up_adc_channel #(.ADC_CHANNEL_ID(6)) adc_channel6( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c6), @@ -631,7 +631,7 @@ up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6( .up_rdata (rdata_c6_s), .up_rack (rack_c6_s)); -up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7( +up_adc_channel #(.ADC_CHANNEL_ID(7)) adc_channel7( .adc_clk(ref_clk), .adc_rst(adc_rst), .adc_enable(adc_enable_c7), diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v index c57336a59..79b75f6e4 100644 --- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v +++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v @@ -197,7 +197,7 @@ ad7401 vbus_if( .data_rd_ready_o(), .adc_mdata_i(adc_vbus_dat_i)); -up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia( +up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel_ia( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_ia), @@ -243,7 +243,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia( .up_rdata (up_rdata_0_s), .up_rack (up_rack_0_s)); -up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib( +up_adc_channel #(.ADC_CHANNEL_ID(1)) i_up_adc_channel_ib( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_ib), @@ -289,7 +289,7 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib( .up_rdata (up_rdata_1_s), .up_rack (up_rack_1_s)); -up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus( +up_adc_channel #(.ADC_CHANNEL_ID(2)) i_up_adc_channel_vbus( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_vbus), @@ -335,7 +335,7 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus( .up_rdata (up_rdata_2_s), .up_rack (up_rack_2_s)); -up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_stub( +up_adc_channel #(.ADC_CHANNEL_ID(3)) i_up_adc_channel_stub( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_stub), diff --git a/library/axi_mc_speed/axi_mc_speed.v b/library/axi_mc_speed/axi_mc_speed.v index 349e24549..133883dfc 100644 --- a/library/axi_mc_speed/axi_mc_speed.v +++ b/library/axi_mc_speed/axi_mc_speed.v @@ -134,7 +134,7 @@ end // HALL sensors debouncers debouncer -#( .DEBOUNCER_LEN(400)) +#( .DEBOUNCER_LENGTH(400)) position_0( .clk_i(ref_clk), .rst_i(adc_rst), @@ -142,7 +142,7 @@ position_0( .sig_o(position_s[0])); debouncer -#( .DEBOUNCER_LEN(400)) +#( .DEBOUNCER_LENGTH(400)) position_1( .clk_i(ref_clk), .rst_i(adc_rst), @@ -150,7 +150,7 @@ position_1( .sig_o(position_s[1])); debouncer -#( .DEBOUNCER_LEN(400)) +#( .DEBOUNCER_LENGTH(400)) position_2( .clk_i(ref_clk), .rst_i(adc_rst), diff --git a/library/axi_mc_speed/debouncer.v b/library/axi_mc_speed/debouncer.v index 72d651277..a3472c0bf 100644 --- a/library/axi_mc_speed/debouncer.v +++ b/library/axi_mc_speed/debouncer.v @@ -60,7 +60,7 @@ module debouncer //----------- Paramters Declarations ------------------------------------------- #( - parameter DEBOUNCER_LEN = 4 + parameter DEBOUNCER_LENGTH = 4 ) //----------- Ports Declarations ----------------------------------------------- ( @@ -72,7 +72,7 @@ module debouncer //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ -reg [DEBOUNCER_LEN-1:0] shift_reg; +reg [DEBOUNCER_LENGTH-1:0] shift_reg; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- @@ -87,12 +87,12 @@ begin end else begin - shift_reg <= {shift_reg[DEBOUNCER_LEN-2:0], sig_i}; - if(shift_reg == {DEBOUNCER_LEN{1'b1}}) + shift_reg <= {shift_reg[DEBOUNCER_LENGTH-2:0], sig_i}; + if(shift_reg == {DEBOUNCER_LENGTH{1'b1}}) begin sig_o <= 1'b1; end - else if(shift_reg == {DEBOUNCER_LEN{1'b0}}) + else if(shift_reg == {DEBOUNCER_LENGTH{1'b0}}) begin sig_o <= 1'b0; end diff --git a/library/common/ad_addsub.v b/library/common/ad_addsub.v index 39b1c6af9..86d5530e5 100644 --- a/library/common/ad_addsub.v +++ b/library/common/ad_addsub.v @@ -53,34 +53,34 @@ module ad_addsub ( // parameters - parameter A_WIDTH = 32; - parameter CONST_VALUE = 32'h1; - parameter ADD_SUB = 0; + parameter A_DATA_WIDTH = 32; + parameter B_DATA_VALUE = 32'h1; + parameter ADD_OR_SUB_N = 0; - localparam ADDER = 0; - localparam SUBSTRACTER = 1; + localparam ADDER = 1; + localparam SUBSTRACTER = 0; // I/O definitions input clk; - input [(A_WIDTH-1):0] A; - input [(A_WIDTH-1):0] Amax; - output [(A_WIDTH-1):0] out; + input [(A_DATA_WIDTH-1):0] A; + input [(A_DATA_WIDTH-1):0] Amax; + output [(A_DATA_WIDTH-1):0] out; input CE; // registers - reg [(A_WIDTH-1):0] out = 'b0; - reg [A_WIDTH:0] out_d = 'b0; - reg [A_WIDTH:0] out_d2 = 'b0; - reg [(A_WIDTH-1):0] A_d = 'b0; - reg [(A_WIDTH-1):0] A_d2 = 'b0; - reg [(A_WIDTH-1):0] Amax_d = 'b0; - reg [(A_WIDTH-1):0] Amax_d2 = 'b0; + reg [(A_DATA_WIDTH-1):0] out = 'b0; + reg [A_DATA_WIDTH:0] out_d = 'b0; + reg [A_DATA_WIDTH:0] out_d2 = 'b0; + reg [(A_DATA_WIDTH-1):0] A_d = 'b0; + reg [(A_DATA_WIDTH-1):0] A_d2 = 'b0; + reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0; + reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0; // constant regs - reg [(A_WIDTH-1):0] B_reg = CONST_VALUE; + reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE; // latch the inputs @@ -94,7 +94,7 @@ module ad_addsub ( // ADDER/SUBSTRACTER always @(posedge clk) begin - if ( ADD_SUB == ADDER ) begin + if ( ADD_OR_SUB_N == ADDER ) begin out_d <= A_d + B_reg; end else begin out_d <= A_d - B_reg; @@ -104,14 +104,14 @@ module ad_addsub ( // Resolve always @(posedge clk) begin - if ( ADD_SUB == ADDER ) begin + if ( ADD_OR_SUB_N == ADDER ) begin if ( out_d > Amax_d2 ) begin out_d2 <= out_d - Amax_d2; end else begin out_d2 <= out_d; end end else begin // SUBSTRACTER - if ( out_d[A_WIDTH] == 1'b1 ) begin + if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin out_d2 <= Amax_d2 + out_d; end else begin out_d2 <= out_d; diff --git a/library/common/ad_axis_dma_rx.v b/library/common/ad_axis_dma_rx.v index e3b43770f..08c40b4e2 100644 --- a/library/common/ad_axis_dma_rx.v +++ b/library/common/ad_axis_dma_rx.v @@ -315,7 +315,7 @@ module ad_axis_dma_rx ( // buffer (mainly for clock domain transfer) - ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem ( + ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem ( .clka (adc_clk), .wea (adc_wr), .addra (adc_waddr), diff --git a/library/common/ad_axis_dma_tx.v b/library/common/ad_axis_dma_tx.v index e69a081d6..d14f32c48 100644 --- a/library/common/ad_axis_dma_tx.v +++ b/library/common/ad_axis_dma_tx.v @@ -266,7 +266,7 @@ module ad_axis_dma_tx ( // memory - ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem ( + ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem ( .clka (dma_clk), .wea (dma_wr), .addra (dma_waddr), diff --git a/library/common/ad_csc_1_mul.v b/library/common/ad_csc_1_mul.v index e92641a26..d656e483f 100644 --- a/library/common/ad_csc_1_mul.v +++ b/library/common/ad_csc_1_mul.v @@ -103,8 +103,8 @@ module ad_csc_1_mul ( MULT_MACRO #( .LATENCY (3), - .WIDTH_A (17), - .WIDTH_B (9)) + .A_DATA_WIDTH (17), + .B_DATA_WIDTH (9)) i_mult_macro ( .CE (1'b1), .RST (1'b0), diff --git a/library/common/ad_gt_channel.v b/library/common/ad_gt_channel.v index 4081eab7a..fb25593b9 100644 --- a/library/common/ad_gt_channel.v +++ b/library/common/ad_gt_channel.v @@ -104,7 +104,7 @@ module ad_gt_channel ( // parameters - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; parameter [31:0] PMA_RSV = 32'h00018480; parameter integer CPLL_FBDIV = 2; parameter integer RX_OUT_DIV = 1; @@ -248,7 +248,7 @@ module ad_gt_channel ( assign tx_out_clk = tx_out_clk_s; end - if (GTH_GTX_N == 0) begin + if (GTH_OR_GTX_N == 0) begin assign rx_sys_clk_sel_s = rx_sys_clk_sel; assign tx_sys_clk_sel_s = tx_sys_clk_sel; @@ -700,7 +700,7 @@ module ad_gt_channel ( .TXQPISENN ()); end - if (GTH_GTX_N == 1) begin + if (GTH_OR_GTX_N == 1) begin assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; diff --git a/library/common/ad_gt_channel_1.v b/library/common/ad_gt_channel_1.v index c20ed9379..28a27287b 100644 --- a/library/common/ad_gt_channel_1.v +++ b/library/common/ad_gt_channel_1.v @@ -146,7 +146,7 @@ module ad_gt_channel_1 ( // parameters parameter integer ID = 0; - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; parameter [31:0] PMA_RSV = 32'h00018480; parameter integer CPLL_FBDIV = 2; parameter integer RX_OUT_DIV = 1; @@ -320,7 +320,7 @@ module ad_gt_channel_1 ( .rx_data (rx_data)); ad_gt_channel #( - .GTH_GTX_N (GTH_GTX_N), + .GTH_OR_GTX_N (GTH_OR_GTX_N), .PMA_RSV (PMA_RSV), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), @@ -380,7 +380,7 @@ module ad_gt_channel_1 ( .up_drp_rxrate (up_drp_rxrate_s)); ad_gt_es #( - .GTH_GTX_N (GTH_GTX_N)) + .GTH_OR_GTX_N (GTH_OR_GTX_N)) i_es ( .lpm_dfe_n (lpm_dfe_n_s), .up_rstn (up_rstn), @@ -421,7 +421,7 @@ module ad_gt_channel_1 ( up_gt_channel #( .ID (ID), - .GTH_GTX_N (GTH_GTX_N)) + .GTH_OR_GTX_N (GTH_OR_GTX_N)) i_up ( .pll_rst (pll_rst), .lpm_dfe_n (lpm_dfe_n_s), diff --git a/library/common/ad_gt_common.v b/library/common/ad_gt_common.v index 23993407d..a01f2afbe 100644 --- a/library/common/ad_gt_common.v +++ b/library/common/ad_gt_common.v @@ -59,7 +59,7 @@ module ad_gt_common ( // parameters - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; parameter integer QPLL_ENABLE = 1; parameter integer QPLL_REFCLK_DIV = 2; parameter [26:0] QPLL_CFG = 27'h06801C1; @@ -96,7 +96,7 @@ module ad_gt_common ( assign up_drp_ready = 1'd0; end - if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 0)) begin + if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin GTXE2_COMMON #( .SIM_RESET_SPEEDUP ("TRUE"), .SIM_QPLLREFCLK_SEL (3'b001), @@ -155,7 +155,7 @@ module ad_gt_common ( .RCALENB (1'd1)); end - if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 1)) begin + if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin GTHE3_COMMON #( .SIM_RESET_SPEEDUP ("TRUE"), .SIM_VERSION (2), diff --git a/library/common/ad_gt_common_1.v b/library/common/ad_gt_common_1.v index c63fcbe00..a4444b20f 100644 --- a/library/common/ad_gt_common_1.v +++ b/library/common/ad_gt_common_1.v @@ -66,7 +66,7 @@ module ad_gt_common_1 ( // parameters parameter integer ID = 0; - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; parameter integer QPLL0_ENABLE = 1; parameter integer QPLL0_REFCLK_DIV = 2; parameter [26:0] QPLL0_CFG = 27'h06801C1; @@ -146,7 +146,7 @@ module ad_gt_common_1 ( // instantiations ad_gt_common #( - .GTH_GTX_N (GTH_GTX_N), + .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_ENABLE (QPLL0_ENABLE), .QPLL_REFCLK_DIV (QPLL0_REFCLK_DIV), .QPLL_CFG (QPLL0_CFG), @@ -167,7 +167,7 @@ module ad_gt_common_1 ( .up_drp_ready (up_drp_qpll0_ready_s)); ad_gt_common #( - .GTH_GTX_N (GTH_GTX_N), + .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_ENABLE (QPLL1_ENABLE), .QPLL_REFCLK_DIV (QPLL1_REFCLK_DIV), .QPLL_CFG (QPLL1_CFG), @@ -188,7 +188,7 @@ module ad_gt_common_1 ( .up_drp_ready (up_drp_qpll1_ready_s)); up_gt #( - .GTH_GTX_N (GTH_GTX_N), + .GTH_OR_GTX_N (GTH_OR_GTX_N), .ID (ID)) i_up ( .up_drp_qpll0_sel (up_drp_qpll0_sel_s), diff --git a/library/common/ad_gt_es.v b/library/common/ad_gt_es.v index 5c8d11621..a8ecc4d09 100644 --- a/library/common/ad_gt_es.v +++ b/library/common/ad_gt_es.v @@ -87,26 +87,26 @@ module ad_gt_es ( // parameters - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; // gt address - localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d - localparam [11:0] ES_DRP_SDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036 - localparam [11:0] ES_DRP_SDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037 - localparam [11:0] ES_DRP_SDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038 - localparam [11:0] ES_DRP_SDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039 - localparam [11:0] ES_DRP_SDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a - localparam [11:0] ES_DRP_QDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031 - localparam [11:0] ES_DRP_QDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032 - localparam [11:0] ES_DRP_QDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033 - localparam [11:0] ES_DRP_QDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034 - localparam [11:0] ES_DRP_QDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035 - localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c - localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b - localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153 - localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152 - localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151 + localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d + localparam [11:0] ES_DRP_SDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036 + localparam [11:0] ES_DRP_SDATA1_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037 + localparam [11:0] ES_DRP_SDATA2_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038 + localparam [11:0] ES_DRP_SDATA3_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039 + localparam [11:0] ES_DRP_SDATA4_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a + localparam [11:0] ES_DRP_QDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031 + localparam [11:0] ES_DRP_QDATA1_ADDR = (GTH_OR_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032 + localparam [11:0] ES_DRP_QDATA2_ADDR = (GTH_OR_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033 + localparam [11:0] ES_DRP_QDATA3_ADDR = (GTH_OR_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034 + localparam [11:0] ES_DRP_QDATA4_ADDR = (GTH_OR_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035 + localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c + localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b + localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153 + localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152 + localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151 // state machine @@ -653,7 +653,7 @@ module ad_gt_es ( up_es_drp_sel <= 1'b1; up_es_drp_wr <= 1'b1; up_es_drp_addr <= ES_DRP_CTRL_ADDR; - if (GTH_GTX_N == 1) begin + if (GTH_OR_GTX_N == 1) begin up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:5], up_es_prescale}; end else begin @@ -730,7 +730,7 @@ module ad_gt_es ( up_es_drp_sel <= 1'b1; up_es_drp_wr <= 1'b1; up_es_drp_addr <= ES_DRP_HOFFSET_ADDR; - if (GTH_GTX_N == 1) begin + if (GTH_OR_GTX_N == 1) begin up_es_drp_wdata <= {up_es_hoffset, up_es_hoffset_rdata[3:0]}; end else begin up_es_drp_wdata <= {up_es_hoffset_rdata[15:12], up_es_hoffset}; @@ -746,7 +746,7 @@ module ad_gt_es ( up_es_drp_sel <= 1'b1; up_es_drp_wr <= 1'b1; up_es_drp_addr <= ES_DRP_VOFFSET_ADDR; - if (GTH_GTX_N == 1) begin + if (GTH_OR_GTX_N == 1) begin up_es_drp_wdata <= {up_es_voffset_rdata[15:11], up_es_voffset_s[7], up_es_ut_s, up_es_voffset_s[6:0], up_es_voffset_range}; end else begin @@ -764,7 +764,7 @@ module ad_gt_es ( up_es_drp_sel <= 1'b1; up_es_drp_wr <= 1'b1; up_es_drp_addr <= ES_DRP_CTRL_ADDR; - if (GTH_GTX_N == 1) begin + if (GTH_OR_GTX_N == 1) begin up_es_drp_wdata <= {6'd1, up_es_ctrl_rdata[9:0]}; end else begin up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd1}; @@ -786,7 +786,7 @@ module ad_gt_es ( up_es_drp_sel <= 1'b1; up_es_drp_wr <= 1'b1; up_es_drp_addr <= ES_DRP_CTRL_ADDR; - if (GTH_GTX_N == 1) begin + if (GTH_OR_GTX_N == 1) begin up_es_drp_wdata <= {6'd0, up_es_ctrl_rdata[9:0]}; end else begin up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd0}; diff --git a/library/common/ad_iqcor.v b/library/common/ad_iqcor.v index f666bcb68..6895104a1 100644 --- a/library/common/ad_iqcor.v +++ b/library/common/ad_iqcor.v @@ -57,7 +57,7 @@ module ad_iqcor ( // select i/q if disabled - parameter IQSEL = 0; + parameter Q_OR_I_N = 0; // data interface @@ -95,8 +95,8 @@ module ad_iqcor ( // swap i & q - assign data_i_s = (IQSEL == 1) ? data_iq : data_in; - assign data_q_s = (IQSEL == 1) ? data_in : data_iq; + assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in; + assign data_q_s = (Q_OR_I_N == 1) ? data_in : data_iq; // scaling functions - i @@ -133,7 +133,7 @@ module ad_iqcor ( valid_out <= p1_valid; if (iqcor_enable == 1'b1) begin data_out <= p1_data_p[29:14]; - end else if (IQSEL == 1) begin + end else if (Q_OR_I_N == 1) begin data_out <= p1_data_q; end else begin data_out <= p1_data_i; diff --git a/library/common/ad_lvds_clk.v b/library/common/ad_lvds_clk.v index 04e4b73c1..e65ea434f 100644 --- a/library/common/ad_lvds_clk.v +++ b/library/common/ad_lvds_clk.v @@ -45,7 +45,7 @@ module ad_lvds_clk ( clk_in_n, clk); - parameter BUFTYPE = 0; + parameter DEVICE_TYPE = 0; localparam SERIES7 = 0; localparam VIRTEX6 = 1; @@ -65,7 +65,7 @@ module ad_lvds_clk ( .O (clk_ibuf_s)); generate - if (BUFTYPE == VIRTEX6) begin + if (DEVICE_TYPE == VIRTEX6) begin BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf ( .CLR (1'b0), .CE (1'b1), diff --git a/library/common/ad_lvds_in.v b/library/common/ad_lvds_in.v index 8608145ac..44cd171ba 100644 --- a/library/common/ad_lvds_in.v +++ b/library/common/ad_lvds_in.v @@ -64,7 +64,7 @@ module ad_lvds_in ( // parameters - parameter BUFTYPE = 0; + parameter DEVICE_TYPE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; localparam SERIES7 = 0; @@ -122,7 +122,7 @@ module ad_lvds_in ( .IB (rx_data_in_n), .O (rx_data_ibuf_s)); - if (BUFTYPE == VIRTEX6) begin + if (DEVICE_TYPE == VIRTEX6) begin (* IODELAY_GROUP = IODELAY_GROUP *) IODELAYE1 #( .CINVCTRL_SEL ("FALSE"), diff --git a/library/common/ad_lvds_out.v b/library/common/ad_lvds_out.v index 3d089eda3..14b380e38 100644 --- a/library/common/ad_lvds_out.v +++ b/library/common/ad_lvds_out.v @@ -64,7 +64,7 @@ module ad_lvds_out ( // parameters - parameter BUFTYPE = 0; + parameter DEVICE_TYPE = 0; parameter IODELAY_ENABLE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; @@ -100,7 +100,7 @@ module ad_lvds_out ( // delay controller generate - if ((IODELAY_ENABLE == 1) && (BUFTYPE == SERIES7) && (IODELAY_CTRL == 1)) begin + if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYCTRL i_delay_ctrl ( .RST (delay_rst), @@ -127,7 +127,7 @@ module ad_lvds_out ( .Q (tx_data_oddr_s)); generate - if ((IODELAY_ENABLE == 1) && (BUFTYPE == SERIES7)) begin + if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin (* IODELAY_GROUP = IODELAY_GROUP *) ODELAYE2 #( .CINVCTRL_SEL ("FALSE"), diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v index b96730467..412e17f8f 100644 --- a/library/common/ad_mem.v +++ b/library/common/ad_mem.v @@ -51,9 +51,9 @@ module ad_mem ( doutb); parameter DATA_WIDTH = 16; - parameter ADDR_WIDTH = 5; + parameter ADDRESS_WIDTH = 5; localparam DW = DATA_WIDTH - 1; - localparam AW = ADDR_WIDTH - 1; + localparam AW = ADDRESS_WIDTH - 1; input clka; input wea; @@ -64,7 +64,7 @@ module ad_mem ( input [AW:0] addrb; output [DW:0] doutb; - reg [DW:0] m_ram[0:((2**ADDR_WIDTH)-1)]; + reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)]; reg [DW:0] doutb; always @(posedge clka) begin diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v index af398584a..7d3564cd1 100644 --- a/library/common/ad_mem_asym.v +++ b/library/common/ad_mem_asym.v @@ -50,33 +50,33 @@ module ad_mem_asym ( addrb, doutb); - parameter ADDR_WIDTH_A = 10; - parameter DATA_WIDTH_A = 256; - parameter ADDR_WIDTH_B = 8; - parameter DATA_WIDTH_B = 64; + parameter A_ADDRESS_WIDTH = 10; + parameter A_DATA_WIDTH = 256; + parameter B_ADDRESS_WIDTH = 8; + parameter B_DATA_WIDTH = 64; - localparam MEM_SIZE_A = 2**ADDR_WIDTH_A; - localparam MEM_SIZE_B = 2**ADDR_WIDTH_B; + localparam MEM_SIZE_A = 2**A_ADDRESS_WIDTH; + localparam MEM_SIZE_B = 2**B_ADDRESS_WIDTH; localparam MEM_SIZE = (MEM_SIZE_A > MEM_SIZE_B) ? MEM_SIZE_A : MEM_SIZE_B; - localparam MEM_RATIO = DATA_WIDTH_A/DATA_WIDTH_B; + localparam MEM_RATIO = A_DATA_WIDTH/B_DATA_WIDTH; // write interface input clka; input wea; - input [ADDR_WIDTH_A-1:0] addra; - input [DATA_WIDTH_A-1:0] dina; + input [A_ADDRESS_WIDTH-1:0] addra; + input [A_DATA_WIDTH-1:0] dina; // read interface input clkb; - input [ADDR_WIDTH_B-1:0] addrb; - output [DATA_WIDTH_B-1:0] doutb; + input [B_ADDRESS_WIDTH-1:0] addrb; + output [B_DATA_WIDTH-1:0] doutb; // internal registers - reg [DATA_WIDTH_B-1:0] m_ram[0:MEM_SIZE-1]; - reg [DATA_WIDTH_B-1:0] doutb; + reg [B_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1]; + reg [B_DATA_WIDTH-1:0] doutb; // write interface @@ -84,8 +84,8 @@ module ad_mem_asym ( if (MEM_RATIO == 2) begin always @(posedge clka) begin if (wea == 1'b1) begin - m_ram[{addra, 1'd0}] <= dina[((1*DATA_WIDTH_B)-1):(DATA_WIDTH_B*0)]; - m_ram[{addra, 1'd1}] <= dina[((2*DATA_WIDTH_B)-1):(DATA_WIDTH_B*1)]; + m_ram[{addra, 1'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; + m_ram[{addra, 1'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; end end end @@ -93,10 +93,10 @@ module ad_mem_asym ( if (MEM_RATIO == 4) begin always @(posedge clka) begin if (wea == 1'b1) begin - m_ram[{addra, 2'd0}] <= dina[((1*DATA_WIDTH_B)-1):(DATA_WIDTH_B*0)]; - m_ram[{addra, 2'd1}] <= dina[((2*DATA_WIDTH_B)-1):(DATA_WIDTH_B*1)]; - m_ram[{addra, 2'd2}] <= dina[((3*DATA_WIDTH_B)-1):(DATA_WIDTH_B*2)]; - m_ram[{addra, 2'd3}] <= dina[((4*DATA_WIDTH_B)-1):(DATA_WIDTH_B*3)]; + m_ram[{addra, 2'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; + m_ram[{addra, 2'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; + m_ram[{addra, 2'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)]; + m_ram[{addra, 2'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)]; end end end @@ -104,14 +104,14 @@ module ad_mem_asym ( if (MEM_RATIO == 8) begin always @(posedge clka) begin if (wea == 1'b1) begin - m_ram[{addra, 3'd0}] <= dina[((1*DATA_WIDTH_B)-1):(DATA_WIDTH_B*0)]; - m_ram[{addra, 3'd1}] <= dina[((2*DATA_WIDTH_B)-1):(DATA_WIDTH_B*1)]; - m_ram[{addra, 3'd2}] <= dina[((3*DATA_WIDTH_B)-1):(DATA_WIDTH_B*2)]; - m_ram[{addra, 3'd3}] <= dina[((4*DATA_WIDTH_B)-1):(DATA_WIDTH_B*3)]; - m_ram[{addra, 3'd4}] <= dina[((5*DATA_WIDTH_B)-1):(DATA_WIDTH_B*4)]; - m_ram[{addra, 3'd5}] <= dina[((6*DATA_WIDTH_B)-1):(DATA_WIDTH_B*5)]; - m_ram[{addra, 3'd6}] <= dina[((7*DATA_WIDTH_B)-1):(DATA_WIDTH_B*6)]; - m_ram[{addra, 3'd7}] <= dina[((8*DATA_WIDTH_B)-1):(DATA_WIDTH_B*7)]; + m_ram[{addra, 3'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; + m_ram[{addra, 3'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; + m_ram[{addra, 3'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)]; + m_ram[{addra, 3'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)]; + m_ram[{addra, 3'd4}] <= dina[((5*B_DATA_WIDTH)-1):(B_DATA_WIDTH*4)]; + m_ram[{addra, 3'd5}] <= dina[((6*B_DATA_WIDTH)-1):(B_DATA_WIDTH*5)]; + m_ram[{addra, 3'd6}] <= dina[((7*B_DATA_WIDTH)-1):(B_DATA_WIDTH*6)]; + m_ram[{addra, 3'd7}] <= dina[((8*B_DATA_WIDTH)-1):(B_DATA_WIDTH*7)]; end end end diff --git a/library/common/ad_mmcm_drp.v b/library/common/ad_mmcm_drp.v index 234254f8f..3f8a0b052 100644 --- a/library/common/ad_mmcm_drp.v +++ b/library/common/ad_mmcm_drp.v @@ -34,7 +34,7 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// MMCM with DRP and device specific +// MMCM_OR_BUFR_N with DRP and device specific `timescale 1ns/100ps diff --git a/library/common/ad_mul.v b/library/common/ad_mul.v index 2c3ad9f6a..c5b7986cf 100644 --- a/library/common/ad_mul.v +++ b/library/common/ad_mul.v @@ -85,8 +85,8 @@ module ad_mul ( MULT_MACRO #( .LATENCY (3), - .WIDTH_A (17), - .WIDTH_B (17)) + .A_DATA_WIDTH (17), + .B_DATA_WIDTH (17)) i_mult_macro ( .CE (1'b1), .RST (1'b0), diff --git a/library/common/ad_mul_u16.v b/library/common/ad_mul_u16.v index 265467e1b..eb4978dfb 100644 --- a/library/common/ad_mul_u16.v +++ b/library/common/ad_mul_u16.v @@ -94,8 +94,8 @@ module ad_mul_u16 ( MULT_MACRO #( .LATENCY (3), - .WIDTH_A (17), - .WIDTH_B (17)) + .A_DATA_WIDTH (17), + .B_DATA_WIDTH (17)) i_mult_macro ( .CE (1'b1), .RST (1'b0), diff --git a/library/common/ad_serdes_clk.v b/library/common/ad_serdes_clk.v index 13032c5ab..6adb1811f 100644 --- a/library/common/ad_serdes_clk.v +++ b/library/common/ad_serdes_clk.v @@ -63,8 +63,8 @@ module ad_serdes_clk ( // parameters - parameter SERDES = 1; - parameter MMCM = 1; + parameter SERDES_OR_DDR_N = 1; + parameter MMCM_OR_BUFR_N = 1; parameter MMCM_DEVICE_TYPE = 0; parameter MMCM_CLKIN_PERIOD = 1.667; parameter MMCM_VCO_DIV = 6; @@ -105,7 +105,7 @@ module ad_serdes_clk ( .O (clk_in_s)); generate - if (MMCM == 1) begin + if (MMCM_OR_BUFR_N == 1) begin ad_mmcm_drp #( .MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE), .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), @@ -129,7 +129,7 @@ module ad_serdes_clk ( .up_drp_locked (up_drp_locked)); end - if ((MMCM == 0) && (SERDES == 0)) begin + if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 0)) begin BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf ( .CLR (1'b0), .CE (1'b1), @@ -139,7 +139,7 @@ module ad_serdes_clk ( assign div_clk = clk; end - if ((MMCM == 0) && (SERDES == 1)) begin + if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin BUFIO i_clk_buf ( .I (clk_in_s), .O (clk)); diff --git a/library/common/ad_serdes_in.v b/library/common/ad_serdes_in.v index a0e123dea..5c4873ef1 100644 --- a/library/common/ad_serdes_in.v +++ b/library/common/ad_serdes_in.v @@ -79,9 +79,9 @@ module ad_serdes_in ( parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; // SDR = 0 / DDR = 1 - parameter IF_TYPE = 0; + parameter DDR_OR_SDR_N = 0; // serialization factor - parameter PARALLEL_WIDTH = 8; + parameter DATA_WIDTH = 8; localparam DEVICE_6SERIES = 1; localparam DEVICE_7SERIES = 0; @@ -175,10 +175,10 @@ module ad_serdes_in ( .CNTVALUEOUT (up_drdata)); // Note: The first sample in time will be data_s7, the last data_s0! - if(IF_TYPE == SDR) begin - ISERDESE2 #( + if(DDR_OR_SDR_N == SDR) begin + ISERDES_OR_DDR_NE2 #( .DATA_RATE("SDR"), - .DATA_WIDTH(PARALLEL_WIDTH), + .DATA_WIDTH(DATA_WIDTH), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), @@ -189,12 +189,12 @@ module ad_serdes_in ( .IOBDELAY("IFD"), .NUM_CE(2), .OFB_USED("FALSE"), - .SERDES_MODE("MASTER"), + .SERDES_OR_DDR_N_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) - ISERDESE2_inst ( + ISERDES_OR_DDR_NE2_inst ( .O(), .Q1(data_s0), .Q2(data_s1), @@ -226,9 +226,9 @@ module ad_serdes_in ( ); end else begin - ISERDESE2 #( + ISERDES_OR_DDR_NE2 #( .DATA_RATE("DDR"), - .DATA_WIDTH(PARALLEL_WIDTH), + .DATA_WIDTH(DATA_WIDTH), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), @@ -239,12 +239,12 @@ module ad_serdes_in ( .IOBDELAY("IFD"), .NUM_CE(2), .OFB_USED("FALSE"), - .SERDES_MODE("MASTER"), + .SERDES_OR_DDR_N_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) - ISERDESE2_inst ( + ISERDES_OR_DDR_NE2_inst ( .O(), .Q1(data_s0), .Q2(data_s1), @@ -304,9 +304,9 @@ module ad_serdes_in ( .CNTVALUEIN (up_dwdata), .CNTVALUEOUT (up_drdata)); - ISERDESE1 #( + ISERDES_OR_DDR_NE1 #( .DATA_RATE("DDR"), - .DATA_WIDTH(PARALLEL_WIDTH), + .DATA_WIDTH(DATA_WIDTH), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), @@ -317,7 +317,7 @@ module ad_serdes_in ( .IOBDELAY("NONE"), .NUM_CE(1), .OFB_USED("FALSE"), - .SERDES_MODE("MASTER"), + .SERDES_OR_DDR_N_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), @@ -349,9 +349,9 @@ module ad_serdes_in ( .SHIFTIN2(1'b0) ); - ISERDESE1 #( + ISERDES_OR_DDR_NE1 #( .DATA_RATE("DDR"), - .DATA_WIDTH(PARALLEL_WIDTH), + .DATA_WIDTH(DATA_WIDTH), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), @@ -362,7 +362,7 @@ module ad_serdes_in ( .IOBDELAY("NONE"), .NUM_CE(1), .OFB_USED("FALSE"), - .SERDES_MODE("SLAVE"), + .SERDES_OR_DDR_N_MODE("SLAVE"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), diff --git a/library/common/ad_serdes_out.v b/library/common/ad_serdes_out.v index b7036ed4f..931a7368c 100644 --- a/library/common/ad_serdes_out.v +++ b/library/common/ad_serdes_out.v @@ -64,7 +64,7 @@ module ad_serdes_out ( // parameters parameter DEVICE_TYPE = 0; - parameter SERDES = 1; + parameter SERDES_OR_DDR_N = 1; parameter DATA_WIDTH = 16; @@ -103,7 +103,7 @@ module ad_serdes_out ( generate for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data - if (SERDES == 0) begin + if (SERDES_OR_DDR_N == 0) begin ODDR #( .DDR_CLK_EDGE ("SAME_EDGE"), .INIT (1'b0), @@ -118,13 +118,13 @@ module ad_serdes_out ( .Q (data_out_s[l_inst])); end - if ((SERDES == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin - OSERDESE2 #( + if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin + OSERDES_OR_DDR_NE2 #( .DATA_RATE_OQ ("DDR"), .DATA_RATE_TQ ("SDR"), .DATA_WIDTH (8), .TRISTATE_WIDTH (1), - .SERDES_MODE ("MASTER")) + .SERDES_OR_DDR_N_MODE ("MASTER")) i_serdes ( .D1 (data_s0[l_inst]), .D2 (data_s1[l_inst]), @@ -155,14 +155,14 @@ module ad_serdes_out ( .RST (rst)); end - if ((SERDES == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin - OSERDESE1 #( + if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin + OSERDES_OR_DDR_NE1 #( .DATA_RATE_OQ ("DDR"), .DATA_RATE_TQ ("SDR"), .DATA_WIDTH (8), .INTERFACE_TYPE ("DEFAULT"), .TRISTATE_WIDTH (1), - .SERDES_MODE ("MASTER")) + .SERDES_OR_DDR_N_MODE ("MASTER")) i_serdes_m ( .D1 (data_s0[l_inst]), .D2 (data_s1[l_inst]), @@ -193,13 +193,13 @@ module ad_serdes_out ( .TCE (1'b0), .RST (rst)); - OSERDESE1 #( + OSERDES_OR_DDR_NE1 #( .DATA_RATE_OQ ("DDR"), .DATA_RATE_TQ ("SDR"), .DATA_WIDTH (8), .INTERFACE_TYPE ("DEFAULT"), .TRISTATE_WIDTH (1), - .SERDES_MODE ("SLAVE")) + .SERDES_OR_DDR_N_MODE ("SLAVE")) i_serdes_s ( .D1 (1'b0), .D2 (1'b0), diff --git a/library/common/ad_ss_422to444.v b/library/common/ad_ss_422to444.v index 613f9fa56..fbfdd2c6f 100644 --- a/library/common/ad_ss_422to444.v +++ b/library/common/ad_ss_422to444.v @@ -54,7 +54,7 @@ module ad_ss_422to444 ( // parameters - parameter Cr_Cb_N = 0; + parameter CR_CB_N = 0; parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; @@ -108,7 +108,7 @@ module ad_ss_422to444 ( if (s422_de_d == 1'b1) begin cr_cb_sel <= ~cr_cb_sel; end else begin - cr_cb_sel <= Cr_Cb_N; + cr_cb_sel <= CR_CB_N; end end diff --git a/library/common/ad_ss_444to422.v b/library/common/ad_ss_444to422.v index f94639124..3618cbcba 100644 --- a/library/common/ad_ss_444to422.v +++ b/library/common/ad_ss_444to422.v @@ -54,7 +54,7 @@ module ad_ss_444to422 ( // parameters - parameter Cr_Cb_N = 0; + parameter CR_CB_N = 0; parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; @@ -128,7 +128,7 @@ module ad_ss_444to422 ( if (s444_de_3d == 1'b1) begin cr_cb_sel <= ~cr_cb_sel; end else begin - cr_cb_sel <= Cr_Cb_N; + cr_cb_sel <= CR_CB_N; end end diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index 459a6e1b2..e06eda2b6 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -491,9 +491,9 @@ module ad_tdd_control( // internal datapath delay compensation ad_addsub #( - .A_WIDTH(24), - .CONST_VALUE(11), - .ADD_SUB(1) + .A_DATA_WIDTH(24), + .B_DATA_VALUE(11), + .ADD_OR_SUB_N(0) ) i_tx_dp_on_1_comp ( .clk(clk), .A(tdd_tx_dp_on_1), @@ -503,9 +503,9 @@ module ad_tdd_control( ); ad_addsub #( - .A_WIDTH(24), - .CONST_VALUE(11), - .ADD_SUB(1) + .A_DATA_WIDTH(24), + .B_DATA_VALUE(11), + .ADD_OR_SUB_N(0) ) i_tx_dp_on_2_comp ( .clk(clk), .A(tdd_tx_dp_on_2), @@ -515,9 +515,9 @@ module ad_tdd_control( ); ad_addsub #( - .A_WIDTH(24), - .CONST_VALUE(11), - .ADD_SUB(1) + .A_DATA_WIDTH(24), + .B_DATA_VALUE(11), + .ADD_OR_SUB_N(0) ) i_tx_dp_off_1_comp ( .clk(clk), .A(tdd_tx_dp_off_1), @@ -527,9 +527,9 @@ module ad_tdd_control( ); ad_addsub #( - .A_WIDTH(24), - .CONST_VALUE(11), - .ADD_SUB(1) + .A_DATA_WIDTH(24), + .B_DATA_VALUE(11), + .ADD_OR_SUB_N(0) ) i_tx_dp_off_2_comp ( .clk(clk), .A(tdd_tx_dp_off_2), diff --git a/library/common/altera/MULT_MACRO.v b/library/common/altera/MULT_MACRO.v index c961ed99b..713ace7ff 100644 --- a/library/common/altera/MULT_MACRO.v +++ b/library/common/altera/MULT_MACRO.v @@ -50,23 +50,23 @@ module MULT_MACRO ( P); parameter LATENCY = 3; - parameter WIDTH_A = 16; - parameter WIDTH_B = 16; + parameter A_DATA_WIDTH = 16; + parameter B_DATA_WIDTH = 16; - localparam WIDTH_P = WIDTH_A + WIDTH_B; + localparam WIDTH_P = A_DATA_WIDTH + B_DATA_WIDTH; input CE; input RST; input CLK; - input [WIDTH_A-1:0] A; - input [WIDTH_B-1:0] B; + input [A_DATA_WIDTH-1:0] A; + input [B_DATA_WIDTH-1:0] B; output [WIDTH_P-1:0] P; lpm_mult #( .lpm_type ("lpm_mult"), - .lpm_widtha (WIDTH_A), - .lpm_widthb (WIDTH_B), + .lpm_widtha (A_DATA_WIDTH), + .lpm_widthb (B_DATA_WIDTH), .lpm_widthp (WIDTH_P), .lpm_representation ("SIGNED"), .lpm_pipeline (3)) diff --git a/library/common/altera/ad_lvds_clk.v b/library/common/altera/ad_lvds_clk.v index f9ea1365e..eab93e029 100644 --- a/library/common/altera/ad_lvds_clk.v +++ b/library/common/altera/ad_lvds_clk.v @@ -45,7 +45,7 @@ module ad_lvds_clk ( clk_in_n, clk); - parameter BUFTYPE = 0; + parameter DEVICE_TYPE = 0; localparam SERIES7 = 0; localparam VIRTEX6 = 1; diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v index 459a14019..7ab54045e 100644 --- a/library/common/altera/ad_lvds_in.v +++ b/library/common/altera/ad_lvds_in.v @@ -60,7 +60,7 @@ module ad_lvds_in ( // parameters - parameter BUFTYPE = 0; + parameter DEVICE_TYPE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; localparam SERIES7 = 0; diff --git a/library/common/altera/ad_lvds_out.v b/library/common/altera/ad_lvds_out.v index 81f24f4a4..edc756114 100644 --- a/library/common/altera/ad_lvds_out.v +++ b/library/common/altera/ad_lvds_out.v @@ -51,7 +51,7 @@ module ad_lvds_out ( // parameters - parameter BUFTYPE = 0; + parameter DEVICE_TYPE = 0; localparam SERIES7 = 0; localparam VIRTEX6 = 1; diff --git a/library/common/sync_bits.v b/library/common/sync_bits.v index 674d95627..cec9f09ec 100644 --- a/library/common/sync_bits.v +++ b/library/common/sync_bits.v @@ -45,20 +45,20 @@ */ module sync_bits ( - input [NUM_BITS-1:0] in, + input [NUM_OF_BITS-1:0] in, input out_resetn, input out_clk, - output [NUM_BITS-1:0] out + output [NUM_OF_BITS-1:0] out ); // Number of bits to synchronize -parameter NUM_BITS = 1; +parameter NUM_OF_BITS = 1; // Whether input and output clocks are asynchronous, if 0 the synchronizer will // be bypassed and the output signal equals the input signal. -parameter CLK_ASYNC = 1; +parameter ASYNC_CLK = 1; -reg [NUM_BITS-1:0] cdc_sync_stage1 = 'h0; -reg [NUM_BITS-1:0] cdc_sync_stage2 = 'h0; +reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0; +reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; always @(posedge out_clk) begin @@ -71,6 +71,6 @@ begin end end -assign out = CLK_ASYNC ? cdc_sync_stage2 : in; +assign out = ASYNC_CLK ? cdc_sync_stage2 : in; endmodule diff --git a/library/common/sync_gray.v b/library/common/sync_gray.v index 06d7d4472..701dfe37c 100644 --- a/library/common/sync_gray.v +++ b/library/common/sync_gray.v @@ -55,7 +55,7 @@ module sync_gray ( parameter DATA_WIDTH = 1; // Whether the input and output clock are asynchronous, if set to 0 the // synchronizer will be bypassed and out_count will be in_count. -parameter CLK_ASYNC = 1; +parameter ASYNC_CLK = 1; reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0; reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0; @@ -106,6 +106,6 @@ always @(posedge out_clk) begin end end -assign out_count = CLK_ASYNC ? out_count_m : in_count; +assign out_count = ASYNC_CLK ? out_count_m : in_count; endmodule diff --git a/library/common/up_adc_channel.v b/library/common/up_adc_channel.v index 2e2fb0bfc..db3278c6c 100644 --- a/library/common/up_adc_channel.v +++ b/library/common/up_adc_channel.v @@ -96,7 +96,7 @@ module up_adc_channel ( // parameters - parameter PCORE_ADC_CHID = 4'h0; + parameter ADC_CHANNEL_ID = 4'h0; // adc interface @@ -211,8 +211,8 @@ module up_adc_channel ( // decode block select - assign up_wreq_s = ((up_waddr[13:8] == 6'h01) && (up_waddr[7:4] == PCORE_ADC_CHID)) ? up_wreq : 1'b0; - assign up_rreq_s = ((up_raddr[13:8] == 6'h01) && (up_raddr[7:4] == PCORE_ADC_CHID)) ? up_rreq : 1'b0; + assign up_wreq_s = ((up_waddr[13:8] == 6'h01) && (up_waddr[7:4] == ADC_CHANNEL_ID)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == 6'h01) && (up_raddr[7:4] == ADC_CHANNEL_ID)) ? up_rreq : 1'b0; // processor write interface diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 65fb42fe6..373e9e8fa 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -97,7 +97,7 @@ module up_adc_common ( // parameters localparam PCORE_VERSION = 32'h00090062; - parameter PCORE_ID = 0; + parameter ID = 0; // clock reset @@ -298,7 +298,7 @@ module up_adc_common ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; diff --git a/library/common/up_axi.v b/library/common/up_axi.v index 6804b3ced..91e1e7c1b 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -79,8 +79,8 @@ module up_axi ( // parameters - parameter PCORE_ADDR_WIDTH = 14; - localparam AW = PCORE_ADDR_WIDTH - 1; + parameter ADDRESS_WIDTH = 14; + localparam AW = ADDRESS_WIDTH - 1; // reset and clocks diff --git a/library/common/up_axis_dma_rx.v b/library/common/up_axis_dma_rx.v index 457a0c07b..71494cf80 100644 --- a/library/common/up_axis_dma_rx.v +++ b/library/common/up_axis_dma_rx.v @@ -74,7 +74,7 @@ module up_axis_dma_rx ( // parameters localparam PCORE_VERSION = 32'h00050063; - parameter PCORE_ID = 0; + parameter ID = 0; // adc interface @@ -189,7 +189,7 @@ module up_axis_dma_rx ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {31'd0, up_resetn}; 8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start}; diff --git a/library/common/up_axis_dma_tx.v b/library/common/up_axis_dma_tx.v index d29147c58..454ed9f37 100644 --- a/library/common/up_axis_dma_tx.v +++ b/library/common/up_axis_dma_tx.v @@ -70,7 +70,7 @@ module up_axis_dma_tx ( // parameters localparam PCORE_VERSION = 32'h00050062; - parameter PCORE_ID = 0; + parameter ID = 0; // dac interface @@ -169,7 +169,7 @@ module up_axis_dma_tx ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {31'd0, up_resetn}; 8'h21: up_rdata <= up_dma_frmcnt; diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v index b45f62050..2c6d47175 100644 --- a/library/common/up_clkgen.v +++ b/library/common/up_clkgen.v @@ -69,7 +69,7 @@ module up_clkgen ( // parameters localparam PCORE_VERSION = 32'h00040063; - parameter PCORE_ID = 0; + parameter ID = 0; // mmcm reset @@ -186,7 +186,7 @@ module up_clkgen ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h17: up_rdata <= {31'd0, up_drp_locked}; diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v index 443b82f38..e4507cfd7 100644 --- a/library/common/up_dac_channel.v +++ b/library/common/up_dac_channel.v @@ -90,7 +90,7 @@ module up_dac_channel ( // parameters - parameter PCORE_DAC_CHID = 4'h0; + parameter DAC_CHANNEL_ID = 4'h0; // dac interface @@ -193,8 +193,8 @@ module up_dac_channel ( // decode block select - assign up_wreq_s = ((up_waddr[13:8] == 6'h11) && (up_waddr[7:4] == PCORE_DAC_CHID)) ? up_wreq : 1'b0; - assign up_rreq_s = ((up_raddr[13:8] == 6'h11) && (up_raddr[7:4] == PCORE_DAC_CHID)) ? up_rreq : 1'b0; + assign up_wreq_s = ((up_waddr[13:8] == 6'h11) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == 6'h11) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0; // processor write interface diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index bddb1a72e..c74fb666f 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -92,7 +92,7 @@ module up_dac_common ( // parameters localparam PCORE_VERSION = 32'h00080062; - parameter PCORE_ID = 0; + parameter ID = 0; // mmcm reset @@ -309,7 +309,7 @@ module up_dac_common ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h11: up_rdata <= {31'd0, up_dac_sync}; diff --git a/library/common/up_delay_cntrl.v b/library/common/up_delay_cntrl.v index febaa9cb6..c20bcef90 100644 --- a/library/common/up_delay_cntrl.v +++ b/library/common/up_delay_cntrl.v @@ -66,8 +66,8 @@ module up_delay_cntrl ( // parameters - parameter IO_WIDTH = 8; - parameter IO_BASEADDR = 6'h02; + parameter DATA_WIDTH = 8; + parameter BASE_ADDRESS = 6'h02; // delay interface @@ -77,9 +77,9 @@ module up_delay_cntrl ( // io interface - output [(IO_WIDTH-1):0] up_dld; - output [((IO_WIDTH*5)-1):0] up_dwdata; - input [((IO_WIDTH*5)-1):0] up_drdata; + output [(DATA_WIDTH-1):0] up_dld; + output [((DATA_WIDTH*5)-1):0] up_dwdata; + input [((DATA_WIDTH*5)-1):0] up_drdata; // processor interface @@ -102,19 +102,19 @@ module up_delay_cntrl ( reg [31:0] up_rdata = 'd0; reg up_dlocked_m1 = 'd0; reg up_dlocked = 'd0; - reg [(IO_WIDTH-1):0] up_dld = 'd0; - reg [((IO_WIDTH*5)-1):0] up_dwdata = 'd0; + reg [(DATA_WIDTH-1):0] up_dld = 'd0; + reg [((DATA_WIDTH*5)-1):0] up_dwdata = 'd0; // internal signals wire up_wreq_s; wire up_rreq_s; wire [ 4:0] up_rdata_s; - wire [(IO_WIDTH-1):0] up_drdata4_s; - wire [(IO_WIDTH-1):0] up_drdata3_s; - wire [(IO_WIDTH-1):0] up_drdata2_s; - wire [(IO_WIDTH-1):0] up_drdata1_s; - wire [(IO_WIDTH-1):0] up_drdata0_s; + wire [(DATA_WIDTH-1):0] up_drdata4_s; + wire [(DATA_WIDTH-1):0] up_drdata3_s; + wire [(DATA_WIDTH-1):0] up_drdata2_s; + wire [(DATA_WIDTH-1):0] up_drdata1_s; + wire [(DATA_WIDTH-1):0] up_drdata0_s; // variables @@ -122,8 +122,8 @@ module up_delay_cntrl ( // decode block select - assign up_wreq_s = (up_waddr[13:8] == IO_BASEADDR) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == IO_BASEADDR) ? up_rreq : 1'b0; + assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0; assign up_rdata_s[4] = | up_drdata4_s; assign up_rdata_s[3] = | up_drdata3_s; assign up_rdata_s[2] = | up_drdata2_s; @@ -131,7 +131,7 @@ module up_delay_cntrl ( assign up_rdata_s[0] = | up_drdata0_s; generate - for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_drd + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_drd assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0; assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0; assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0; @@ -171,7 +171,7 @@ module up_delay_cntrl ( // write does not hold- read back what goes into effect. generate - for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_dwr + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin up_dld[n] <= 'd0; diff --git a/library/common/up_gt.v b/library/common/up_gt.v index dc44e1765..43ee7dcb5 100644 --- a/library/common/up_gt.v +++ b/library/common/up_gt.v @@ -70,7 +70,7 @@ module up_gt ( // parameters localparam [31:0] VERSION = 32'h00070161; - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; parameter integer ID = 0; // drp interface @@ -219,7 +219,7 @@ module up_gt ( 8'h24: up_rdata <= {3'd0, up_drp_qpll1_rwn, up_drp_qpll1_addr, up_drp_qpll1_wdata}; 8'h25: up_rdata <= {15'd0, up_drp_qpll1_status, up_drp_qpll1_rdata}; - 8'h3a: up_rdata <= GTH_GTX_N; + 8'h3a: up_rdata <= GTH_OR_GTX_N; default: up_rdata <= 0; endcase end else begin diff --git a/library/common/up_gt_channel.v b/library/common/up_gt_channel.v index bbbe4f027..c8ca5f809 100644 --- a/library/common/up_gt_channel.v +++ b/library/common/up_gt_channel.v @@ -144,7 +144,7 @@ module up_gt_channel ( // parameters parameter integer ID = 0; - parameter integer GTH_GTX_N = 0; + parameter integer GTH_OR_GTX_N = 0; // gt interface @@ -642,7 +642,7 @@ module up_gt_channel ( 8'h33: up_rdata <= up_es_qdata4; 8'h38: up_rdata <= {30'd0, up_es_dma_err_hold, up_es_status}; 8'h39: up_rdata <= {24'd0, up_drp_rxrate}; - 8'h3a: up_rdata <= GTH_GTX_N; + 8'h3a: up_rdata <= GTH_OR_GTX_N; default: up_rdata <= 0; endcase end else begin diff --git a/library/common/up_hdmi_rx.v b/library/common/up_hdmi_rx.v index 0931db20c..a9c698677 100644 --- a/library/common/up_hdmi_rx.v +++ b/library/common/up_hdmi_rx.v @@ -74,7 +74,7 @@ module up_hdmi_rx ( // parameters localparam PCORE_VERSION = 32'h00040063; - parameter PCORE_ID = 0; + parameter ID = 0; // hdmi interface @@ -237,7 +237,7 @@ module up_hdmi_rx ( if(up_rreq_s == 1'b1) begin case (up_raddr[11:0]) 12'h000: up_rdata <= PCORE_VERSION; - 12'h001: up_rdata <= PCORE_ID; + 12'h001: up_rdata <= ID; 12'h002: up_rdata <= up_scratch; 12'h010: up_rdata <= {31'h0, ~up_preset}; 12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass}; diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index 6bdb31ea3..a181f516a 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -86,7 +86,7 @@ module up_hdmi_tx ( // parameters localparam PCORE_VERSION = 32'h00040063; - parameter PCORE_ID = 0; + parameter ID = 0; // hdmi interface @@ -279,7 +279,7 @@ module up_hdmi_tx ( if (up_rreq_s == 1'b1) begin case (up_raddr[11:0]) 12'h000: up_rdata <= PCORE_VERSION; - 12'h001: up_rdata <= PCORE_ID; + 12'h001: up_rdata <= ID; 12'h002: up_rdata <= up_scratch; 12'h010: up_rdata <= {31'd0, up_resetn}; 12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass}; diff --git a/library/common/up_pmod.v b/library/common/up_pmod.v index e20b07565..2e1c14590 100644 --- a/library/common/up_pmod.v +++ b/library/common/up_pmod.v @@ -61,7 +61,7 @@ module up_pmod ( // parameters localparam PCORE_VERSION = 32'h00010001; - parameter PCORE_ID = 0; + parameter ID = 0; input pmod_clk; output pmod_rst; @@ -129,7 +129,7 @@ module up_pmod ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h03: up_rdata <= up_pmod_signal_freq_s; 8'h10: up_rdata <= up_resetn; diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 2136b18e5..066fcf5a8 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -96,7 +96,7 @@ module up_tdd_cntrl ( // parameters localparam PCORE_VERSION = 32'h00010001; - parameter PCORE_ID = 0; + parameter ID = 0; input clk; input rst; diff --git a/library/common/up_xcvr.v b/library/common/up_xcvr.v index e223b08aa..48d9b6b18 100644 --- a/library/common/up_xcvr.v +++ b/library/common/up_xcvr.v @@ -79,8 +79,8 @@ module up_xcvr ( // parameters localparam PCORE_VERSION = 32'h00060162; - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; + parameter ID = 0; + parameter DEVICE_TYPE = 0; // common reset @@ -235,7 +235,7 @@ module up_xcvr ( if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h03: up_rdata <= {31'd0, up_resetn}; 8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref}; @@ -246,7 +246,7 @@ module up_xcvr ( 8'h21: up_rdata <= {31'd0, up_tx_sync}; 8'h22: up_rdata <= {23'd0, up_tx_status}; 8'h23: up_rdata <= {31'd0, up_tx_resetn}; - 8'h30: up_rdata <= PCORE_DEVICE_TYPE; + 8'h30: up_rdata <= DEVICE_TYPE; default: up_rdata <= 0; endcase end else begin diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 8db1a93a9..35bf015e5 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -68,10 +68,10 @@ parameter ASYNC_SPI_CLK = 0; parameter NUM_OFFLOAD = 0; -parameter OFFLOAD0_CMD_MEM_ADDR_WIDTH = 4; -parameter OFFLOAD0_SDO_MEM_ADDR_WIDTH = 4; +parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4; +parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4; -parameter PCORE_ID = 'h00; +parameter ID = 'h00; localparam PCORE_VERSION = 'h010061; wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room; @@ -114,7 +114,7 @@ reg [7:0] sync_id = 'h00; reg sync_id_pending = 1'b0; up_axi #( - .PCORE_ADDR_WIDTH (8) + .ADDRESS_WIDTH (8) ) i_up_axi ( .up_rstn(s_axi_aresetn), .up_clk(s_axi_aclk), @@ -200,7 +200,7 @@ end always @(posedge s_axi_aclk) begin case (up_raddr) 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; + 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= up_reset; 8'h20: up_rdata <= up_irq_mask; @@ -258,10 +258,10 @@ assign cmd_fifo_almost_empty = `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH); util_axis_fifo #( - .C_DATA_WIDTH(16), - .C_CLKS_ASYNC(ASYNC_SPI_CLK), - .C_ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), - .C_S_AXIS_REGISTERED(0) + .DATA_WIDTH(16), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), + .S_AXIS_REGISTERED(0) ) i_cmd_fifo ( .s_axis_aclk(s_axi_aclk), .s_axis_aresetn(up_resetn), @@ -283,10 +283,10 @@ assign sdo_fifo_almost_empty = `axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH); util_axis_fifo #( - .C_DATA_WIDTH(8), - .C_CLKS_ASYNC(ASYNC_SPI_CLK), - .C_ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), - .C_S_AXIS_REGISTERED(0) + .DATA_WIDTH(8), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), + .S_AXIS_REGISTERED(0) ) i_sdo_fifo ( .s_axis_aclk(s_axi_aclk), .s_axis_aresetn(up_resetn), @@ -307,10 +307,10 @@ assign sdi_fifo_almost_full = `axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH); util_axis_fifo #( - .C_DATA_WIDTH(8), - .C_CLKS_ASYNC(ASYNC_SPI_CLK), - .C_ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), - .C_S_AXIS_REGISTERED(0) + .DATA_WIDTH(8), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), + .S_AXIS_REGISTERED(0) ) i_sdi_fifo ( .s_axis_aclk(spi_clk), .s_axis_aresetn(spi_resetn), diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v index 2593adbad..12173a6e7 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -25,11 +25,11 @@ module spi_engine_execution ( output sdo, output reg sdo_t, input sdi, - output reg [NUM_CS-1:0] cs, + output reg [NUM_OF_CS-1:0] cs, output reg three_wire ); -parameter NUM_CS = 1; +parameter NUM_OF_CS = 1; parameter DEFAULT_SPI_CFG = 0; parameter DEFAULT_CLK_DIV = 0; @@ -198,7 +198,7 @@ always @(posedge clk) begin if (resetn == 1'b0) begin cs <= 'hff; end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin - cs <= cmd_d1[NUM_CS-1:0]; + cs <= cmd_d1[NUM_OF_CS-1:0]; end end diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v index 8662c46e8..862b869b1 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v @@ -38,21 +38,21 @@ module spi_engine_offload ( output [7:0] offload_sdi_data ); -parameter SPI_CLK_ASYNC = 0; -parameter CMD_MEM_ADDR_WIDTH = 4; -parameter SDO_MEM_ADDR_WIDTH = 4; +parameter ASYNC_SPI_CLK = 0; +parameter CMD_MEM_ADDRESS_WIDTH = 4; +parameter SDO_MEM_ADDRESS_WIDTH = 4; reg spi_active = 1'b0; -reg [CMD_MEM_ADDR_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00; -reg [CMD_MEM_ADDR_WIDTH-1:0] spi_cmd_rd_addr = 'h00; -reg [SDO_MEM_ADDR_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00; -reg [SDO_MEM_ADDR_WIDTH-1:0] spi_sdo_rd_addr = 'h00; +reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00; +reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00; +reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00; +reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00; -reg [15:0] cmd_mem[0:2**CMD_MEM_ADDR_WIDTH-1]; -reg [7:0] sdo_mem[0:2**SDO_MEM_ADDR_WIDTH-1]; +reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1]; +reg [7:0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1]; -wire [CMD_MEM_ADDR_WIDTH-1:0] spi_cmd_rd_addr_next; +wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next; wire spi_enable; assign cmd_valid = spi_active; @@ -66,7 +66,7 @@ assign offload_sdi_data = sdi_data; assign cmd = cmd_mem[spi_cmd_rd_addr]; assign sdo_data = sdo_mem[spi_sdo_rd_addr]; -generate if (SPI_CLK_ASYNC) begin +generate if (ASYNC_SPI_CLK) begin /* * The synchronization circuit takes care that there are no glitches on the @@ -96,8 +96,8 @@ always @(posedge spi_clk) begin end sync_bits # ( - .NUM_BITS(1), - .CLK_ASYNC(1) + .NUM_OF_BITS(1), + .ASYNC_CLK(1) ) i_sync_enable ( .in(ctrl_do_enable), .out_clk(spi_clk), @@ -106,8 +106,8 @@ sync_bits # ( ); sync_bits # ( - .NUM_BITS(1), - .CLK_ASYNC(1) + .NUM_OF_BITS(1), + .ASYNC_CLK(1) ) i_sync_enabled ( .in(spi_enabled), .out_clk(ctrl_clk), diff --git a/library/util_adc_pack/util_adc_pack.v b/library/util_adc_pack/util_adc_pack.v index a5607617d..6a7dae0ab 100644 --- a/library/util_adc_pack/util_adc_pack.v +++ b/library/util_adc_pack/util_adc_pack.v @@ -81,8 +81,8 @@ module util_adc_pack ( ); - parameter CHANNELS = 8 ; // valid values are 4 and 8 - parameter DATA_WIDTH = 16; // valid values are 16 and 32 + parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8 + parameter DATA_WIDTH = 16; // valid values are 16 and 32 // common clock input clk; @@ -119,13 +119,13 @@ module util_adc_pack ( input chan_enable_7; input [(DATA_WIDTH-1):0] chan_data_7; - output [(DATA_WIDTH*CHANNELS-1):0] ddata; + output [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata; output dvalid; output dsync; - reg [(DATA_WIDTH*CHANNELS-1):0] packed_data = 0; - reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_0 = 0; - reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_1 = 0; + reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] packed_data = 0; + reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] temp_data_0 = 0; + reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] temp_data_1 = 0; reg [3:0] enable_cnt; reg [2:0] enable_cnt_0; @@ -140,7 +140,7 @@ module util_adc_pack ( reg [7:0] en4 = 0; reg dvalid = 0; - reg [(DATA_WIDTH*CHANNELS-1):0] ddata = 0; + reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata = 0; reg [(DATA_WIDTH-1):0] chan_data_0_r; reg [(DATA_WIDTH-1):0] chan_data_1_r; reg [(DATA_WIDTH-1):0] chan_data_2_r; @@ -159,7 +159,7 @@ module util_adc_pack ( begin enable_cnt = enable_cnt_0 + enable_cnt_1; enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3; - if (CHANNELS == 8) + if (NUM_OF_CHANNELS == 8) begin enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7; end @@ -297,7 +297,7 @@ module util_adc_pack ( end 4: begin - if (CHANNELS == 8) + if (NUM_OF_CHANNELS == 8) begin en1 = path_enabled[0] << 4; en2 = {2{path_enabled[1]}} << 4; @@ -354,15 +354,15 @@ module util_adc_pack ( begin if( chan_valid == 1'b1) begin - if (counter_0 > (CHANNELS - 1) ) + if (counter_0 > (NUM_OF_CHANNELS - 1) ) begin - counter_0 <= counter_0 - CHANNELS + enable_cnt; + counter_0 <= counter_0 - NUM_OF_CHANNELS + enable_cnt; end else begin counter_0 <= counter_0 + enable_cnt; end - if ((counter_0 == (CHANNELS - enable_cnt)) || (path_enabled == (8'h1 << (CHANNELS - 1)) )) + if ((counter_0 == (NUM_OF_CHANNELS - enable_cnt)) || (path_enabled == (8'h1 << (NUM_OF_CHANNELS - 1)) )) begin dvalid <= 1'b1; end @@ -379,14 +379,14 @@ module util_adc_pack ( end generate - // 8 CHANNELS - if ( CHANNELS == 8 ) + // 8 NUM_OF_CHANNELS + if ( NUM_OF_CHANNELS == 8 ) begin - // FIRST FOUR CHANNELS + // FIRST FOUR NUM_OF_CHANNELS always @(posedge clk) begin // ddata 0 - if ((en1[0] | en2[0] | en4[0] | path_enabled[CHANNELS-1]) == 1'b1) + if ((en1[0] | en2[0] | en4[0] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) begin ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0]; end @@ -396,7 +396,7 @@ module util_adc_pack ( begin ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; end - if ( (en2[1] | en4[1] | path_enabled[CHANNELS-1]) == 1'b1) + if ( (en2[1] | en4[1] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) begin ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; end @@ -406,7 +406,7 @@ module util_adc_pack ( begin ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; end - if ((en4[2] | path_enabled[CHANNELS-1]) == 1'b1) + if ((en4[2] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) begin ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH]; end @@ -420,7 +420,7 @@ module util_adc_pack ( begin ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; end - if ((en4[3] | path_enabled[CHANNELS-1]) == 1'b1) + if ((en4[3] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) begin ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH]; end @@ -430,7 +430,7 @@ module util_adc_pack ( begin ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; end - if (path_enabled[CHANNELS-1] == 1'b1) + if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) begin ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[5*DATA_WIDTH-1:4*DATA_WIDTH]; end @@ -444,7 +444,7 @@ module util_adc_pack ( begin ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; end - if (path_enabled[CHANNELS-1] == 1'b1) + if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) begin ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[6*DATA_WIDTH-1:5*DATA_WIDTH]; end @@ -458,7 +458,7 @@ module util_adc_pack ( begin ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH]; end - if (path_enabled[CHANNELS-1] == 1'b1) + if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) begin ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[7*DATA_WIDTH-1:6*DATA_WIDTH]; end @@ -476,7 +476,7 @@ module util_adc_pack ( begin ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH]; end - if (path_enabled[CHANNELS-1] == 1'b1) + if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) begin ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[8*DATA_WIDTH-1:7*DATA_WIDTH]; end diff --git a/library/util_adc_pack/util_adc_pack_hw.tcl b/library/util_adc_pack/util_adc_pack_hw.tcl index 891c9d508..30c58480a 100644 --- a/library/util_adc_pack/util_adc_pack_hw.tcl +++ b/library/util_adc_pack/util_adc_pack_hw.tcl @@ -17,14 +17,14 @@ add_fileset_file util_adc_pack.v VERILOG PATH util_adc_pack.v # parameters -add_parameter CHANNELS INTEGER 0 -set_parameter_property CHANNELS DEFAULT_VALUE 8 -set_parameter_property CHANNELS ALLOWED_RANGES {4 8} -set_parameter_property CHANNELS DESCRIPTION "Valid values are 4 and 8" -set_parameter_property CHANNELS DISPLAY_NAME CHANNELS -set_parameter_property CHANNELS TYPE INTEGER -set_parameter_property CHANNELS UNITS None -set_parameter_property CHANNELS HDL_PARAMETER true +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8} +set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8" +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true add_parameter DATA_WIDTH INTEGER 0 set_parameter_property DATA_WIDTH DEFAULT_VALUE 16 @@ -59,12 +59,12 @@ add_interface_port channels_data chan_data_3 chan_data_3 Input DATA_WIDTH proc util_adc_pack_elaborate {} { set DW [ get_parameter_value DATA_WIDTH ] - set CHAN [ get_parameter_value CHANNELS ] + set CHAN [ get_parameter_value NUM_OF_CHANNELS ] add_interface_port channels_data dvalid dvalid Output 1 add_interface_port channels_data dsync dsync Output 1 add_interface_port channels_data ddata ddata Output [expr {$DW * $CHAN}] - if {[get_parameter_value CHANNELS] == 8} { + if {[get_parameter_value NUM_OF_CHANNELS] == 8} { add_interface_port channels_data chan_enable_4 chan_enable_4 Input 1 add_interface_port channels_data chan_valid_4 chan_valid_4 Input 1 diff --git a/library/util_adc_pack/util_adc_pack_ip.tcl b/library/util_adc_pack/util_adc_pack_ip.tcl index a69d67943..e2f31f206 100644 --- a/library/util_adc_pack/util_adc_pack_ip.tcl +++ b/library/util_adc_pack/util_adc_pack_ip.tcl @@ -22,7 +22,7 @@ for {set i 0} {$i < 8} {incr i} { foreach port {"chan_enable" "chan_valid" "chan_data"} { set name [format "%s_%d" $port $i] set_property ENABLEMENT_DEPENDENCY \ - "(spirit:decode(id('MODELPARAM_VALUE.CHANNELS')) > $i)" \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \ [ipx::get_ports $name] set_property DRIVER_VALUE "0" [ipx::get_ports $name] } diff --git a/library/util_adcfifo/util_adcfifo.v b/library/util_adcfifo/util_adcfifo.v index eb6d88357..210f38ea2 100644 --- a/library/util_adcfifo/util_adcfifo.v +++ b/library/util_adcfifo/util_adcfifo.v @@ -63,12 +63,12 @@ module util_adcfifo ( parameter ADC_DATA_WIDTH = 256; parameter DMA_DATA_WIDTH = 64; parameter DMA_READY_ENABLE = 1; - parameter DMA_ADDR_WIDTH = 10; + parameter DMA_ADDRESS_WIDTH = 10; localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH; - localparam ADC_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) : - ((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3)); - localparam ADC_ADDR_LIMIT = (2**ADC_ADDR_WIDTH)-1; + localparam ADC_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : + ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3)); + localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1; // adc interface @@ -94,21 +94,21 @@ module util_adcfifo ( reg adc_xfer_enable = 'd0; reg adc_wr_int = 'd0; reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0; - reg [ADC_ADDR_WIDTH-1:0] adc_waddr_int = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0; reg adc_waddr_rel_t = 'd0; - reg [ADC_ADDR_WIDTH-1:0] adc_waddr_rel = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_rel = 'd0; reg dma_rst = 'd0; reg [ 2:0] dma_waddr_rel_t_m = 'd0; - reg [ADC_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0; reg dma_rd = 'd0; reg dma_rd_d = 'd0; reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0; - reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0; // internal signals wire dma_waddr_rel_t_s; - wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s; + wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s; wire dma_wready_s; wire dma_rd_s; wire [DMA_DATA_WIDTH-1:0] dma_rdata_s; @@ -209,10 +209,10 @@ module util_adcfifo ( // instantiations ad_mem_asym #( - .ADDR_WIDTH_A (ADC_ADDR_WIDTH), - .DATA_WIDTH_A (ADC_DATA_WIDTH), - .ADDR_WIDTH_B (DMA_ADDR_WIDTH), - .DATA_WIDTH_B (DMA_DATA_WIDTH)) + .A_ADDRESS_WIDTH (ADC_ADDRESS_WIDTH), + .A_DATA_WIDTH (ADC_DATA_WIDTH), + .B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), + .B_DATA_WIDTH (DMA_DATA_WIDTH)) i_mem_asym ( .clka (adc_clk), .wea (adc_wr_int), diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v index 5ebd4882e..a6aad02e3 100644 --- a/library/util_axis_fifo/address_gray.v +++ b/library/util_axis_fifo/address_gray.v @@ -41,36 +41,36 @@ module fifo_address_gray ( input m_axis_aresetn, input m_axis_ready, output reg m_axis_valid, - output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next, - output reg [C_ADDRESS_WIDTH:0] m_axis_level, + output [ADDRESS_WIDTH-1:0] m_axis_raddr_next, + output reg [ADDRESS_WIDTH:0] m_axis_level, input s_axis_aclk, input s_axis_aresetn, output reg s_axis_ready, input s_axis_valid, output reg s_axis_empty, - output [C_ADDRESS_WIDTH-1:0] s_axis_waddr, - output reg [C_ADDRESS_WIDTH:0] s_axis_room + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room ); -parameter C_ADDRESS_WIDTH = 4; +parameter ADDRESS_WIDTH = 4; -reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; -reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next; +reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; +reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; -reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; -reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next; +reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; +reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; -reg [C_ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00; -wire [C_ADDRESS_WIDTH:0] s_axis_waddr_gray_next; -wire [C_ADDRESS_WIDTH:0] s_axis_raddr_gray; +reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00; +wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next; +wire [ADDRESS_WIDTH:0] s_axis_raddr_gray; -reg [C_ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00; -wire [C_ADDRESS_WIDTH:0] m_axis_raddr_gray_next; -wire [C_ADDRESS_WIDTH:0] m_axis_waddr_gray; +reg [ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00; +wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next; +wire [ADDRESS_WIDTH:0] m_axis_waddr_gray; -assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0]; -assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0]; +assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; +assign m_axis_raddr_next = _m_axis_raddr_next[ADDRESS_WIDTH-1:0]; always @(*) begin @@ -80,7 +80,7 @@ begin _s_axis_waddr_next <= _s_axis_waddr; end -assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[C_ADDRESS_WIDTH:1]; +assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1]; always @(posedge s_axis_aclk) begin @@ -101,7 +101,7 @@ begin _m_axis_raddr_next <= _m_axis_raddr; end -assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[C_ADDRESS_WIDTH:1]; +assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1]; always @(posedge m_axis_aclk) begin @@ -115,7 +115,7 @@ begin end sync_bits #( - .NUM_BITS(C_ADDRESS_WIDTH + 1) + .NUM_OF_BITS(ADDRESS_WIDTH + 1) ) i_waddr_sync ( .out_clk(m_axis_aclk), .out_resetn(m_axis_aresetn), @@ -124,7 +124,7 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(C_ADDRESS_WIDTH + 1) + .NUM_OF_BITS(ADDRESS_WIDTH + 1) ) i_raddr_sync ( .out_clk(s_axis_aclk), .out_resetn(s_axis_aresetn), @@ -138,9 +138,9 @@ begin s_axis_ready <= 1'b1; s_axis_empty <= 1'b1; end else begin - s_axis_ready <= (s_axis_raddr_gray[C_ADDRESS_WIDTH] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH] || - s_axis_raddr_gray[C_ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH-1] || - s_axis_raddr_gray[C_ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[C_ADDRESS_WIDTH-2:0]); + s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] || + s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] || + s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]); s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next; end end diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v index 7637943e0..fb56c1ed6 100644 --- a/library/util_axis_fifo/address_gray_pipelined.v +++ b/library/util_axis_fifo/address_gray_pipelined.v @@ -41,32 +41,32 @@ module fifo_address_gray_pipelined ( input m_axis_aresetn, input m_axis_ready, output reg m_axis_valid, - output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next, - output [C_ADDRESS_WIDTH-1:0] m_axis_raddr, - output reg [C_ADDRESS_WIDTH:0] m_axis_level, + output [ADDRESS_WIDTH-1:0] m_axis_raddr_next, + output [ADDRESS_WIDTH-1:0] m_axis_raddr, + output reg [ADDRESS_WIDTH:0] m_axis_level, input s_axis_aclk, input s_axis_aresetn, output reg s_axis_ready, input s_axis_valid, output reg s_axis_empty, - output [C_ADDRESS_WIDTH-1:0] s_axis_waddr, - output reg [C_ADDRESS_WIDTH:0] s_axis_room + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room ); -parameter C_ADDRESS_WIDTH = 4; +parameter ADDRESS_WIDTH = 4; -reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; -reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next; -wire [C_ADDRESS_WIDTH:0] _s_axis_raddr; +reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; +reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; +wire [ADDRESS_WIDTH:0] _s_axis_raddr; -reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; -reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next; -wire [C_ADDRESS_WIDTH:0] _m_axis_waddr; +reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; +reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; +wire [ADDRESS_WIDTH:0] _m_axis_waddr; -assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0]; -assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0]; -assign m_axis_raddr = _m_axis_raddr[C_ADDRESS_WIDTH-1:0]; +assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; +assign m_axis_raddr_next = _m_axis_raddr_next[ADDRESS_WIDTH-1:0]; +assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0]; always @(*) begin @@ -103,7 +103,7 @@ begin end sync_gray #( - .DATA_WIDTH(C_ADDRESS_WIDTH + 1) + .DATA_WIDTH(ADDRESS_WIDTH + 1) ) i_waddr_sync ( .in_clk(s_axis_aclk), .in_resetn(s_axis_aresetn), @@ -114,7 +114,7 @@ sync_gray #( ); sync_gray #( - .DATA_WIDTH(C_ADDRESS_WIDTH + 1) + .DATA_WIDTH(ADDRESS_WIDTH + 1) ) i_raddr_sync ( .in_clk(m_axis_aclk), .in_resetn(m_axis_aresetn), @@ -129,12 +129,12 @@ begin if (s_axis_aresetn == 1'b0) begin s_axis_ready <= 1'b1; s_axis_empty <= 1'b1; - s_axis_room <= 2**C_ADDRESS_WIDTH; + s_axis_room <= 2**ADDRESS_WIDTH; end else begin - s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] || - _s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]); + s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] || + _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]); s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next; - s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**C_ADDRESS_WIDTH; + s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH; end end diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v index 47ecd9a27..e1594efc1 100644 --- a/library/util_axis_fifo/address_sync.v +++ b/library/util_axis_fifo/address_sync.v @@ -42,22 +42,22 @@ module fifo_address_sync ( input m_axis_ready, output reg m_axis_valid, - output reg [C_ADDRESS_WIDTH-1:0] m_axis_raddr, - output reg [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next, - output [C_ADDRESS_WIDTH:0] m_axis_level, + output reg [ADDRESS_WIDTH-1:0] m_axis_raddr, + output reg [ADDRESS_WIDTH-1:0] m_axis_raddr_next, + output [ADDRESS_WIDTH:0] m_axis_level, output reg s_axis_ready, input s_axis_valid, output reg s_axis_empty, - output reg [C_ADDRESS_WIDTH-1:0] s_axis_waddr, - output [C_ADDRESS_WIDTH:0] s_axis_room + output reg [ADDRESS_WIDTH-1:0] s_axis_waddr, + output [ADDRESS_WIDTH:0] s_axis_room ); -parameter C_ADDRESS_WIDTH = 4; +parameter ADDRESS_WIDTH = 4; -reg [C_ADDRESS_WIDTH:0] room = 2**C_ADDRESS_WIDTH; -reg [C_ADDRESS_WIDTH:0] level = 'h00; -reg [C_ADDRESS_WIDTH:0] level_next; +reg [ADDRESS_WIDTH:0] room = 2**ADDRESS_WIDTH; +reg [ADDRESS_WIDTH:0] level = 'h00; +reg [ADDRESS_WIDTH:0] level_next; assign s_axis_room = room; assign m_axis_level = level; @@ -101,13 +101,13 @@ begin m_axis_valid <= 1'b0; s_axis_ready <= 1'b0; level <= 'h00; - room <= 2**C_ADDRESS_WIDTH; + room <= 2**ADDRESS_WIDTH; s_axis_empty <= 'h00; end else begin level <= level_next; - room <= 2**C_ADDRESS_WIDTH - level_next; + room <= 2**ADDRESS_WIDTH - level_next; m_axis_valid <= level_next != 0; - s_axis_ready <= level_next != 2**C_ADDRESS_WIDTH; + s_axis_ready <= level_next != 2**ADDRESS_WIDTH; s_axis_empty <= level_next == 0; end end diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v index 9b209dba7..8b30190d8 100644 --- a/library/util_axis_fifo/util_axis_fifo.v +++ b/library/util_axis_fifo/util_axis_fifo.v @@ -41,26 +41,26 @@ module util_axis_fifo ( input m_axis_aresetn, input m_axis_ready, output m_axis_valid, - output [C_DATA_WIDTH-1:0] m_axis_data, - output [C_ADDRESS_WIDTH:0] m_axis_level, + output [DATA_WIDTH-1:0] m_axis_data, + output [ADDRESS_WIDTH:0] m_axis_level, input s_axis_aclk, input s_axis_aresetn, output s_axis_ready, input s_axis_valid, - input [C_DATA_WIDTH-1:0] s_axis_data, + input [DATA_WIDTH-1:0] s_axis_data, output s_axis_empty, - output [C_ADDRESS_WIDTH:0] s_axis_room + output [ADDRESS_WIDTH:0] s_axis_room ); -parameter C_DATA_WIDTH = 64; -parameter C_CLKS_ASYNC = 1; -parameter C_ADDRESS_WIDTH = 4; -parameter C_S_AXIS_REGISTERED = 1; +parameter DATA_WIDTH = 64; +parameter ASYNC_CLK = 1; +parameter ADDRESS_WIDTH = 4; +parameter S_AXIS_REGISTERED = 1; -generate if (C_ADDRESS_WIDTH == 0) begin +generate if (ADDRESS_WIDTH == 0) begin -reg [C_DATA_WIDTH-1:0] cdc_sync_fifo_ram; +reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; reg s_axis_waddr = 1'b0; reg m_axis_raddr = 1'b0; @@ -68,8 +68,8 @@ wire m_axis_waddr; wire s_axis_raddr; sync_bits #( - .NUM_BITS(1), - .CLK_ASYNC(C_CLKS_ASYNC) + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) ) i_waddr_sync ( .out_clk(m_axis_aclk), .out_resetn(m_axis_aresetn), @@ -78,8 +78,8 @@ sync_bits #( ); sync_bits #( - .NUM_BITS(1), - .CLK_ASYNC(C_CLKS_ASYNC) + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) ) i_raddr_sync ( .out_clk(s_axis_aclk), .out_resetn(s_axis_aresetn), @@ -121,17 +121,17 @@ assign m_axis_data = cdc_sync_fifo_ram; end else begin -reg [C_DATA_WIDTH-1:0] ram[0:2**C_ADDRESS_WIDTH-1]; +reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1]; -wire [C_ADDRESS_WIDTH-1:0] s_axis_waddr; -wire [C_ADDRESS_WIDTH-1:0] m_axis_raddr; +wire [ADDRESS_WIDTH-1:0] s_axis_waddr; +wire [ADDRESS_WIDTH-1:0] m_axis_raddr; wire _m_axis_ready; wire _m_axis_valid; -if (C_CLKS_ASYNC == 1) begin +if (ASYNC_CLK == 1) begin fifo_address_gray_pipelined #( - .C_ADDRESS_WIDTH(C_ADDRESS_WIDTH) + .ADDRESS_WIDTH(ADDRESS_WIDTH) ) i_address_gray ( .m_axis_aclk(m_axis_aclk), .m_axis_aresetn(m_axis_aresetn), @@ -152,7 +152,7 @@ fifo_address_gray_pipelined #( end else begin fifo_address_sync #( - .C_ADDRESS_WIDTH(C_ADDRESS_WIDTH) + .ADDRESS_WIDTH(ADDRESS_WIDTH) ) i_address_sync ( .clk(m_axis_aclk), .resetn(m_axis_aresetn), @@ -175,9 +175,9 @@ always @(posedge s_axis_aclk) begin ram[s_axis_waddr] <= s_axis_data; end -if (C_S_AXIS_REGISTERED == 1) begin +if (S_AXIS_REGISTERED == 1) begin -reg [C_DATA_WIDTH-1:0] data; +reg [DATA_WIDTH-1:0] data; reg valid; always @(posedge m_axis_aclk) begin diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v index 15e2293ee..13a6e5634 100644 --- a/library/util_axis_resize/util_axis_resize.v +++ b/library/util_axis_resize/util_axis_resize.v @@ -42,28 +42,28 @@ module util_axis_resize ( input s_valid, output s_ready, - input [C_S_DATA_WIDTH-1:0] s_data, + input [SLAVE_DATA_WIDTH-1:0] s_data, output m_valid, input m_ready, - output [C_M_DATA_WIDTH-1:0] m_data + output [MASTER_DATA_WIDTH-1:0] m_data ); -parameter C_M_DATA_WIDTH = 64; -parameter C_S_DATA_WIDTH = 64; -parameter C_BIG_ENDIAN = 0; +parameter MASTER_DATA_WIDTH = 64; +parameter SLAVE_DATA_WIDTH = 64; +parameter BIG_ENDIAN = 0; -generate if (C_S_DATA_WIDTH == C_M_DATA_WIDTH) begin +generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin assign m_valid = s_valid; assign s_ready = m_ready; assign m_data = s_data; -end else if (C_S_DATA_WIDTH < C_M_DATA_WIDTH) begin +end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin -localparam RATIO = C_M_DATA_WIDTH / C_S_DATA_WIDTH; +localparam RATIO = MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH; -reg [C_M_DATA_WIDTH-1:0] data; +reg [MASTER_DATA_WIDTH-1:0] data; reg [$clog2(RATIO)-1:0] count; reg valid; @@ -90,10 +90,10 @@ end always @(posedge clk) begin if (s_ready == 1'b1 && s_valid == 1'b1) - if (C_BIG_ENDIAN == 1) begin - data <= {data[C_M_DATA_WIDTH-C_S_DATA_WIDTH-1:0], s_data}; + if (BIG_ENDIAN == 1) begin + data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data}; end else begin - data <= {s_data, data[C_M_DATA_WIDTH-1:C_S_DATA_WIDTH]}; + data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]}; end end @@ -103,9 +103,9 @@ assign m_data = data; end else begin -localparam RATIO = C_S_DATA_WIDTH / C_M_DATA_WIDTH; +localparam RATIO = SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH; -reg [C_S_DATA_WIDTH-1:0] data; +reg [SLAVE_DATA_WIDTH-1:0] data; reg [$clog2(RATIO)-1:0] count; reg valid; @@ -134,19 +134,19 @@ begin if (s_ready == 1'b1 && s_valid == 1'b1) begin data <= s_data; end else if (m_ready == 1'b1 && m_valid == 1'b1) begin - if (C_BIG_ENDIAN == 1) begin - data[C_S_DATA_WIDTH-1:C_M_DATA_WIDTH] <= data[C_S_DATA_WIDTH-C_M_DATA_WIDTH-1:0]; + if (BIG_ENDIAN == 1) begin + data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0]; end else begin - data[C_S_DATA_WIDTH-C_M_DATA_WIDTH-1:0] <= data[C_S_DATA_WIDTH-1:C_M_DATA_WIDTH]; + data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH]; end end end assign s_ready = ~valid || (m_ready && count == 'h0); assign m_valid = valid; -assign m_data = C_BIG_ENDIAN == 1 ? - data[C_S_DATA_WIDTH-1:C_S_DATA_WIDTH-C_M_DATA_WIDTH] : - data[C_M_DATA_WIDTH-1:0]; +assign m_data = BIG_ENDIAN == 1 ? + data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] : + data[MASTER_DATA_WIDTH-1:0]; end endgenerate diff --git a/library/util_bsplit/util_bsplit.v b/library/util_bsplit/util_bsplit.v index c0723dcee..ac97588da 100755 --- a/library/util_bsplit/util_bsplit.v +++ b/library/util_bsplit/util_bsplit.v @@ -53,39 +53,39 @@ module util_bsplit ( // parameters - parameter CH_DW = 1; - parameter CH_CNT = 8; - localparam CH_MCNT = 9; + parameter CHANNEL_DATA_WIDTH = 1; + parameter NUM_OF_CHANNELS = 8; + localparam NUM_OF_CHANNELS_M = 9; // interface - input [((CH_CNT*CH_DW)-1):0] data; - output [(CH_DW-1):0] split_data_0; - output [(CH_DW-1):0] split_data_1; - output [(CH_DW-1):0] split_data_2; - output [(CH_DW-1):0] split_data_3; - output [(CH_DW-1):0] split_data_4; - output [(CH_DW-1):0] split_data_5; - output [(CH_DW-1):0] split_data_6; - output [(CH_DW-1):0] split_data_7; + input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] data; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_0; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_1; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_2; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_3; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_4; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_5; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_6; + output [(CHANNEL_DATA_WIDTH-1):0] split_data_7; // internal signals - wire [((CH_MCNT*CH_DW)-1):0] data_s; + wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s; // extend and split - assign data_s[((CH_MCNT*CH_DW)-1):(CH_CNT*CH_DW)] = 'd0; - assign data_s[((CH_CNT*CH_DW)-1):0] = data; + assign data_s[((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):(NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)] = 'd0; + assign data_s[((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] = data; - assign split_data_0 = data_s[((CH_DW*1)-1):(CH_DW*0)]; - assign split_data_1 = data_s[((CH_DW*2)-1):(CH_DW*1)]; - assign split_data_2 = data_s[((CH_DW*3)-1):(CH_DW*2)]; - assign split_data_3 = data_s[((CH_DW*4)-1):(CH_DW*3)]; - assign split_data_4 = data_s[((CH_DW*5)-1):(CH_DW*4)]; - assign split_data_5 = data_s[((CH_DW*6)-1):(CH_DW*5)]; - assign split_data_6 = data_s[((CH_DW*7)-1):(CH_DW*6)]; - assign split_data_7 = data_s[((CH_DW*8)-1):(CH_DW*7)]; + assign split_data_0 = data_s[((CHANNEL_DATA_WIDTH*1)-1):(CHANNEL_DATA_WIDTH*0)]; + assign split_data_1 = data_s[((CHANNEL_DATA_WIDTH*2)-1):(CHANNEL_DATA_WIDTH*1)]; + assign split_data_2 = data_s[((CHANNEL_DATA_WIDTH*3)-1):(CHANNEL_DATA_WIDTH*2)]; + assign split_data_3 = data_s[((CHANNEL_DATA_WIDTH*4)-1):(CHANNEL_DATA_WIDTH*3)]; + assign split_data_4 = data_s[((CHANNEL_DATA_WIDTH*5)-1):(CHANNEL_DATA_WIDTH*4)]; + assign split_data_5 = data_s[((CHANNEL_DATA_WIDTH*6)-1):(CHANNEL_DATA_WIDTH*5)]; + assign split_data_6 = data_s[((CHANNEL_DATA_WIDTH*7)-1):(CHANNEL_DATA_WIDTH*6)]; + assign split_data_7 = data_s[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]; endmodule diff --git a/library/util_bsplit/util_bsplit_hw.tcl b/library/util_bsplit/util_bsplit_hw.tcl index 3823b27bd..ad0aa342a 100755 --- a/library/util_bsplit/util_bsplit_hw.tcl +++ b/library/util_bsplit/util_bsplit_hw.tcl @@ -20,50 +20,50 @@ add_fileset_file util_bsplit.v VERILOG PATH util_bsplit.v TOP_LEVEL_FILE # parameters -add_parameter CH_DW INTEGER 0 -set_parameter_property CH_DW DEFAULT_VALUE 32 -set_parameter_property CH_DW DISPLAY_NAME CH_DW -set_parameter_property CH_DW TYPE INTEGER -set_parameter_property CH_DW UNITS None -set_parameter_property CH_DW HDL_PARAMETER true +add_parameter CHANNEL_DATA_WIDTH INTEGER 0 +set_parameter_property CHANNEL_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property CHANNEL_DATA_WIDTH DISPLAY_NAME CHANNEL_DATA_WIDTH +set_parameter_property CHANNEL_DATA_WIDTH TYPE INTEGER +set_parameter_property CHANNEL_DATA_WIDTH UNITS None +set_parameter_property CHANNEL_DATA_WIDTH HDL_PARAMETER true -add_parameter CH_CNT INTEGER 0 -set_parameter_property CH_CNT DEFAULT_VALUE 8 -set_parameter_property CH_CNT DISPLAY_NAME CH_CNT -set_parameter_property CH_CNT TYPE INTEGER -set_parameter_property CH_CNT UNITS None -set_parameter_property CH_CNT HDL_PARAMETER true +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # avalon streaming -ad_alt_intf signal data input CH_CNT*CH_DW -ad_alt_intf signal split_data_0 output CH_DW data +ad_alt_intf signal data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH +ad_alt_intf signal split_data_0 output CHANNEL_DATA_WIDTH data proc p_util_bsplit {} { - set p_ch_cnt [get_parameter_value "CH_CNT"] - set p_ch_dw [get_parameter_value "CH_DW"] + set p_ch_cnt [get_parameter_value "NUM_OF_CHANNELS"] + set p_ch_dw [get_parameter_value "CHANNEL_DATA_WIDTH"] - if {[get_parameter_value CH_CNT] > 1} { - ad_alt_intf signal split_data_1 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { + ad_alt_intf signal split_data_1 output CHANNEL_DATA_WIDTH data } - if {[get_parameter_value CH_CNT] > 2} { - ad_alt_intf signal split_data_2 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { + ad_alt_intf signal split_data_2 output CHANNEL_DATA_WIDTH data } - if {[get_parameter_value CH_CNT] > 3} { - ad_alt_intf signal split_data_3 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { + ad_alt_intf signal split_data_3 output CHANNEL_DATA_WIDTH data } - if {[get_parameter_value CH_CNT] > 4} { - ad_alt_intf signal split_data_4 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { + ad_alt_intf signal split_data_4 output CHANNEL_DATA_WIDTH data } - if {[get_parameter_value CH_CNT] > 5} { - ad_alt_intf signal split_data_5 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { + ad_alt_intf signal split_data_5 output CHANNEL_DATA_WIDTH data } - if {[get_parameter_value CH_CNT] > 6} { - ad_alt_intf signal split_data_6 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { + ad_alt_intf signal split_data_6 output CHANNEL_DATA_WIDTH data } - if {[get_parameter_value CH_CNT] > 7} { - ad_alt_intf signal split_data_7 output CH_DW data + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { + ad_alt_intf signal split_data_7 output CHANNEL_DATA_WIDTH data } } diff --git a/library/util_bsplit/util_bsplit_ip.tcl b/library/util_bsplit/util_bsplit_ip.tcl index 8b22055b1..5791f5948 100644 --- a/library/util_bsplit/util_bsplit_ip.tcl +++ b/library/util_bsplit/util_bsplit_ip.tcl @@ -12,31 +12,31 @@ adi_ip_properties_lite util_bsplit adi_ip_constraints util_bsplit [list \ "util_bsplit_constr.xdc" ] -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 1}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ [ipx::get_port split_data_1 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 2}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ [ipx::get_port split_data_2 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 3}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ [ipx::get_port split_data_3 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 4}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ [ipx::get_port split_data_4 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 5}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ [ipx::get_port split_data_5 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 6}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ [ipx::get_port split_data_6 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 7}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ [ipx::get_port split_data_7 [ipx::current_core]] \ diff --git a/library/util_ccat/util_ccat.v b/library/util_ccat/util_ccat.v index 4f17b9407..b0e4d2810 100755 --- a/library/util_ccat/util_ccat.v +++ b/library/util_ccat/util_ccat.v @@ -53,38 +53,38 @@ module util_ccat ( // parameters - parameter CH_DW = 1; - parameter CH_CNT = 8; - localparam CH_MCNT = 8; + parameter CHANNEL_DATA_WIDTH = 1; + parameter NUM_OF_CHANNELS = 8; + localparam NUM_OF_CHANNELS_M = 8; // interface - input [(CH_DW-1):0] data_0; - input [(CH_DW-1):0] data_1; - input [(CH_DW-1):0] data_2; - input [(CH_DW-1):0] data_3; - input [(CH_DW-1):0] data_4; - input [(CH_DW-1):0] data_5; - input [(CH_DW-1):0] data_6; - input [(CH_DW-1):0] data_7; - output [((CH_CNT*CH_DW)-1):0] ccat_data; + input [(CHANNEL_DATA_WIDTH-1):0] data_0; + input [(CHANNEL_DATA_WIDTH-1):0] data_1; + input [(CHANNEL_DATA_WIDTH-1):0] data_2; + input [(CHANNEL_DATA_WIDTH-1):0] data_3; + input [(CHANNEL_DATA_WIDTH-1):0] data_4; + input [(CHANNEL_DATA_WIDTH-1):0] data_5; + input [(CHANNEL_DATA_WIDTH-1):0] data_6; + input [(CHANNEL_DATA_WIDTH-1):0] data_7; + output [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] ccat_data; // internal signals - wire [((CH_MCNT*CH_DW)-1):0] data_s; + wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s; // concatenate - assign data_s[((CH_DW*1)-1):(CH_DW*0)] = data_0; - assign data_s[((CH_DW*2)-1):(CH_DW*1)] = data_1; - assign data_s[((CH_DW*3)-1):(CH_DW*2)] = data_2; - assign data_s[((CH_DW*4)-1):(CH_DW*3)] = data_3; - assign data_s[((CH_DW*5)-1):(CH_DW*4)] = data_4; - assign data_s[((CH_DW*6)-1):(CH_DW*5)] = data_5; - assign data_s[((CH_DW*7)-1):(CH_DW*6)] = data_6; - assign data_s[((CH_DW*8)-1):(CH_DW*7)] = data_7; + assign data_s[((CHANNEL_DATA_WIDTH*1)-1):(CHANNEL_DATA_WIDTH*0)] = data_0; + assign data_s[((CHANNEL_DATA_WIDTH*2)-1):(CHANNEL_DATA_WIDTH*1)] = data_1; + assign data_s[((CHANNEL_DATA_WIDTH*3)-1):(CHANNEL_DATA_WIDTH*2)] = data_2; + assign data_s[((CHANNEL_DATA_WIDTH*4)-1):(CHANNEL_DATA_WIDTH*3)] = data_3; + assign data_s[((CHANNEL_DATA_WIDTH*5)-1):(CHANNEL_DATA_WIDTH*4)] = data_4; + assign data_s[((CHANNEL_DATA_WIDTH*6)-1):(CHANNEL_DATA_WIDTH*5)] = data_5; + assign data_s[((CHANNEL_DATA_WIDTH*7)-1):(CHANNEL_DATA_WIDTH*6)] = data_6; + assign data_s[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)] = data_7; - assign ccat_data = data_s[((CH_CNT*CH_DW)-1):0]; + assign ccat_data = data_s[((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0]; endmodule diff --git a/library/util_ccat/util_ccat_ip.tcl b/library/util_ccat/util_ccat_ip.tcl index a54067bef..eb326e84c 100644 --- a/library/util_ccat/util_ccat_ip.tcl +++ b/library/util_ccat/util_ccat_ip.tcl @@ -12,31 +12,31 @@ adi_ip_properties_lite util_ccat adi_ip_constraints util_ccat [list \ "util_ccat_constr.xdc" ] -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 1}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ [ipx::get_port data_1 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 2}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ [ipx::get_port data_2 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 3}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ [ipx::get_port data_3 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 4}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ [ipx::get_port data_4 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 5}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ [ipx::get_port data_5 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 6}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ [ipx::get_port data_6 [ipx::current_core]] \ -set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 7}} \ +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ [ipx::get_port data_7 [ipx::current_core]] \ diff --git a/library/util_cpack/util_cpack.v b/library/util_cpack/util_cpack.v index 0743a77b4..a772ee20b 100755 --- a/library/util_cpack/util_cpack.v +++ b/library/util_cpack/util_cpack.v @@ -76,13 +76,13 @@ module util_cpack ( // parameters - parameter CH_DW = 32; - parameter CH_CNT = 8; + parameter CHANNEL_DATA_WIDTH = 32; + parameter NUM_OF_CHANNELS = 8; - localparam CH_SCNT = CH_DW/16; - localparam CH_MCNT = 8; - localparam P_DW = CH_CNT*CH_DW; - localparam P_CNT = CH_CNT; + localparam CH_SCNT = CHANNEL_DATA_WIDTH/16; + localparam NUM_OF_CHANNELS_M = 8; + localparam P_DW = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH; + localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS; localparam P_SCNT = P_DW/16; // adc interface @@ -91,52 +91,52 @@ module util_cpack ( input adc_clk; input adc_enable_0; input adc_valid_0; - input [(CH_DW-1):0] adc_data_0; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_0; input adc_enable_1; input adc_valid_1; - input [(CH_DW-1):0] adc_data_1; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_1; input adc_enable_2; input adc_valid_2; - input [(CH_DW-1):0] adc_data_2; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_2; input adc_enable_3; input adc_valid_3; - input [(CH_DW-1):0] adc_data_3; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_3; input adc_enable_4; input adc_valid_4; - input [(CH_DW-1):0] adc_data_4; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_4; input adc_enable_5; input adc_valid_5; - input [(CH_DW-1):0] adc_data_5; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_5; input adc_enable_6; input adc_valid_6; - input [(CH_DW-1):0] adc_data_6; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_6; input adc_enable_7; input adc_valid_7; - input [(CH_DW-1):0] adc_data_7; + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_7; // fifo interface output adc_valid; output adc_sync; - output [((CH_CNT*CH_DW)-1):0] adc_data; + output [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data; // internal registers reg adc_valid_d = 'd0; - reg [((CH_MCNT*CH_DW)-1):0] adc_data_d = 'd0; + reg [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_d = 'd0; reg adc_mux_valid = 'd0; - reg [(CH_MCNT-1):0] adc_mux_enable = 'd0; + reg [(NUM_OF_CHANNELS_M-1):0] adc_mux_enable = 'd0; reg [((CH_SCNT*16*79)-1):0] adc_mux_data = 'd0; reg adc_valid = 'd0; reg adc_sync = 'd0; - reg [((CH_CNT*CH_DW)-1):0] adc_data = 'd0; + reg [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data = 'd0; // internal signals - wire [(CH_MCNT-1):0] adc_enable_s; - wire [(CH_MCNT-1):0] adc_valid_s; - wire [((CH_MCNT*CH_DW)-1):0] adc_data_s; - wire [((CH_MCNT*CH_DW)-1):0] adc_data_intlv_s; + wire [(NUM_OF_CHANNELS_M-1):0] adc_enable_s; + wire [(NUM_OF_CHANNELS_M-1):0] adc_valid_s; + wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_s; + wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_intlv_s; wire [(CH_SCNT-1):0] adc_mux_valid_s; wire [(CH_SCNT-1):0] adc_mux_enable_0_s; wire [(CH_SCNT-1):0] adc_mux_enable_1_s; @@ -154,9 +154,9 @@ module util_cpack ( wire [((CH_SCNT*16*6)-1):0] adc_mux_data_5_s; wire [((CH_SCNT*16*7)-1):0] adc_mux_data_6_s; wire [((CH_SCNT*16*8)-1):0] adc_mux_data_7_s; - wire [(CH_MCNT-1):0] adc_dsf_valid_s; - wire [(CH_MCNT-1):0] adc_dsf_sync_s; - wire [(P_DW-1):0] adc_dsf_data_s[(CH_MCNT-1):0]; + wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_valid_s; + wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_sync_s; + wire [(P_DW-1):0] adc_dsf_data_s[(NUM_OF_CHANNELS_M-1):0]; // loop variables @@ -184,13 +184,13 @@ module util_cpack ( // mw requires unused to be zero generate - for (n = 0; n < CH_MCNT; n = n + 1) begin: g_in + for (n = 0; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_in always @(posedge adc_clk) begin if ((adc_rst == 1'b1) && (adc_enable_s[n] == 1'b0)) begin - adc_data_d[((CH_DW*(n+1))-1):(CH_DW*n)] <= 'd0; + adc_data_d[((CHANNEL_DATA_WIDTH*(n+1))-1):(CHANNEL_DATA_WIDTH*n)] <= 'd0; end else if (adc_valid_s[n] == 1'b1) begin - adc_data_d[((CH_DW*(n+1))-1):(CH_DW*n)] <= - adc_data_s[((CH_DW*(n+1))-1):(CH_DW*n)]; + adc_data_d[((CHANNEL_DATA_WIDTH*(n+1))-1):(CHANNEL_DATA_WIDTH*n)] <= + adc_data_s[((CHANNEL_DATA_WIDTH*(n+1))-1):(CHANNEL_DATA_WIDTH*n)]; end end end @@ -200,15 +200,15 @@ module util_cpack ( generate for (n = 0; n < CH_SCNT; n = n + 1) begin: g_intlv - assign adc_data_intlv_s[((16*CH_MCNT*(n+1))-1):(16*CH_MCNT*n)] = - { adc_data_d[(((CH_DW*7)+(16*(n+1)))-1):((CH_DW*7)+(16*n))], - adc_data_d[(((CH_DW*6)+(16*(n+1)))-1):((CH_DW*6)+(16*n))], - adc_data_d[(((CH_DW*5)+(16*(n+1)))-1):((CH_DW*5)+(16*n))], - adc_data_d[(((CH_DW*4)+(16*(n+1)))-1):((CH_DW*4)+(16*n))], - adc_data_d[(((CH_DW*3)+(16*(n+1)))-1):((CH_DW*3)+(16*n))], - adc_data_d[(((CH_DW*2)+(16*(n+1)))-1):((CH_DW*2)+(16*n))], - adc_data_d[(((CH_DW*1)+(16*(n+1)))-1):((CH_DW*1)+(16*n))], - adc_data_d[(((CH_DW*0)+(16*(n+1)))-1):((CH_DW*0)+(16*n))]}; + assign adc_data_intlv_s[((16*NUM_OF_CHANNELS_M*(n+1))-1):(16*NUM_OF_CHANNELS_M*n)] = + { adc_data_d[(((CHANNEL_DATA_WIDTH*7)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*7)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*6)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*6)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*5)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*5)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*4)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*4)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*3)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*3)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*2)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*2)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*1)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*1)+(16*n))], + adc_data_d[(((CHANNEL_DATA_WIDTH*0)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*0)+(16*n))]}; end endgenerate @@ -220,7 +220,7 @@ module util_cpack ( .adc_clk (adc_clk), .adc_valid (adc_valid_d), .adc_enable (adc_enable_s), - .adc_data (adc_data_intlv_s[((16*CH_MCNT*(n+1))-1):(16*CH_MCNT*n)]), + .adc_data (adc_data_intlv_s[((16*NUM_OF_CHANNELS_M*(n+1))-1):(16*NUM_OF_CHANNELS_M*n)]), .adc_mux_valid (adc_mux_valid_s[n]), .adc_mux_enable_0 (adc_mux_enable_0_s[n]), .adc_mux_data_0 (adc_mux_data_0_s[(((n+1)*16*1)-1):(n*16*1)]), @@ -274,12 +274,12 @@ module util_cpack ( // store & fwd generate - for (n = 0; n < P_CNT; n = n + 1) begin: g_dsf + for (n = 0; n < NUM_OF_CHANNELS_P; n = n + 1) begin: g_dsf util_cpack_dsf #( - .CH_MCNT (CH_MCNT), - .P_CNT (P_CNT), - .CH_DW (CH_DW), - .CH_ICNT ((n+1))) + .NUM_OF_CHANNELS_M (NUM_OF_CHANNELS_M), + .NUM_OF_CHANNELS_P (NUM_OF_CHANNELS_P), + .CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH), + .NUM_OF_CHANNELS_I ((n+1))) i_dsf ( .adc_clk (adc_clk), .adc_valid (adc_mux_valid), @@ -292,8 +292,8 @@ module util_cpack ( endgenerate generate - if (CH_MCNT > P_CNT) begin - for (n = P_CNT; n < CH_MCNT; n = n + 1) begin: g_def + if (NUM_OF_CHANNELS_M > NUM_OF_CHANNELS_P) begin + for (n = NUM_OF_CHANNELS_P; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_def assign adc_dsf_valid_s[n] = 'd0; assign adc_dsf_sync_s[n] = 'd0; assign adc_dsf_data_s[n] = 'd0; diff --git a/library/util_cpack/util_cpack_dsf.v b/library/util_cpack/util_cpack_dsf.v index aec94e9fa..b1f99ed25 100755 --- a/library/util_cpack/util_cpack_dsf.v +++ b/library/util_cpack/util_cpack_dsf.v @@ -54,15 +54,15 @@ module util_cpack_dsf ( // parameters - parameter CH_DW = 32; - parameter CH_ICNT = 4; - parameter CH_MCNT = 8; - parameter P_CNT = 4; + parameter CHANNEL_DATA_WIDTH = 32; + parameter NUM_OF_CHANNELS_I = 4; + parameter NUM_OF_CHANNELS_M = 8; + parameter NUM_OF_CHANNELS_P = 4; - localparam CH_DCNT = P_CNT - CH_ICNT; - localparam I_WIDTH = CH_DW*CH_ICNT; - localparam P_WIDTH = CH_DW*P_CNT; - localparam M_WIDTH = CH_DW*CH_MCNT; + localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_I; + localparam I_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_I; + localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; + localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; // adc interface @@ -96,7 +96,7 @@ module util_cpack_dsf ( // bypass generate - if (CH_ICNT == P_CNT) begin + if (NUM_OF_CHANNELS_I == NUM_OF_CHANNELS_P) begin assign adc_data_s = 'd0; always @(posedge adc_clk) begin @@ -122,7 +122,7 @@ module util_cpack_dsf ( // data store & forward generate - if (P_CNT > CH_ICNT) begin + if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_I) begin assign adc_data_s[(M_WIDTH-1):I_WIDTH] = 'd0; assign adc_data_s[(I_WIDTH-1):0] = adc_data; @@ -131,7 +131,7 @@ module util_cpack_dsf ( if (adc_samples_int >= CH_DCNT) begin adc_samples_int <= adc_samples_int - CH_DCNT; end else begin - adc_samples_int <= adc_samples_int + CH_ICNT; + adc_samples_int <= adc_samples_int + NUM_OF_CHANNELS_I; end adc_data_int <= {adc_data_s[(I_WIDTH-1):0], adc_data_int[(M_WIDTH-1):I_WIDTH]}; @@ -159,20 +159,20 @@ module util_cpack_dsf ( always @(posedge adc_clk) begin if (adc_valid == 1'b1) begin case (adc_samples_int) - 3'b111: adc_dsf_data_int <= {adc_data_s[((CH_DW*1)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*1)]}; - 3'b110: adc_dsf_data_int <= {adc_data_s[((CH_DW*2)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*2)]}; - 3'b101: adc_dsf_data_int <= {adc_data_s[((CH_DW*3)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*3)]}; - 3'b100: adc_dsf_data_int <= {adc_data_s[((CH_DW*4)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*4)]}; - 3'b011: adc_dsf_data_int <= {adc_data_s[((CH_DW*5)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*5)]}; - 3'b010: adc_dsf_data_int <= {adc_data_s[((CH_DW*6)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*6)]}; - 3'b001: adc_dsf_data_int <= {adc_data_s[((CH_DW*7)-1):0], - adc_data_int[((CH_DW*8)-1):(CH_DW*7)]}; + 3'b111: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*1)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*1)]}; + 3'b110: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*2)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*2)]}; + 3'b101: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*3)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*3)]}; + 3'b100: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*4)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*4)]}; + 3'b011: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*5)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*5)]}; + 3'b010: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*6)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*6)]}; + 3'b001: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*7)-1):0], + adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]}; 3'b000: adc_dsf_data_int <= adc_data_s; default: adc_dsf_data_int <= 'd0; endcase diff --git a/library/util_cpack/util_cpack_hw.tcl b/library/util_cpack/util_cpack_hw.tcl index 74554576e..5cd74a2bb 100755 --- a/library/util_cpack/util_cpack_hw.tcl +++ b/library/util_cpack/util_cpack_hw.tcl @@ -22,29 +22,29 @@ add_fileset_file util_cpack.v VERILOG PATH util_cpack.v TOP_LEVEL_FILE # parameters -add_parameter CH_DW INTEGER 0 -set_parameter_property CH_DW DEFAULT_VALUE 32 -set_parameter_property CH_DW DISPLAY_NAME CH_DW -set_parameter_property CH_DW TYPE INTEGER -set_parameter_property CH_DW UNITS None -set_parameter_property CH_DW HDL_PARAMETER true +add_parameter CHANNEL_DATA_WIDTH INTEGER 0 +set_parameter_property CHANNEL_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property CHANNEL_DATA_WIDTH DISPLAY_NAME CHANNEL_DATA_WIDTH +set_parameter_property CHANNEL_DATA_WIDTH TYPE INTEGER +set_parameter_property CHANNEL_DATA_WIDTH UNITS None +set_parameter_property CHANNEL_DATA_WIDTH HDL_PARAMETER true -add_parameter CH_CNT INTEGER 0 -set_parameter_property CH_CNT DEFAULT_VALUE 8 -set_parameter_property CH_CNT DISPLAY_NAME CH_CNT -set_parameter_property CH_CNT TYPE INTEGER -set_parameter_property CH_CNT UNITS None -set_parameter_property CH_CNT HDL_PARAMETER true +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # defaults ad_alt_intf clock adc_clk input 1 ad_alt_intf signal adc_valid output 1 ad_alt_intf signal adc_sync output 1 -ad_alt_intf signal adc_data output CH_CNT*CH_DW +ad_alt_intf signal adc_data output NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH ad_alt_intf signal adc_valid_0 input 1 ad_alt_intf signal adc_enable_0 input 1 -ad_alt_intf signal adc_data_0 input CH_DW +ad_alt_intf signal adc_data_0 input CHANNEL_DATA_WIDTH add_interface adc_reset reset end set_interface_property adc_reset associatedClock if_adc_clk @@ -52,40 +52,40 @@ add_interface_port adc_reset adc_rst reset Input 1 proc p_util_cpack {} { - if {[get_parameter_value CH_CNT] > 1} { + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { ad_alt_intf signal adc_valid_1 input 1 ad_alt_intf signal adc_enable_1 input 1 - ad_alt_intf signal adc_data_1 input CH_DW + ad_alt_intf signal adc_data_1 input CHANNEL_DATA_WIDTH } - if {[get_parameter_value CH_CNT] > 2} { + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { ad_alt_intf signal adc_valid_2 input 1 ad_alt_intf signal adc_enable_2 input 1 - ad_alt_intf signal adc_data_2 input CH_DW + ad_alt_intf signal adc_data_2 input CHANNEL_DATA_WIDTH } - if {[get_parameter_value CH_CNT] > 3} { + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { ad_alt_intf signal adc_valid_3 input 1 ad_alt_intf signal adc_enable_3 input 1 - ad_alt_intf signal adc_data_3 input CH_DW + ad_alt_intf signal adc_data_3 input CHANNEL_DATA_WIDTH } - if {[get_parameter_value CH_CNT] > 4} { + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { ad_alt_intf signal adc_valid_4 input 1 ad_alt_intf signal adc_enable_4 input 1 - ad_alt_intf signal adc_data_4 input CH_DW + ad_alt_intf signal adc_data_4 input CHANNEL_DATA_WIDTH } - if {[get_parameter_value CH_CNT] > 5} { + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { ad_alt_intf signal adc_valid_5 input 1 ad_alt_intf signal adc_enable_5 input 1 - ad_alt_intf signal adc_data_5 input CH_DW + ad_alt_intf signal adc_data_5 input CHANNEL_DATA_WIDTH } - if {[get_parameter_value CH_CNT] > 6} { + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { ad_alt_intf signal adc_valid_6 input 1 ad_alt_intf signal adc_enable_6 input 1 - ad_alt_intf signal adc_data_6 input CH_DW + ad_alt_intf signal adc_data_6 input CHANNEL_DATA_WIDTH } - if {[get_parameter_value CH_CNT] > 7} { + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { ad_alt_intf signal adc_valid_7 input 1 ad_alt_intf signal adc_enable_7 input 1 - ad_alt_intf signal adc_data_7 input CH_DW + ad_alt_intf signal adc_data_7 input CHANNEL_DATA_WIDTH } } diff --git a/library/util_cpack/util_cpack_ip.tcl b/library/util_cpack/util_cpack_ip.tcl index 83011527b..4314a976a 100644 --- a/library/util_cpack/util_cpack_ip.tcl +++ b/library/util_cpack/util_cpack_ip.tcl @@ -14,19 +14,19 @@ adi_ip_properties_lite util_cpack adi_ip_constraints util_cpack [list \ "util_cpack_constr.xdc" ] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 1} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ [ipx::get_ports *_1* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 2} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ [ipx::get_ports *_2* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 3} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ [ipx::get_ports *_3* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 4} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ [ipx::get_ports *_4* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 5} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ [ipx::get_ports *_5* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 6} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ [ipx::get_ports *_6* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 7} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ [ipx::get_ports *_7* -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core] diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v index 004700b55..bf2edbf3d 100644 --- a/library/util_dac_unpack/util_dac_unpack.v +++ b/library/util_dac_unpack/util_dac_unpack.v @@ -79,7 +79,7 @@ module util_dac_unpack ( dma_rd, dma_data); - parameter CHANNELS = 8; // valid values are 4 and 8 + parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8 parameter DATA_WIDTH = 16; input clk; @@ -118,25 +118,25 @@ module util_dac_unpack ( input fifo_valid; output dma_rd; - input [CHANNELS*DATA_WIDTH-1:0] dma_data; + input [NUM_OF_CHANNELS*DATA_WIDTH-1:0] dma_data; - localparam DMA_WIDTH = CHANNELS*DATA_WIDTH; + localparam DMA_DATA_WIDTH = NUM_OF_CHANNELS*DATA_WIDTH; - wire [CHANNELS-1:0] dac_enable; - wire [CHANNELS-1:0] dac_valid; + wire [NUM_OF_CHANNELS-1:0] dac_enable; + wire [NUM_OF_CHANNELS-1:0] dac_valid; - wire [DATA_WIDTH-1:0] data_array[0:CHANNELS-1]; + wire [DATA_WIDTH-1:0] data_array[0:NUM_OF_CHANNELS-1]; - wire [$clog2(CHANNELS)-1:0] offset [0:CHANNELS-1]; + wire [$clog2(NUM_OF_CHANNELS)-1:0] offset [0:NUM_OF_CHANNELS-1]; wire dac_chan_valid; - reg [DATA_WIDTH*CHANNELS-1:0] dac_data = 'h00; - reg [DMA_WIDTH-1:0] buffer = 'h00; + reg [DATA_WIDTH*NUM_OF_CHANNELS-1:0] dac_data = 'h00; + reg [DMA_DATA_WIDTH-1:0] buffer = 'h00; reg dma_rd = 1'b0; - reg [$clog2(CHANNELS)-1:0] rd_counter = 'h00; - reg [$clog2(CHANNELS)-1:0] req_counter = 'h00; - reg [CHANNELS-1:0] dac_enable_d1 = 'h00; + reg [$clog2(NUM_OF_CHANNELS)-1:0] rd_counter = 'h00; + reg [$clog2(NUM_OF_CHANNELS)-1:0] req_counter = 'h00; + reg [NUM_OF_CHANNELS-1:0] dac_enable_d1 = 'h00; assign dac_enable[0] = dac_enable_00; assign dac_enable[1] = dac_enable_01; @@ -152,7 +152,7 @@ module util_dac_unpack ( assign dac_data_03 = dac_data[DATA_WIDTH*4-1:DATA_WIDTH*3]; generate - if (CHANNELS >= 8) begin + if (NUM_OF_CHANNELS >= 8) begin assign dac_enable[4] = dac_enable_04; assign dac_enable[5] = dac_enable_05; assign dac_enable[6] = dac_enable_06; @@ -191,7 +191,7 @@ module util_dac_unpack ( buffer <= dma_data; rd_counter <= 'h0; end else if (dac_chan_valid == 1'b1) begin - rd_counter <= rd_counter + enable_reduce(CHANNELS); + rd_counter <= rd_counter + enable_reduce(NUM_OF_CHANNELS); end end @@ -200,7 +200,7 @@ module util_dac_unpack ( if (dac_enable != dac_enable_d1) begin req_counter <= 'h00; end else if (dac_chan_valid == 1'b1) begin - req_counter <= req_counter + enable_reduce(CHANNELS); + req_counter <= req_counter + enable_reduce(NUM_OF_CHANNELS); if (req_counter == 'h00) begin dma_rd <= 1'b1; end @@ -210,14 +210,14 @@ module util_dac_unpack ( generate genvar i; - for (i = 0; i < CHANNELS; i = i + 1) begin : gen_data_array + for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin : gen_data_array assign data_array[i] = buffer[DATA_WIDTH+i*DATA_WIDTH-1:i*DATA_WIDTH]; end endgenerate generate genvar j; - for (j = 0; j < CHANNELS; j = j + 1) begin : gen_dac_data + for (j = 0; j < NUM_OF_CHANNELS; j = j + 1) begin : gen_dac_data assign offset[j] = rd_counter + enable_reduce(j); always @(posedge clk) begin if (dac_chan_valid) begin diff --git a/library/util_dac_unpack/util_dac_unpack_hw.tcl b/library/util_dac_unpack/util_dac_unpack_hw.tcl index 5a08d9999..549860d43 100644 --- a/library/util_dac_unpack/util_dac_unpack_hw.tcl +++ b/library/util_dac_unpack/util_dac_unpack_hw.tcl @@ -15,14 +15,14 @@ add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" set_fileset_property quartus_synth TOP_LEVEL util_dac_unpack add_fileset_file util_dac_unpack.v VERILOG PATH util_dac_unpack.v -add_parameter CHANNELS INTEGER 0 -set_parameter_property CHANNELS DEFAULT_VALUE 8 -set_parameter_property CHANNELS ALLOWED_RANGES {4 8} -set_parameter_property CHANNELS DESCRIPTION "Valid values are 4 and 8" -set_parameter_property CHANNELS DISPLAY_NAME CHANNELS -set_parameter_property CHANNELS TYPE INTEGER -set_parameter_property CHANNELS UNITS None -set_parameter_property CHANNELS HDL_PARAMETER true +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8} +set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8" +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true add_parameter DATA_WIDTH INTEGER 0 set_parameter_property DATA_WIDTH DEFAULT_VALUE 16 @@ -36,7 +36,7 @@ add_interface_port data_clock clk clk Input 1 proc util_dac_unpack_elaborate {} { set DW [ get_parameter_value DATA_WIDTH ] - set CHAN [ get_parameter_value CHANNELS ] + set CHAN [ get_parameter_value NUM_OF_CHANNELS ] add_interface channels_data conduit end set_interface_property channels_data associatedClock data_clock diff --git a/library/util_dac_unpack/util_dac_unpack_ip.tcl b/library/util_dac_unpack/util_dac_unpack_ip.tcl index a5a2a7570..d5ada0d9b 100644 --- a/library/util_dac_unpack/util_dac_unpack_ip.tcl +++ b/library/util_dac_unpack/util_dac_unpack_ip.tcl @@ -22,7 +22,7 @@ for {set i 0} {$i < 8} {incr i} { foreach port {"dac_enable" "dac_valid" "dac_data"} { set name [format "%s_%.2d" $port $i] set_property ENABLEMENT_DEPENDENCY \ - "(spirit:decode(id('MODELPARAM_VALUE.CHANNELS')) > $i)" \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \ [ipx::get_ports $name] } foreach port {"dac_enable" "dac_valid"} { diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index ccd2097b1..f15c93043 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -59,7 +59,7 @@ module util_dacfifo ( ); // depth of the FIFO - parameter ADDR_WIDTH = 6; + parameter ADDRESS_WIDTH = 6; parameter DATA_WIDTH = 128; // local parameters @@ -84,14 +84,14 @@ module util_dacfifo ( // internal registers - reg [(ADDR_WIDTH-1):0] dma_waddr = 'b0; - reg [(ADDR_WIDTH-1):0] dma_lastaddr = 'b0; - reg [(ADDR_WIDTH-1):0] dma_lastaddr_d = 'b0; - reg [(ADDR_WIDTH-1):0] dma_lastaddr_2d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0; reg dma_xfer_req_ff = 1'b0; reg dma_ready = 1'b0; - reg [(ADDR_WIDTH-1):0] dac_raddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0; reg [(DATA_WIDTH-1):0] dac_data = 'b0; // internal wires @@ -112,7 +112,7 @@ module util_dacfifo ( always @(posedge dma_clk) begin if(dma_rst == 1'b1) begin dma_waddr <= 'b0; - dma_lastaddr <= {ADDR_WIDTH{1'b1}}; + dma_lastaddr <= {ADDRESS_WIDTH{1'b1}}; end else begin if (dma_valid && dma_xfer_req) begin dma_waddr <= dma_waddr + 1; @@ -146,7 +146,7 @@ module util_dacfifo ( // memory instantiation ad_mem #( - .ADDR_WIDTH (ADDR_WIDTH), + .ADDRESS_WIDTH (ADDRESS_WIDTH), .DATA_WIDTH (DATA_WIDTH)) i_mem_fifo ( .clka (dma_clk), diff --git a/library/util_pmod_fmeter/util_pmod_fmeter.v b/library/util_pmod_fmeter/util_pmod_fmeter.v index eaee75f75..da5dc5819 100644 --- a/library/util_pmod_fmeter/util_pmod_fmeter.v +++ b/library/util_pmod_fmeter/util_pmod_fmeter.v @@ -66,7 +66,7 @@ module util_pmod_fmeter ( // parameters - parameter PCORE_ID = 0; + parameter ID = 0; // physical interface diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v index e7c0d2d2f..d7c7e9ffb 100644 --- a/library/util_rfifo/util_rfifo.v +++ b/library/util_rfifo/util_rfifo.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -86,7 +86,7 @@ module util_rfifo ( parameter DAC_DATA_WIDTH = 32; parameter DMA_DATA_WIDTH = 64; - + // dac interface input dac_clk; diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v index b61eabc31..9a9f3fa3f 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -9,18 +9,18 @@ module util_sigma_delta_spi ( input s_sdo, input s_sdo_t, output s_sdi, - input [NUM_CS-1:0] s_cs, + input [NUM_OF_CS-1:0] s_cs, output m_sclk, output m_sdo, output m_sdo_t, input m_sdi, - output [NUM_CS-1:0] m_cs, + output [NUM_OF_CS-1:0] m_cs, output reg data_ready ); -parameter NUM_CS = 1; +parameter NUM_OF_CS = 1; parameter CS_PIN = 0; parameter IDLE_TIMEOUT = 63; diff --git a/library/util_upack/util_upack.v b/library/util_upack/util_upack.v index dd1a0a993..4d3153274 100755 --- a/library/util_upack/util_upack.v +++ b/library/util_upack/util_upack.v @@ -86,49 +86,49 @@ module util_upack ( // parameters - parameter CH_DW = 32; - parameter CH_CNT = 8; + parameter CHANNEL_DATA_WIDTH = 32; + parameter NUM_OF_CHANNELS = 8; - localparam M_CNT = 8; - localparam P_CNT = CH_CNT; - localparam CH_SCNT = CH_DW/16; - localparam M_WIDTH = CH_DW*M_CNT; - localparam P_WIDTH = CH_DW*P_CNT; + localparam NUM_OF_CHANNELS_M = 8; + localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS; + localparam CH_SCNT = CHANNEL_DATA_WIDTH/16; + localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; + localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; // dac interface input dac_clk; input dac_enable_0; input dac_valid_0; - output [(CH_DW-1):0] dac_data_0; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0; output upack_valid_0; input dac_enable_1; input dac_valid_1; - output [(CH_DW-1):0] dac_data_1; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1; output upack_valid_1; input dac_enable_2; input dac_valid_2; - output [(CH_DW-1):0] dac_data_2; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2; output upack_valid_2; input dac_enable_3; input dac_valid_3; - output [(CH_DW-1):0] dac_data_3; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3; output upack_valid_3; input dac_enable_4; input dac_valid_4; - output [(CH_DW-1):0] dac_data_4; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4; output upack_valid_4; input dac_enable_5; input dac_valid_5; - output [(CH_DW-1):0] dac_data_5; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5; output upack_valid_5; input dac_enable_6; input dac_valid_6; - output [(CH_DW-1):0] dac_data_6; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6; output upack_valid_6; input dac_enable_7; input dac_valid_7; - output [(CH_DW-1):0] dac_data_7; + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7; output upack_valid_7; input dma_xfer_in; @@ -138,7 +138,7 @@ module util_upack ( output dac_valid; output dac_sync; - input [((CH_CNT*CH_DW)-1):0] dac_data; + input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data; // internal registers @@ -156,9 +156,9 @@ module util_upack ( // internal signals wire dac_valid_s; - wire dac_dsf_valid_s[(M_CNT-1):0]; - wire dac_dsf_sync_s[(M_CNT-1):0]; - wire [(M_WIDTH-1):0] dac_dsf_data_s[(M_CNT-1):0]; + wire dac_dsf_valid_s[(NUM_OF_CHANNELS_M-1):0]; + wire dac_dsf_sync_s[(NUM_OF_CHANNELS_M-1):0]; + wire [(M_WIDTH-1):0] dac_dsf_data_s[(NUM_OF_CHANNELS_M-1):0]; wire [(CH_SCNT-1):0] dac_dmx_enable_7_s; wire [(CH_SCNT-1):0] dac_dmx_enable_6_s; wire [(CH_SCNT-1):0] dac_dmx_enable_5_s; @@ -192,7 +192,7 @@ module util_upack ( xfer_valid_d3 <= xfer_valid_d2; xfer_valid_d4 <= xfer_valid_d3; xfer_valid_d5 <= xfer_valid_d4; - if (dac_dmx_enable[P_CNT-1] == 1'b1) begin + if (dac_dmx_enable[NUM_OF_CHANNELS_P-1] == 1'b1) begin dac_xfer_out <= xfer_valid_d4; end else begin dac_xfer_out <= xfer_valid_d5; @@ -225,20 +225,20 @@ module util_upack ( // store & fwd generate - if (P_CNT < M_CNT) begin - for (n = P_CNT; n < M_CNT; n = n + 1) begin: g_def + if (NUM_OF_CHANNELS_P < NUM_OF_CHANNELS_M) begin + for (n = NUM_OF_CHANNELS_P; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_def assign dac_dsf_valid_s[n] = 'd0; assign dac_dsf_sync_s[n] = 'd0; assign dac_dsf_data_s[n] = 'd0; end end - for (n = 0; n < P_CNT; n = n + 1) begin: g_dsf + for (n = 0; n < NUM_OF_CHANNELS_P; n = n + 1) begin: g_dsf util_upack_dsf #( - .P_CNT (P_CNT), - .M_CNT (M_CNT), - .CH_DW (CH_DW), - .CH_OCNT ((n+1))) + .NUM_OF_CHANNELS_P (NUM_OF_CHANNELS_P), + .NUM_OF_CHANNELS_M (NUM_OF_CHANNELS_M), + .CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH), + .NUM_OF_CHANNELS_O ((n+1))) i_dsf ( .dac_clk (dac_clk), .dac_valid (dac_valid_s), @@ -270,7 +270,7 @@ module util_upack ( dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n], dac_dmx_enable_3_s[n], dac_dmx_enable_2_s[n], dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}), - .dac_dsf_data (dac_dsf_data[((M_CNT*16*(n+1))-1):(M_CNT*16*n)])); + .dac_dsf_data (dac_dsf_data[((NUM_OF_CHANNELS_M*16*(n+1))-1):(NUM_OF_CHANNELS_M*16*n)])); end endgenerate diff --git a/library/util_upack/util_upack_dsf.v b/library/util_upack/util_upack_dsf.v index af57907b7..bb4f62dbe 100755 --- a/library/util_upack/util_upack_dsf.v +++ b/library/util_upack/util_upack_dsf.v @@ -54,17 +54,17 @@ module util_upack_dsf ( // parameters - parameter P_CNT = 4; - parameter M_CNT = 8; - parameter CH_DW = 32; - parameter CH_OCNT = 4; + parameter NUM_OF_CHANNELS_P = 4; + parameter NUM_OF_CHANNELS_M = 8; + parameter CHANNEL_DATA_WIDTH = 32; + parameter NUM_OF_CHANNELS_O = 4; - localparam CH_SCNT = CH_DW/16; - localparam P_WIDTH = CH_DW*P_CNT; - localparam M_WIDTH = CH_DW*M_CNT; - localparam O_WIDTH = CH_DW*CH_OCNT; - localparam E_WIDTH = CH_DW*(M_CNT+1); - localparam CH_DCNT = P_CNT - CH_OCNT; + localparam CH_SCNT = CHANNEL_DATA_WIDTH/16; + localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; + localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; + localparam O_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_O; + localparam E_WIDTH = CHANNEL_DATA_WIDTH*(NUM_OF_CHANNELS_M+1); + localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_O; // dac interface @@ -104,16 +104,16 @@ module util_upack_dsf ( genvar i; generate - if (CH_OCNT == P_CNT) begin + if (NUM_OF_CHANNELS_O == NUM_OF_CHANNELS_P) begin for (i = 0; i < CH_SCNT ; i = i +1) begin: g_dsf_data - assign dac_dsf_data_s[(((i +1) * M_CNT * 16)-1):(i*M_CNT*16)] = - dac_data[(((i+1)*16*P_CNT)-1): (i*16*P_CNT)]; + assign dac_dsf_data_s[(((i +1) * NUM_OF_CHANNELS_M * 16)-1):(i*NUM_OF_CHANNELS_M*16)] = + dac_data[(((i+1)*16*NUM_OF_CHANNELS_P)-1): (i*16*NUM_OF_CHANNELS_P)]; end end endgenerate generate - if (CH_OCNT == P_CNT) begin + if (NUM_OF_CHANNELS_O == NUM_OF_CHANNELS_P) begin assign dac_samples_int_s = 'd0; assign dac_data_s = 'd0; @@ -142,15 +142,15 @@ module util_upack_dsf ( // data store & forward generate - if (P_CNT > CH_OCNT) begin + if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_O) begin assign dac_samples_int_s = (dac_dsf_valid == 1'b1) ? (dac_samples_int + CH_DCNT) : - ((dac_samples_int >= CH_OCNT) ? (dac_samples_int - CH_OCNT) : dac_samples_int); + ((dac_samples_int >= NUM_OF_CHANNELS_O) ? (dac_samples_int - NUM_OF_CHANNELS_O) : dac_samples_int); always @(posedge dac_clk) begin dac_dmx_valid <= dac_valid & dac_dmx_enable; - if (dac_samples_int_s < CH_OCNT) begin + if (dac_samples_int_s < NUM_OF_CHANNELS_O) begin dac_dsf_valid <= dac_valid & dac_dmx_enable; end else begin dac_dsf_valid <= 1'b0; @@ -190,20 +190,20 @@ module util_upack_dsf ( always @(posedge dac_clk) begin if (dac_dmx_valid_d == 1'b1) begin case (dac_samples_int_d) - 3'b111: dac_dsf_data_int <= { dac_data_s[((CH_DW*1)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*1)]}; - 3'b110: dac_dsf_data_int <= { dac_data_s[((CH_DW*2)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*2)]}; - 3'b101: dac_dsf_data_int <= { dac_data_s[((CH_DW*3)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*3)]}; - 3'b100: dac_dsf_data_int <= { dac_data_s[((CH_DW*4)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*4)]}; - 3'b011: dac_dsf_data_int <= { dac_data_s[((CH_DW*5)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*5)]}; - 3'b010: dac_dsf_data_int <= { dac_data_s[((CH_DW*6)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*6)]}; - 3'b001: dac_dsf_data_int <= { dac_data_s[((CH_DW*7)-1):0], - dac_data_int[((CH_DW*8)-1):(CH_DW*7)]}; + 3'b111: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*1)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*1)]}; + 3'b110: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*2)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*2)]}; + 3'b101: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*3)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*3)]}; + 3'b100: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*4)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*4)]}; + 3'b011: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*5)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*5)]}; + 3'b010: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*6)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*6)]}; + 3'b001: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*7)-1):0], + dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]}; 3'b000: dac_dsf_data_int <= dac_data_s; default: dac_dsf_data_int <= 'd0; endcase @@ -214,18 +214,18 @@ module util_upack_dsf ( genvar n; generate - if (P_CNT > CH_OCNT) begin + if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_O) begin assign dac_dsf_data_s[M_WIDTH] = 'd0; for (n = 0; n < CH_SCNT; n = n + 1) begin: g_out - assign dac_dsf_data_s[(((n+1)*M_CNT*16)-1):(((n*M_CNT)+CH_OCNT)*16)] = 'd0; - assign dac_dsf_data_s[((((n*M_CNT)+CH_OCNT)*16)-1):(n*M_CNT*16)] = - dac_dsf_data_int[(((n+1)*CH_OCNT*16)-1):(n*CH_OCNT*16)]; + assign dac_dsf_data_s[(((n+1)*NUM_OF_CHANNELS_M*16)-1):(((n*NUM_OF_CHANNELS_M)+NUM_OF_CHANNELS_O)*16)] = 'd0; + assign dac_dsf_data_s[((((n*NUM_OF_CHANNELS_M)+NUM_OF_CHANNELS_O)*16)-1):(n*NUM_OF_CHANNELS_M*16)] = + dac_dsf_data_int[(((n+1)*NUM_OF_CHANNELS_O*16)-1):(n*NUM_OF_CHANNELS_O*16)]; end end endgenerate generate - if (P_CNT > CH_OCNT) begin + if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_O) begin always @(posedge dac_clk) begin if (dac_dmx_enable == 1'b1) begin dac_dsf_data <= dac_dsf_data_s[(M_WIDTH-1):0]; diff --git a/library/util_upack/util_upack_hw.tcl b/library/util_upack/util_upack_hw.tcl index 543b3d1a3..f2c1c3b4d 100755 --- a/library/util_upack/util_upack_hw.tcl +++ b/library/util_upack/util_upack_hw.tcl @@ -22,19 +22,19 @@ add_fileset_file util_upack.v VERILOG PATH util_upack.v TOP_LEVEL_FILE # parameters -add_parameter CH_DW INTEGER 0 -set_parameter_property CH_DW DEFAULT_VALUE 32 -set_parameter_property CH_DW DISPLAY_NAME CH_DW -set_parameter_property CH_DW TYPE INTEGER -set_parameter_property CH_DW UNITS None -set_parameter_property CH_DW HDL_PARAMETER true +add_parameter CHANNEL_DATA_WIDTH INTEGER 0 +set_parameter_property CHANNEL_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property CHANNEL_DATA_WIDTH DISPLAY_NAME CHANNEL_DATA_WIDTH +set_parameter_property CHANNEL_DATA_WIDTH TYPE INTEGER +set_parameter_property CHANNEL_DATA_WIDTH UNITS None +set_parameter_property CHANNEL_DATA_WIDTH HDL_PARAMETER true -add_parameter CH_CNT INTEGER 0 -set_parameter_property CH_CNT DEFAULT_VALUE 8 -set_parameter_property CH_CNT DISPLAY_NAME CH_CNT -set_parameter_property CH_CNT TYPE INTEGER -set_parameter_property CH_CNT UNITS None -set_parameter_property CH_CNT HDL_PARAMETER true +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # defaults @@ -43,54 +43,54 @@ ad_alt_intf signal dma_xfer_in input 1 ad_alt_intf signal dac_xfer_out output 1 ad_alt_intf signal dac_valid output 1 ad_alt_intf signal dac_sync output 1 -ad_alt_intf signal dac_data input CH_CNT*CH_DW +ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH ad_alt_intf signal dac_enable_0 input 1 ad_alt_intf signal dac_valid_0 input 1 -ad_alt_intf signal dac_data_0 output CH_DW +ad_alt_intf signal dac_data_0 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_0 output 1 proc p_util_upack {} { - if {[get_parameter_value CH_CNT] > 1} { + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { ad_alt_intf signal dac_enable_1 input 1 ad_alt_intf signal dac_valid_1 input 1 - ad_alt_intf signal dac_data_1 output CH_DW + ad_alt_intf signal dac_data_1 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_1 output 1 } - if {[get_parameter_value CH_CNT] > 2} { + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { ad_alt_intf signal dac_enable_2 input 1 ad_alt_intf signal dac_valid_2 input 1 - ad_alt_intf signal dac_data_2 output CH_DW + ad_alt_intf signal dac_data_2 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_2 output 1 } - if {[get_parameter_value CH_CNT] > 3} { + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { ad_alt_intf signal dac_enable_3 input 1 ad_alt_intf signal dac_valid_3 input 1 - ad_alt_intf signal dac_data_3 output CH_DW + ad_alt_intf signal dac_data_3 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_3 output 1 } - if {[get_parameter_value CH_CNT] > 4} { + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { ad_alt_intf signal dac_enable_4 input 1 ad_alt_intf signal dac_valid_4 input 1 - ad_alt_intf signal dac_data_4 output CH_DW + ad_alt_intf signal dac_data_4 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_4 output 1 } - if {[get_parameter_value CH_CNT] > 5} { + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { ad_alt_intf signal dac_enable_5 input 1 ad_alt_intf signal dac_valid_5 input 1 - ad_alt_intf signal dac_data_5 output CH_DW + ad_alt_intf signal dac_data_5 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_5 output 1 } - if {[get_parameter_value CH_CNT] > 6} { + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { ad_alt_intf signal dac_enable_6 input 1 ad_alt_intf signal dac_valid_6 input 1 - ad_alt_intf signal dac_data_6 output CH_DW + ad_alt_intf signal dac_data_6 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_6 output 1 } - if {[get_parameter_value CH_CNT] > 7} { + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { ad_alt_intf signal dac_enable_7 input 1 ad_alt_intf signal dac_valid_7 input 1 - ad_alt_intf signal dac_data_7 output CH_DW + ad_alt_intf signal dac_data_7 output CHANNEL_DATA_WIDTH ad_alt_intf signal upack_valid_7 output 1 } } diff --git a/library/util_upack/util_upack_ip.tcl b/library/util_upack/util_upack_ip.tcl index 8bf6f003c..485b47169 100644 --- a/library/util_upack/util_upack_ip.tcl +++ b/library/util_upack/util_upack_ip.tcl @@ -18,19 +18,19 @@ set_property driver_value 0 [ipx::get_ports *dac_enable* -of_objects [ipx::curre set_property driver_value 0 [ipx::get_ports *dac_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_data* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dma_xfer_in* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 1} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ [ipx::get_ports *_1* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 2} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ [ipx::get_ports *_2* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 3} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ [ipx::get_ports *_3* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 4} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ [ipx::get_ports *_4* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 5} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ [ipx::get_ports *_5* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 6} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ [ipx::get_ports *_6* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CH_CNT')) > 7} \ +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ [ipx::get_ports *_7* -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core] diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v index 1f93d1b13..c02555d73 100644 --- a/library/util_wfifo/util_wfifo.v +++ b/library/util_wfifo/util_wfifo.v @@ -108,10 +108,10 @@ module util_wfifo ( parameter NUM_OF_CHANNELS = 4; parameter DIN_DATA_WIDTH = 32; parameter DOUT_DATA_WIDTH = 64; - parameter DIN_ADDR_WIDTH = 8; + parameter DIN_ADDRESS_WIDTH = 8; localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH; - localparam ADDR_WIDTH = (DIN_ADDR_WIDTH > 4) ? DIN_ADDR_WIDTH : 4; + localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4; localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS; localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8; localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8; @@ -182,20 +182,20 @@ module util_wfifo ( reg [ 7:0] din_enable = 'd0; reg [ 2:0] din_dcnt = 'd0; reg din_wr = 'd0; - reg [(ADDR_WIDTH-1):0] din_waddr = 'd0; + reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0; reg din_waddr_rel_t = 'd0; - reg [(ADDR_WIDTH-1):0] din_waddr_rel = 'd0; + reg [(ADDRESS_WIDTH-1):0] din_waddr_rel = 'd0; reg [ 2:0] din_ovf_m = 'd0; reg din_ovf = 'd0; reg [ 2:0] dout_waddr_rel_t_m = 'd0; - reg [(ADDR_WIDTH-1):0] dout_waddr_rel = 'd0; + reg [(ADDRESS_WIDTH-1):0] dout_waddr_rel = 'd0; reg dout_ovf_int = 'd0; reg [ 7:0] dout_enable_m = 'd0; reg [ 7:0] dout_enable = 'd0; reg dout_rd = 'd0; reg dout_rd_d = 'd0; reg [(DATA_WIDTH-1):0] dout_rdata_d = 'd0; - reg [(ADDR_WIDTH-1):0] dout_raddr = 'd0; + reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; // internal signals @@ -356,7 +356,7 @@ module util_wfifo ( // instantiations - ad_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem ( + ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem ( .clka (din_clk), .wea (din_wr), .addra (din_waddr), diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index 7f688cc47..a28083b20 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -37,24 +37,24 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad6676_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad6676_gt set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad6676_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad6676_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad6676_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad6676_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma # connections (gt) ad_connect axi_ad6676_gt/ref_clk_c rx_ref_clk -ad_connect axi_ad6676_gt/rx_data_p rx_data_p -ad_connect axi_ad6676_gt/rx_data_n rx_data_n +ad_connect axi_ad6676_gt/rx_data_p rx_data_p +ad_connect axi_ad6676_gt/rx_data_n rx_data_n ad_connect axi_ad6676_gt/rx_sync rx_sync ad_connect axi_ad6676_gt/rx_sysref rx_sysref @@ -71,32 +71,32 @@ ad_connect axi_ad6676_gt/rx_sysref axi_ad6676_jesd/rx_sysref ad_connect axi_ad6676_gt/tx_clk_g axi_ad6676_gt/tx_clk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_ad6676_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad6676_jesd/gt0_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad6676_jesd/gt1_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_disperr] ad_connect util_bsplit_rx_gt_disperr/data axi_ad6676_gt/rx_gt_disperr ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad6676_jesd/gt0_rxdisperr ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad6676_jesd/gt1_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_ad6676_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad6676_jesd/gt0_rxnotintable ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad6676_jesd/gt1_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_ad6676_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad6676_jesd/gt0_rxdata diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index cd3b73ebd..2d3efdb12 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -13,18 +13,18 @@ create_bd_port -dir I -from 7 -to 0 adc_data_in_p set axi_ad9265 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9265:1.0 axi_ad9265] set axi_ad9265_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9265_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9265_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9265_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9265_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9265_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9265_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9265_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9265_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9265_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9265_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9265_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma # clock for ila diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl index 6f7295451..eda8d00b1 100644 --- a/projects/ad9434_fmc/common/ad9434_bd.tcl +++ b/projects/ad9434_fmc/common/ad9434_bd.tcl @@ -14,17 +14,17 @@ set axi_ad9434 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9434:1.0 ax # dma for ad9434 set axi_ad9434_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9434_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9434_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9434_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9434_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9434_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9434_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma # additions to default configuration diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 2e6c2f45a..cf299b1eb 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -13,18 +13,18 @@ create_bd_port -dir I -from 7 -to 0 adc_data_in_p set axi_ad9467 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9467:1.0 axi_ad9467] set axi_ad9467_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9467_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9467_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9467_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9467_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9467_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9467_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9467_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9467_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9467_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9467_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9467_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma # connections (ad9467) diff --git a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl index 377148b19..c52c6cc19 100644 --- a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl +++ b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl @@ -15,16 +15,16 @@ create_bd_port -dir O -from 13 -to 0 dac_data_out_b_n set axi_ad9739a [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9739a:1.0 axi_ad9739a] set axi_ad9739a_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9739a_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_FIFO_SIZE {64}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9739a_dma -set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9739a_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9739a_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9739a_dma +set_property -dict [list CONFIG.FIFO_SIZE {64}] $axi_ad9739a_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9739a_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9739a_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9739a_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9739a_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9739a_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9739a_dma +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9739a_dma # connections (dac) @@ -38,7 +38,7 @@ ad_connect dac_data_out_b_p axi_ad9739a/dac_data_out_b_p ad_connect dac_data_out_b_n axi_ad9739a/dac_data_out_b_n ad_connect dac_div_clk axi_ad9739a/dac_div_clk ad_connect dac_div_clk axi_ad9739a_dma/fifo_rd_clk -ad_connect axi_ad9739a/dac_valid axi_ad9739a_dma/fifo_rd_en +ad_connect axi_ad9739a/dac_valid axi_ad9739a_dma/fifo_rd_en ad_connect axi_ad9739a/dac_ddata axi_ad9739a_dma/fifo_rd_dout ad_connect axi_ad9739a/dac_dunf axi_ad9739a_dma/fifo_rd_underflow diff --git a/projects/adv7511/common/adv7511_bd.tcl b/projects/adv7511/common/adv7511_bd.tcl index 373604314..2ca203683 100755 --- a/projects/adv7511/common/adv7511_bd.tcl +++ b/projects/adv7511/common/adv7511_bd.tcl @@ -37,7 +37,7 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma] set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma diff --git a/projects/adv7511/kcu105/system_bd.tcl b/projects/adv7511/kcu105/system_bd.tcl index 8b0ba82fa..ff697a7c9 100644 --- a/projects/adv7511/kcu105/system_bd.tcl +++ b/projects/adv7511/kcu105/system_bd.tcl @@ -2,5 +2,5 @@ source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl source ../common/adv7511_bd.tcl -set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_hdmi_core +set_property -dict [list CONFIG.DEVICE_TYPE {1}] $axi_hdmi_core diff --git a/projects/cftl_cip/common/cftl_cip_bd.tcl b/projects/cftl_cip/common/cftl_cip_bd.tcl index 3d1ccba03..92b48b30b 100644 --- a/projects/cftl_cip/common/cftl_cip_bd.tcl +++ b/projects/cftl_cip/common/cftl_cip_bd.tcl @@ -18,10 +18,10 @@ set_property -dict [list CONFIG.FPGA_CLOCK_MHZ {100}] $pmod_spi_core set pmod_spi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 pmod_spi_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $pmod_spi_dma set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $pmod_spi_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $pmod_spi_dma +set_property -dict [list CONFIG.ID {0}] $pmod_spi_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $pmod_spi_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $pmod_spi_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $pmod_spi_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $pmod_spi_dma set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $pmod_spi_dma set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $pmod_spi_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $pmod_spi_dma diff --git a/projects/cn0363/zed/system_bd.tcl b/projects/cn0363/zed/system_bd.tcl index b769b2a63..fed015c7f 100644 --- a/projects/cn0363/zed/system_bd.tcl +++ b/projects/cn0363/zed/system_bd.tcl @@ -35,9 +35,9 @@ set_property -dict [list \ CONFIG.C_SYNC_TRANSFER_START 1 \ CONFIG.C_AXI_SLICE_SRC 0 \ CONFIG.C_AXI_SLICE_DEST 0 \ - CONFIG.C_CLKS_ASYNC_DEST_REQ 0 \ - CONFIG.C_CLKS_ASYNC_SRC_DEST 0 \ - CONFIG.C_CLKS_ASYNC_REQ_SRC 0 \ + CONFIG.ASYNC_CLK_DEST_REQ 0 \ + CONFIG.ASYNC_CLK_SRC_DEST 0 \ + CONFIG.ASYNC_CLK_REQ_SRC 0 \ CONFIG.C_2D_TRANSFER 0 \ CONFIG.C_DMA_DATA_WIDTH_SRC 32 \ CONFIG.C_DMA_DATA_WIDTH_DEST 64 \ @@ -61,9 +61,9 @@ current_bd_instance /spi set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect] set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi] - set_property -dict [list CONFIG.NUM_CS 2] $spi_engine + set_property -dict [list CONFIG.NUM_OF_CS 2] $spi_engine - set_property -dict [list CONFIG.NUM_CS 2] $util_sigma_delta_spi + set_property -dict [list CONFIG.NUM_OF_CS 2] $util_sigma_delta_spi ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl @@ -147,8 +147,8 @@ current_bd_instance /processing set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize] set_property -dict [list \ - CONFIG.C_M_DATA_WIDTH 32 \ - CONFIG.C_S_DATA_WIDTH 64 \ + CONFIG.MASTER_DATA_WIDTH 32 \ + CONFIG.SLAVE_DATA_WIDTH 64 \ ] $i_q_resize set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf] @@ -268,7 +268,7 @@ ad_connect /phase_gen/Q /processing/phase set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc] set_property -dict [list \ - CONFIG.NUM_CHANNELS 14 \ + CONFIG.NUM_OF_CHANNELS 14 \ ] $axi_adc ad_connect processing/overflow axi_adc/adc_dovf diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index eae42e744..1a4387108 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -119,7 +119,7 @@ set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer] set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd] -set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd +set_property -dict [list CONFIG.C_GPDATA_WIDTH {7}] $axi_gpio_lcd set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi] @@ -129,7 +129,7 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio] set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio -set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_GPDATA_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 069734ec6..00384958c 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -102,7 +102,7 @@ set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer] set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd] -set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd +set_property -dict [list CONFIG.C_GPDATA_WIDTH {7}] $axi_gpio_lcd set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi] @@ -112,7 +112,7 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio] set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio -set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_GPDATA_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 3f956f44d..bb28fadec 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -129,7 +129,7 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio] set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio -set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_GPDATA_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index 671ac9ad6..8be4ef0d6 100644 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -119,11 +119,11 @@ set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi # system reset/clock definitions diff --git a/projects/common/rfsom/rfsom_system_bd.tcl b/projects/common/rfsom/rfsom_system_bd.tcl index 326662869..bf7186079 100644 --- a/projects/common/rfsom/rfsom_system_bd.tcl +++ b/projects/common/rfsom/rfsom_system_bd.tcl @@ -145,11 +145,11 @@ set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi # system reset/clock definitions diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index afe6de9dd..5b4309374 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -106,7 +106,7 @@ set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer] set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd] -set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd +set_property -dict [list CONFIG.C_GPDATA_WIDTH {7}] $axi_gpio_lcd set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi] @@ -116,7 +116,7 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio] set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio -set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_GPDATA_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dmafifo.tcl index c816f0004..dec208f4f 100644 --- a/projects/common/xilinx/sys_dmafifo.tcl +++ b/projects/common/xilinx/sys_dmafifo.tcl @@ -31,7 +31,7 @@ proc p_sys_dmafifo {p_name m_name adc_data_width dma_addr_width} { set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $util_adcfifo set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $util_adcfifo set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $util_adcfifo - set_property -dict [list CONFIG.DMA_ADDR_WIDTH $dma_addr_width] $util_adcfifo + set_property -dict [list CONFIG.DMA_ADDRESS_WIDTH $dma_addr_width] $util_adcfifo ad_connect adc_rst util_adcfifo/adc_rst ad_connect adc_clk util_adcfifo/adc_clk @@ -74,7 +74,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} { set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo] set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo - set_property -dict [list CONFIG.ADDR_WIDTH $addr_width] $util_dacfifo + set_property -dict [list CONFIG.ADDRESS_WIDTH $addr_width] $util_dacfifo ad_connect dma_clk util_dacfifo/dma_clk ad_connect dac_clk util_dacfifo/dac_clk diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index f55e25d92..e35e122f4 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -108,7 +108,7 @@ set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core # system reset/clock definitions diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 768728121..e117b3d6d 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -111,7 +111,7 @@ set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core # system reset/clock definitions diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index 8b07882d0..38bc92777 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -48,7 +48,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_adcfifo set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo - set_property -dict [list CONFIG.AXI_ADDRLIMIT {0xa0000000}] $axi_adcfifo + set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo ad_connect sys_rst axi_ddr_cntrl/sys_rst diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 8f135fb1f..0c6835396 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -133,11 +133,11 @@ set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi # iic (fmc) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index ae4552a3d..32a5656f8 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -44,7 +44,7 @@ create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.PCORE_ID {1}] [get_bd_cells axi_ad9122_dma] +set_property -dict [list CONFIG.ID {1}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma] @@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd set axi_ad9250_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_dma set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9250_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma @@ -113,29 +113,29 @@ ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_core/rx_clk ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_jesd/rx_core_clk set util_bsplit_rx_gt_charisk [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_daq1_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9250_jesd/gt1_rxcharisk set util_bsplit_gt_rxdisperr [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_gt_rxdisperr] -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_gt_rxdisperr] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_gt_rxdisperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_gt_rxdisperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_gt_rxdisperr] ad_connect util_bsplit_gt_rxdisperr/data axi_daq1_gt/rx_gt_disperr ad_connect util_bsplit_gt_rxdisperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr ad_connect util_bsplit_gt_rxdisperr/split_data_1 axi_ad9250_jesd/gt1_rxdisperr set util_bsplit_rx_gt_notintable [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_daq1_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9250_jesd/gt1_rxnotintable set util_bsplit_rx_gt_data [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_daq1_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 00842dc09..1ed7ba212 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -16,28 +16,28 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n # dac peripherals set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] -set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {1}] $axi_ad9144_dma -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.ID {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack] -set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9144_upack -set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9144_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack # adc peripherals @@ -48,22 +48,22 @@ set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] -set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9680_cpack -set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9680_cpack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack # dac/adc common gt @@ -141,7 +141,7 @@ ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0 ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1 ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1 ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1 -ad_connect util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk +ad_connect util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl index 24b559f0f..e2ad60771 100644 --- a/projects/daq2/kcu105/system_bd.tcl +++ b/projects/daq2/kcu105/system_bd.tcl @@ -7,7 +7,7 @@ p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 source ../common/daq2_bd.tcl -set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_daq2_gt +set_property -dict [list CONFIG.DEVICE_TYPE {1}] $axi_daq2_gt set_property -dict [list CONFIG.PCORE_QPLL_FBDIV {20}] $axi_daq2_gt set_property -dict [list CONFIG.PCORE_QPLL_REFCLK_DIV {1}] $axi_daq2_gt diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index df4c4b402..1b3c4298e 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -22,21 +22,21 @@ set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {1}] $axi_ad9152_dma -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9152_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9152_dma +set_property -dict [list CONFIG.ID {1}] $axi_ad9152_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9152_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9152_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9152_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9152_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack] -set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9152_upack -set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9152_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack # adc peripherals @@ -47,22 +47,22 @@ set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] -set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9680_cpack -set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9680_cpack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack # dac/adc common gt @@ -76,16 +76,16 @@ set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq3_gt # connections (gt) -ad_connect axi_daq3_gt/ref_clk_q rx_ref_clk -ad_connect axi_daq3_gt/ref_clk_c tx_ref_clk -ad_connect axi_daq3_gt/rx_data_p rx_data_p -ad_connect axi_daq3_gt/rx_data_n rx_data_n -ad_connect axi_daq3_gt/rx_sync rx_sync -ad_connect axi_daq3_gt/rx_ext_sysref rx_sysref -ad_connect axi_daq3_gt/tx_data_p tx_data_p -ad_connect axi_daq3_gt/tx_data_n tx_data_n -ad_connect axi_daq3_gt/tx_sync tx_sync -ad_connect axi_daq3_gt/tx_ext_sysref tx_sysref +ad_connect axi_daq3_gt/ref_clk_q rx_ref_clk +ad_connect axi_daq3_gt/ref_clk_c tx_ref_clk +ad_connect axi_daq3_gt/rx_data_p rx_data_p +ad_connect axi_daq3_gt/rx_data_n rx_data_n +ad_connect axi_daq3_gt/rx_sync rx_sync +ad_connect axi_daq3_gt/rx_ext_sysref rx_sysref +ad_connect axi_daq3_gt/tx_data_p tx_data_p +ad_connect axi_daq3_gt/tx_data_n tx_data_n +ad_connect axi_daq3_gt/tx_sync tx_sync +ad_connect axi_daq3_gt/tx_ext_sysref tx_sysref # connections (dac) @@ -163,7 +163,7 @@ ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect axi_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect axi_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst ad_connect axi_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf @@ -201,6 +201,6 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi # interrupts -ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq -ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq +ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq +ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index 85e84cd28..be694028a 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -26,18 +26,18 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_gt set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9625_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma # connections (gt) @@ -57,8 +57,8 @@ ad_connect axi_ad9625_gt/rx_jesd_rst axi_ad9625_jesd/rx_reset ad_connect axi_ad9625_gt/rx_sysref axi_ad9625_jesd/rx_sysref create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_ad9625_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9625_jesd/gt0_rxcharisk @@ -71,8 +71,8 @@ ad_connect util_bsplit_rx_gt_charisk/split_data_6 axi_ad9625_jesd/gt6_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_7 axi_ad9625_jesd/gt7_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_disperr] ad_connect util_bsplit_rx_gt_disperr/data axi_ad9625_gt/rx_gt_disperr ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9625_jesd/gt0_rxdisperr @@ -85,8 +85,8 @@ ad_connect util_bsplit_rx_gt_disperr/split_data_6 axi_ad9625_jesd/gt6_rxdisperr ad_connect util_bsplit_rx_gt_disperr/split_data_7 axi_ad9625_jesd/gt7_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_ad9625_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9625_jesd/gt0_rxnotintable @@ -99,8 +99,8 @@ ad_connect util_bsplit_rx_gt_notintable/split_data_6 axi_ad9625_jesd/gt6_rxnoti ad_connect util_bsplit_rx_gt_notintable/split_data_7 axi_ad9625_jesd/gt7_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_ad9625_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9625_jesd/gt0_rxdata diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index 3ad06ecd6..5ceabe26d 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -27,27 +27,27 @@ create_bd_port -dir I -from 255 -to 0 adc_ddata # adc peripherals set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0] -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_core_0 +set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9680_core_1 +set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma # dac/adc common gt @@ -56,11 +56,11 @@ set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_fmcadc4_gt # connections (gt) -ad_connect axi_fmcadc4_gt/ref_clk_q rx_ref_clk -ad_connect axi_fmcadc4_gt/rx_data_p rx_data_p -ad_connect axi_fmcadc4_gt/rx_data_n rx_data_n -ad_connect axi_fmcadc4_gt/rx_sync rx_sync -ad_connect axi_fmcadc4_gt/rx_ext_sysref rx_sysref +ad_connect axi_fmcadc4_gt/ref_clk_q rx_ref_clk +ad_connect axi_fmcadc4_gt/rx_data_p rx_data_p +ad_connect axi_fmcadc4_gt/rx_data_n rx_data_n +ad_connect axi_fmcadc4_gt/rx_sync rx_sync +ad_connect axi_fmcadc4_gt/rx_ext_sysref rx_sysref # connections (adc) @@ -74,8 +74,8 @@ ad_connect axi_fmcadc4_gt/rx_rst axi_ad9680_jesd/rx_reset ad_connect axi_fmcadc4_gt/rx_sysref axi_ad9680_jesd/rx_sysref create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_fmcadc4_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9680_jesd/gt0_rxcharisk @@ -88,8 +88,8 @@ ad_connect util_bsplit_rx_gt_charisk/split_data_6 axi_ad9680_jesd/gt6_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_7 axi_ad9680_jesd/gt7_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_disperr] ad_connect util_bsplit_rx_gt_disperr/data axi_fmcadc4_gt/rx_gt_disperr ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9680_jesd/gt0_rxdisperr @@ -102,8 +102,8 @@ ad_connect util_bsplit_rx_gt_disperr/split_data_6 axi_ad9680_jesd/gt6_rxdisperr ad_connect util_bsplit_rx_gt_disperr/split_data_7 axi_ad9680_jesd/gt7_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_fmcadc4_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9680_jesd/gt0_rxnotintable @@ -116,8 +116,8 @@ ad_connect util_bsplit_rx_gt_notintable/split_data_6 axi_ad9680_jesd/gt6_rxnoti ad_connect util_bsplit_rx_gt_notintable/split_data_7 axi_ad9680_jesd/gt7_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_fmcadc4_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9680_jesd/gt0_rxdata @@ -136,8 +136,8 @@ ad_connect axi_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame ad_connect axi_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data -set_property -dict [list CONFIG.CH_DW {128}] [get_bd_cells util_bsplit_rx_data] -set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_data] ad_connect util_bsplit_rx_data/data axi_fmcadc4_gt/rx_data ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index e276b8fad..ad5571565 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -24,7 +24,7 @@ create_bd_port -dir I -from 511 -to 0 adc_wdata # adc peripherals set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core] -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_0_core +set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9625_0_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd @@ -41,7 +41,7 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_0_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_0_gt set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core] -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9625_1_core +set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9625_1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd @@ -58,18 +58,18 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_1_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_1_gt set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9625_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18 @@ -107,8 +107,8 @@ ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_0_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_0_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_0_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_charisk] ad_connect util_bsplit_rx_0_gt_charisk/data axi_ad9625_0_gt/rx_gt_charisk ad_connect util_bsplit_rx_0_gt_charisk/split_data_0 axi_ad9625_0_jesd/gt0_rxcharisk @@ -121,8 +121,8 @@ ad_connect util_bsplit_rx_0_gt_charisk/split_data_6 axi_ad9625_0_jesd/gt6_rxcha ad_connect util_bsplit_rx_0_gt_charisk/split_data_7 axi_ad9625_0_jesd/gt7_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_0_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_0_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_0_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_disperr] ad_connect util_bsplit_rx_0_gt_disperr/data axi_ad9625_0_gt/rx_gt_disperr ad_connect util_bsplit_rx_0_gt_disperr/split_data_0 axi_ad9625_0_jesd/gt0_rxdisperr @@ -135,8 +135,8 @@ ad_connect util_bsplit_rx_0_gt_disperr/split_data_6 axi_ad9625_0_jesd/gt6_rxdis ad_connect util_bsplit_rx_0_gt_disperr/split_data_7 axi_ad9625_0_jesd/gt7_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_0_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_0_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_0_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_notintable] ad_connect util_bsplit_rx_0_gt_notintable/data axi_ad9625_0_gt/rx_gt_notintable ad_connect util_bsplit_rx_0_gt_notintable/split_data_0 axi_ad9625_0_jesd/gt0_rxnotintable @@ -149,8 +149,8 @@ ad_connect util_bsplit_rx_0_gt_notintable/split_data_6 axi_ad9625_0_jesd/gt6_rx ad_connect util_bsplit_rx_0_gt_notintable/split_data_7 axi_ad9625_0_jesd/gt7_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_0_gt_data] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_0_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_0_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_data] ad_connect util_bsplit_rx_0_gt_data/data axi_ad9625_0_gt/rx_gt_data ad_connect util_bsplit_rx_0_gt_data/split_data_0 axi_ad9625_0_jesd/gt0_rxdata @@ -169,8 +169,8 @@ ad_connect axi_ad9625_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame ad_connect axi_ad9625_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_1_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_1_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_1_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_charisk] ad_connect util_bsplit_rx_1_gt_charisk/data axi_ad9625_1_gt/rx_gt_charisk ad_connect util_bsplit_rx_1_gt_charisk/split_data_0 axi_ad9625_1_jesd/gt0_rxcharisk @@ -183,8 +183,8 @@ ad_connect util_bsplit_rx_1_gt_charisk/split_data_6 axi_ad9625_1_jesd/gt6_rxcha ad_connect util_bsplit_rx_1_gt_charisk/split_data_7 axi_ad9625_1_jesd/gt7_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_1_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_1_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_1_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_disperr] ad_connect util_bsplit_rx_1_gt_disperr/data axi_ad9625_1_gt/rx_gt_disperr ad_connect util_bsplit_rx_1_gt_disperr/split_data_0 axi_ad9625_1_jesd/gt0_rxdisperr @@ -197,8 +197,8 @@ ad_connect util_bsplit_rx_1_gt_disperr/split_data_6 axi_ad9625_1_jesd/gt6_rxdis ad_connect util_bsplit_rx_1_gt_disperr/split_data_7 axi_ad9625_1_jesd/gt7_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_1_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_1_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_1_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_notintable] ad_connect util_bsplit_rx_1_gt_notintable/data axi_ad9625_1_gt/rx_gt_notintable ad_connect util_bsplit_rx_1_gt_notintable/split_data_0 axi_ad9625_1_jesd/gt0_rxnotintable @@ -211,8 +211,8 @@ ad_connect util_bsplit_rx_1_gt_notintable/split_data_6 axi_ad9625_1_jesd/gt6_rx ad_connect util_bsplit_rx_1_gt_notintable/split_data_7 axi_ad9625_1_jesd/gt7_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_1_gt_data] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_1_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_1_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_data] ad_connect util_bsplit_rx_1_gt_data/data axi_ad9625_1_gt/rx_gt_data ad_connect util_bsplit_rx_1_gt_data/split_data_0 axi_ad9625_1_jesd/gt0_rxdata diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index a13db2ab9..c64390514 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -51,32 +51,32 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9250_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9250_gt set axi_ad9250_0_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_0_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_0_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_0_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_0_dma set axi_ad9250_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_1_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma # constants for avoiding errors when validating bd @@ -118,8 +118,8 @@ ad_connect axi_ad9250_gt_rx_rst axi_ad9250_jesd/rx_reset ad_connect axi_ad9250_gt_rx_sysref axi_ad9250_jesd/rx_sysref create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_ad9250_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk @@ -128,8 +128,8 @@ ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9250_jesd/gt2_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9250_jesd/gt3_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_disperr] ad_connect util_bsplit_rx_gt_disperr/data axi_ad9250_gt/rx_gt_disperr ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr @@ -138,8 +138,8 @@ ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9250_jesd/gt2_rxdisperr ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9250_jesd/gt3_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_ad9250_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable @@ -148,8 +148,8 @@ ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9250_jesd/gt2_rxnoti ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9250_jesd/gt3_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_ad9250_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 58a5385d8..caca7d537 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -28,39 +28,39 @@ set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122] set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_FIFO_SIZE {16}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9122_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma + set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma + set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma + set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9122_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9122_dma + set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma + set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9122_dma + set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9122_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122] - set_property -dict [list CONFIG.CH_DW {64} CONFIG.CH_CNT {2}] $util_upack_ad9122 + set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122 # adc peripherals set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643] set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_FIFO_SIZE {16}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9643_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma + set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9643_dma + set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9643_dma + set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9643_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9643_dma + set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9643_dma + set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9643_dma + set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9643_dma + set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9643_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma set util_cpack_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9643] - set_property -dict [list CONFIG.CH_DW {32} CONFIG.CH_CNT {2}] $util_cpack_ad9643 + set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32} CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9643 set util_ad9643_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9643_adc_fifo] set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9643_adc_fifo - set_property -dict [list CONFIG.DIN_ADDR_WIDTH {4}] $util_ad9643_adc_fifo + set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9643_adc_fifo set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9643_adc_fifo set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $util_ad9643_adc_fifo diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index ce8b68fe6..4fa14c8ff 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -25,7 +25,7 @@ create_bd_port -dir I tdd_sync_in # ad9361 core set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361 +set_property -dict [list CONFIG.ID {0}] $axi_ad9361 set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma @@ -34,15 +34,15 @@ set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack] -set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_dac_upack -set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma @@ -51,19 +51,19 @@ set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack] -set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_adc_pack -set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo] set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo -set_property -dict [list CONFIG.DIN_ADDR_WIDTH {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo diff --git a/projects/fmcomms2/rfsom/system_bd.tcl b/projects/fmcomms2/rfsom/system_bd.tcl index 12ccf242a..90271b0a3 100644 --- a/projects/fmcomms2/rfsom/system_bd.tcl +++ b/projects/fmcomms2/rfsom/system_bd.tcl @@ -3,5 +3,5 @@ source $ad_hdl_dir/projects/common/rfsom/rfsom_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl source ../common/fmcomms2_bd.tcl -set_property -dict [list CONFIG.PCORE_DAC_IODELAY_ENABLE {1}] $axi_ad9361 +set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361 diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index 469dabddd..060306f12 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -36,49 +36,49 @@ create_bd_port -dir O sys_100m_resetn # instances set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0] -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361_0 -set_property -dict [list CONFIG.PCORE_IODELAY_GROUP {dev_0_if_delay_group}] $axi_ad9361_0 +set_property -dict [list CONFIG.ID {0}] $axi_ad9361_0 +set_property -dict [list CONFIG.IO_DELAY_GROUP {dev_0_if_delay_group}] $axi_ad9361_0 set axi_ad9361_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_1] -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9361_1 -set_property -dict [list CONFIG.PCORE_IODELAY_GROUP {dev_1_if_delay_group}] $axi_ad9361_1 +set_property -dict [list CONFIG.ID {1}] $axi_ad9361_1 +set_property -dict [list CONFIG.IO_DELAY_GROUP {dev_1_if_delay_group}] $axi_ad9361_1 set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma if {$sys_zynq == 1} { - set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9361_dac_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_dac_dma + set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9361_dac_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_dac_dma } set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma if {$sys_zynq == 1} { - set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9361_adc_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_adc_dma + set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9361_adc_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_adc_dma } set util_adc_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0] diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl index c96531fe6..bfb64a984 100644 --- a/projects/fmcomms6/common/fmcomms6_bd.tcl +++ b/projects/fmcomms6/common/fmcomms6_bd.tcl @@ -25,12 +25,12 @@ create_bd_port -dir I -from 31 -to 0 adc_ddata set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi_ad9652] set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9652_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9652_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9652_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9652_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma -set_property -dict [list CONFIG.C_FIFO_SIZE {8}] $axi_ad9652_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9652_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma +set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma # connections (adc) @@ -42,7 +42,7 @@ ad_connect adc_or_in_p axi_ad9652/adc_or_in_p ad_connect adc_or_in_n axi_ad9652/adc_or_in_n ad_connect adc_data_in_p axi_ad9652/adc_data_in_p ad_connect adc_data_in_n axi_ad9652/adc_data_in_n -ad_connect axi_ad9652/adc_clk adc_clk +ad_connect axi_ad9652/adc_clk adc_clk ad_connect axi_ad9652/adc_clk sys_wfifo/adc_clk ad_connect axi_ad9652/adc_dovf sys_wfifo/adc_wovf ad_connect sys_200m_clk sys_wfifo/dma_clk diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index e4d59be5c..e853989e7 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -51,24 +51,24 @@ create_bd_port -dir I spi2_sdi_i # dac peripherals set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] -set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {1}] $axi_ad9144_core +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9144_dma +set_property -dict [list CONFIG.ID {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma # adc peripherals @@ -81,10 +81,10 @@ set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma @@ -120,7 +120,7 @@ ad_connect spi2_clk_o axi_fmcomms7_spi/sck_o ad_connect spi2_sdo_i axi_fmcomms7_spi/io0_i ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i -ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk +ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk # connections (gt) @@ -145,32 +145,32 @@ ad_connect axi_fmcomms7_gt/tx_rst axi_ad9144_jesd/tx_reset ad_connect axi_fmcomms7_gt/tx_sysref axi_ad9144_jesd/tx_sysref create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_ccat_tx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_ccat_tx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_ccat_tx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_ccat_tx_gt_charisk] -ad_connect util_ccat_tx_gt_charisk/ccat_data axi_fmcomms7_gt/tx_gt_charisk -ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9144_jesd/gt0_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9144_jesd/gt1_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9144_jesd/gt2_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9144_jesd/gt3_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_4 axi_ad9144_jesd/gt4_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_5 axi_ad9144_jesd/gt5_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_6 axi_ad9144_jesd/gt6_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_7 axi_ad9144_jesd/gt7_txcharisk +ad_connect util_ccat_tx_gt_charisk/ccat_data axi_fmcomms7_gt/tx_gt_charisk +ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9144_jesd/gt0_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9144_jesd/gt1_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9144_jesd/gt2_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9144_jesd/gt3_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_4 axi_ad9144_jesd/gt4_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_5 axi_ad9144_jesd/gt5_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_6 axi_ad9144_jesd/gt6_txcharisk +ad_connect util_ccat_tx_gt_charisk/data_7 axi_ad9144_jesd/gt7_txcharisk create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_ccat_tx_gt_data] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_ccat_tx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_ccat_tx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_ccat_tx_gt_data] -ad_connect util_ccat_tx_gt_data/ccat_data axi_fmcomms7_gt/tx_gt_data -ad_connect util_ccat_tx_gt_data/data_0 axi_ad9144_jesd/gt0_txdata -ad_connect util_ccat_tx_gt_data/data_1 axi_ad9144_jesd/gt1_txdata -ad_connect util_ccat_tx_gt_data/data_2 axi_ad9144_jesd/gt2_txdata -ad_connect util_ccat_tx_gt_data/data_3 axi_ad9144_jesd/gt3_txdata -ad_connect util_ccat_tx_gt_data/data_4 axi_ad9144_jesd/gt4_txdata -ad_connect util_ccat_tx_gt_data/data_5 axi_ad9144_jesd/gt5_txdata -ad_connect util_ccat_tx_gt_data/data_6 axi_ad9144_jesd/gt6_txdata -ad_connect util_ccat_tx_gt_data/data_7 axi_ad9144_jesd/gt7_txdata +ad_connect util_ccat_tx_gt_data/ccat_data axi_fmcomms7_gt/tx_gt_data +ad_connect util_ccat_tx_gt_data/data_0 axi_ad9144_jesd/gt0_txdata +ad_connect util_ccat_tx_gt_data/data_1 axi_ad9144_jesd/gt1_txdata +ad_connect util_ccat_tx_gt_data/data_2 axi_ad9144_jesd/gt2_txdata +ad_connect util_ccat_tx_gt_data/data_3 axi_ad9144_jesd/gt3_txdata +ad_connect util_ccat_tx_gt_data/data_4 axi_ad9144_jesd/gt4_txdata +ad_connect util_ccat_tx_gt_data/data_5 axi_ad9144_jesd/gt5_txdata +ad_connect util_ccat_tx_gt_data/data_6 axi_ad9144_jesd/gt6_txdata +ad_connect util_ccat_tx_gt_data/data_7 axi_ad9144_jesd/gt7_txdata ad_connect axi_fmcomms7_gt/tx_rst_done axi_ad9144_jesd/tx_reset_done ad_connect axi_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync @@ -205,8 +205,8 @@ ad_connect axi_fmcomms7_gt/rx_rst axi_ad9680_jesd/rx_reset ad_connect axi_fmcomms7_gt/rx_sysref axi_ad9680_jesd/rx_sysref create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_fmcomms7_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9680_jesd/gt0_rxcharisk @@ -215,8 +215,8 @@ ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9680_jesd/gt2_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9680_jesd/gt3_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_disperr] ad_connect util_bsplit_rx_gt_disperr/data axi_fmcomms7_gt/rx_gt_disperr ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9680_jesd/gt0_rxdisperr @@ -225,8 +225,8 @@ ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9680_jesd/gt2_rxdisperr ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9680_jesd/gt3_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_fmcomms7_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9680_jesd/gt0_rxnotintable @@ -235,8 +235,8 @@ ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9680_jesd/gt2_rxnoti ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9680_jesd/gt3_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_fmcomms7_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9680_jesd/gt0_rxdata @@ -256,12 +256,12 @@ ad_connect axi_ad9680_core/adc_data_0 adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 adc_data_1 -ad_connect axi_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect axi_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf ad_connect adc_dwr axi_ad9680_fifo/adc_wr ad_connect adc_ddata axi_ad9680_fifo/adc_wdata -ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk +ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl index 87ef6782c..53da7c749 100644 --- a/projects/imageon/common/imageon_bd.tcl +++ b/projects/imageon/common/imageon_bd.tcl @@ -5,7 +5,7 @@ create_bd_port -dir I spdif_rx # adv7511 (reconfigure base design) -set_property CONFIG.PCORE_EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core] +set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core] create_bd_port -dir O -from 15 -to 0 hdmi_es_data ad_connect hdmi_es_data axi_hdmi_core/hdmi_16_es_data @@ -31,19 +31,19 @@ ad_cpu_interrupt ps-11 mb-11 axi_iic_imageon/iic2intc_irpt set axi_hdmi_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_rx:1.0 axi_hdmi_rx_core] set axi_hdmi_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_hdmi_rx_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.2D_TRANSFER {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma ad_connect hdmi_rx_clk axi_hdmi_rx_core/hdmi_rx_clk ad_connect hdmi_rx_data axi_hdmi_rx_core/hdmi_rx_data @@ -55,7 +55,7 @@ ad_connect axi_hdmi_rx_core/hdmi_dma_data axi_hdmi_rx_dma/fifo_wr_din ad_connect axi_hdmi_rx_core/hdmi_dma_ovf axi_hdmi_rx_dma/fifo_wr_overflow set axi_spdif_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_rx:1.0 axi_spdif_rx_core] -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_rx_core +set_property -dict [list CONFIG.C_S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_rx_core set_property -dict [list CONFIG.PCW_USE_DMA3 {1}] $sys_ps7 set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_rx_core diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 29aa1313c..05426e1e9 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -92,93 +92,93 @@ set speed_detector_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m1 ] # dma motor 1 set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m1_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $speed_detector_m1_dma + set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.CYCLIC {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma + set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $speed_detector_m1_dma # speed detector core motor 2 set speed_detector_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m2 ] # dma motor 2 set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m2_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $speed_detector_m2_dma + set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.CYCLIC {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma + set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $speed_detector_m2_dma # current monitor peripherals # current monitor core motor 1 set current_monitor_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m1 ] # dma motor 1 set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ] - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m1_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m1_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m1_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m1_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.CYCLIC {0}] $current_monitor_m1_dma # data packer motor 1 # set current_monitor_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m1_apack] - set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m1_apack + set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $current_monitor_m1_apack # set current_monitor_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m1_pack ] -# set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m1_pack -# set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m1_pack +# set_property -dict [ list CONFIG.NUM_OF_CHANNELS {4} ] $current_monitor_m1_pack +# set_property -dict [ list CONFIG.CHANNEL_DATA_WIDTH {16} ] $current_monitor_m1_pack # current monitor core motor 2 set current_monitor_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m2 ] # dma motor 2 set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ] - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m2_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m2_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m2_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m2_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.CYCLIC {0}] $current_monitor_m2_dma # data packer motor 2 set current_monitor_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m2_apack] - set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m2_apack + set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $current_monitor_m2_apack #set current_monitor_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m2_pack ] - #set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m2_pack - #set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m2_pack + #set_property -dict [ list CONFIG.NUM_OF_CHANNELS {4} ] $current_monitor_m2_pack + #set_property -dict [ list CONFIG.CHANNEL_DATA_WIDTH {16} ] $current_monitor_m2_pack #controller # controller core motor 1 set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ] # dma motor 1 set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ] - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m1_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m1_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $controller_m1_dma + set_property -dict [list CONFIG.CYCLIC {0}] $controller_m1_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma # data packer motor 1 set controller_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m1_apack] - set_property -dict [list CONFIG.CHANNELS {8}] $controller_m1_apack + set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $controller_m1_apack set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m1_apack #set controller_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m1_pack ] - #set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m1_pack - #set_property -dict [ list CONFIG.CH_DW {32} ] $controller_m1_pack + #set_property -dict [ list CONFIG.NUM_OF_CHANNELS {8} ] $controller_m1_pack + #set_property -dict [ list CONFIG.CHANNEL_DATA_WIDTH {32} ] $controller_m1_pack # controller core motor 2 set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ] # dma motor 2 set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ] - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m2_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m2_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma + set_property -dict [list CONFIG.2D_TRANSFER {0}] $controller_m2_dma + set_property -dict [list CONFIG.CYCLIC {0}] $controller_m2_dma + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma # data packer motor 2 #set controller_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m2_pack ] - #set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m2_pack + #set_property -dict [ list CONFIG.NUM_OF_CHANNELS {8} ] $controller_m2_pack set controller_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m2_apack] - set_property -dict [list CONFIG.CHANNELS {8}] $controller_m2_apack + set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $controller_m2_apack set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m2_apack #ethernet gmii to rgmii converters diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 28f813bcf..47654fc27 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -48,20 +48,20 @@ create_bd_port -dir O adc_dovf # adc peripherals set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_0 -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9671_core_0 +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_0 +set_property -dict [list CONFIG.ID {0}] $axi_ad9671_core_0 set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_1 -set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9671_core_1 +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_1 +set_property -dict [list CONFIG.ID {1}] $axi_ad9671_core_1 set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_2 -set_property -dict [list CONFIG.PCORE_ID {2}] $axi_ad9671_core_2 +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_2 +set_property -dict [list CONFIG.ID {2}] $axi_ad9671_core_2 set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_3 -set_property -dict [list CONFIG.PCORE_ID {3}] $axi_ad9671_core_3 +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3 +set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3 set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd @@ -78,18 +78,18 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_usdrx1_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.ID {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma +set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_usdrx1_spi] set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi @@ -129,8 +129,8 @@ ad_connect axi_usdrx1_gt/rx_jesd_rst axi_usdrx1_jesd/rx_reset ad_connect axi_usdrx1_gt/rx_sysref axi_usdrx1_jesd/rx_sysref create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_charisk] ad_connect util_bsplit_rx_gt_charisk/data axi_usdrx1_gt/rx_gt_charisk ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_usdrx1_jesd/gt0_rxcharisk @@ -143,8 +143,8 @@ ad_connect util_bsplit_rx_gt_charisk/split_data_6 axi_usdrx1_jesd/gt6_rxcharisk ad_connect util_bsplit_rx_gt_charisk/split_data_7 axi_usdrx1_jesd/gt7_rxcharisk create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_disperr] ad_connect util_bsplit_rx_gt_disperr/data axi_usdrx1_gt/rx_gt_disperr ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_usdrx1_jesd/gt0_rxdisperr @@ -157,8 +157,8 @@ ad_connect util_bsplit_rx_gt_disperr/split_data_6 axi_usdrx1_jesd/gt6_rxdisperr ad_connect util_bsplit_rx_gt_disperr/split_data_7 axi_usdrx1_jesd/gt7_rxdisperr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_notintable] ad_connect util_bsplit_rx_gt_notintable/data axi_usdrx1_gt/rx_gt_notintable ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_usdrx1_jesd/gt0_rxnotintable @@ -171,8 +171,8 @@ ad_connect util_bsplit_rx_gt_notintable/split_data_6 axi_usdrx1_jesd/gt6_rxnoti ad_connect util_bsplit_rx_gt_notintable/split_data_7 axi_usdrx1_jesd/gt7_rxnotintable create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_data] ad_connect util_bsplit_rx_gt_data/data axi_usdrx1_gt/rx_gt_data ad_connect util_bsplit_rx_gt_data/split_data_0 axi_usdrx1_jesd/gt0_rxdata