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hdl/library: Update the IP parameters 

The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
main
Istvan Csomortani 2015-08-19 14:11:47 +03:00
parent 549801cf2e
commit 57cfb7cfb1
208 changed files with 2270 additions and 2270 deletions
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12
library/axi_ad6676/axi_ad6676.v
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@ -81,9 +81,9 @@ module axi_ad6676 (
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
@ -204,7 +204,7 @@ module axi_ad6676 (
// channel
axi_ad6676_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
@ -227,7 +227,7 @@ module axi_ad6676 (
// channel
axi_ad6676_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
@ -250,7 +250,7 @@ module axi_ad6676 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

6
library/axi_ad6676/axi_ad6676_channel.v
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@ -72,8 +72,8 @@ module axi_ad6676_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
@ -120,7 +120,7 @@ module axi_ad6676_channel (
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

20
library/axi_ad9122/axi_ad9122.v
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@ -91,12 +91,12 @@ module axi_ad9122 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter DAC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// dac interface
@ -198,9 +198,9 @@ module axi_ad9122 (
// device interface
axi_ad9122_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_SERDES_DDR_N (PCORE_SERDES_DDR_N),
.PCORE_MMCM_BUFIO_N (PCORE_MMCM_BUFIO_N))
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N))
i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
@ -243,7 +243,7 @@ module axi_ad9122 (
// core
axi_ad9122_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
axi_ad9122_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s),

14
library/axi_ad9122/axi_ad9122_channel.v
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@ -71,8 +71,8 @@ module axi_ad9122_channel (
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -184,7 +184,7 @@ module axi_ad9122_channel (
end
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -199,7 +199,7 @@ module axi_ad9122_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
@ -214,7 +214,7 @@ module axi_ad9122_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
@ -229,7 +229,7 @@ module axi_ad9122_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
@ -245,7 +245,7 @@ module axi_ad9122_channel (
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),

16
library/axi_ad9122/axi_ad9122_core.v
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@ -106,8 +106,8 @@ module axi_ad9122_core (
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -202,7 +202,7 @@ module axi_ad9122_core (
// master/slave (clocks must be synchronous)
assign dac_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in;
assign dac_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
// processor read interface
@ -221,8 +221,8 @@ module axi_ad9122_core (
// dac channel
axi_ad9122_channel #(
.CHID(0),
.DP_DISABLE(DP_DISABLE))
.CHANNEL_ID(0),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
@ -247,8 +247,8 @@ module axi_ad9122_core (
// dac channel
axi_ad9122_channel #(
.CHID(1),
.DP_DISABLE(DP_DISABLE))
.CHANNEL_ID(1),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
@ -272,7 +272,7 @@ module axi_ad9122_core (
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
up_dac_common #(.ID(ID)) i_up_dac_common (
.mmcm_rst (mmcm_rst),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),

26
library/axi_ad9122/axi_ad9122_if.v
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@ -97,10 +97,10 @@ module axi_ad9122_if (
// parameters
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_IODELAY_GROUP = "dac_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter IO_DELAY_GROUP = "dac_if_delay_group";
// dac interface
@ -176,8 +176,8 @@ module axi_ad9122_if (
// dac data output serdes(s) & buffers
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N(SERDES_OR_DDR_N),
.DATA_WIDTH(16))
i_serdes_out_data (
.rst (dac_rst),
@ -197,8 +197,8 @@ module axi_ad9122_if (
// dac frame output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N(SERDES_OR_DDR_N),
.DATA_WIDTH(1))
i_serdes_out_frame (
.rst (dac_rst),
@ -218,8 +218,8 @@ module axi_ad9122_if (
// dac clock output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N(SERDES_OR_DDR_N),
.DATA_WIDTH(1))
i_serdes_out_clk (
.rst (dac_rst),
@ -239,9 +239,9 @@ module axi_ad9122_if (
// dac clock input buffers
ad_serdes_clk #(
.SERDES (PCORE_SERDES_DDR_N),
.MMCM (PCORE_MMCM_BUFIO_N),
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (1.667),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),

12
library/axi_ad9144/axi_ad9144.v
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@ -91,15 +91,15 @@ module axi_ad9144 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_QUAD_DUAL_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter ID = 0;
parameter QUAD_OR_DUAL_N = 1;
parameter DAC_DATAPATH_DISABLE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [(128*PCORE_QUAD_DUAL_N)+127:0] tx_data;
output [(128*QUAD_OR_DUAL_N)+127:0] tx_data;
// dma interface
@ -184,7 +184,7 @@ module axi_ad9144 (
// dual/quad cores
assign tx_data = (PCORE_QUAD_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0];
assign tx_data = (QUAD_OR_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0];
// device interface
@ -212,7 +212,7 @@ module axi_ad9144 (
// core
axi_ad9144_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
axi_ad9144_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),

14
library/axi_ad9144/axi_ad9144_channel.v
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@ -69,8 +69,8 @@ module axi_ad9144_channel (
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -495,7 +495,7 @@ module axi_ad9144_channel (
end
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -510,7 +510,7 @@ module axi_ad9144_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
@ -525,7 +525,7 @@ module axi_ad9144_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
@ -540,7 +540,7 @@ module axi_ad9144_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
@ -556,7 +556,7 @@ module axi_ad9144_channel (
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),

14
library/axi_ad9144/axi_ad9144_core.v
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@ -94,8 +94,8 @@ module axi_ad9144_core (
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -197,7 +197,7 @@ module axi_ad9144_core (
// dac channel
axi_ad9144_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 (
axi_ad9144_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0),
@ -218,7 +218,7 @@ module axi_ad9144_core (
// dac channel
axi_ad9144_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 (
axi_ad9144_channel #(.CHANNEL_ID(1), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1),
@ -239,7 +239,7 @@ module axi_ad9144_core (
// dac channel
axi_ad9144_channel #(.CHID(2), .DP_DISABLE(DP_DISABLE)) i_channel_2 (
axi_ad9144_channel #(.CHANNEL_ID(2), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_2),
@ -260,7 +260,7 @@ module axi_ad9144_core (
// dac channel
axi_ad9144_channel #(.CHID(3), .DP_DISABLE(DP_DISABLE)) i_channel_3 (
axi_ad9144_channel #(.CHANNEL_ID(3), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_3),
@ -281,7 +281,7 @@ module axi_ad9144_core (
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
up_dac_common #(.ID(ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),

30
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -36,19 +36,19 @@ add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter PCORE_QUAD_DUAL_N INTEGER 0
set_parameter_property PCORE_QUAD_DUAL_N DEFAULT_VALUE 0
set_parameter_property PCORE_QUAD_DUAL_N DISPLAY_NAME PCORE_QUAD_DUAL_N
set_parameter_property PCORE_QUAD_DUAL_N TYPE INTEGER
set_parameter_property PCORE_QUAD_DUAL_N UNITS None
set_parameter_property PCORE_QUAD_DUAL_N HDL_PARAMETER true
add_parameter QUAD_OR_DUAL_N INTEGER 0
set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0
set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
set_parameter_property QUAD_OR_DUAL_N UNITS None
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
# axi4 slave
@ -85,7 +85,7 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
ad_alt_intf clock tx_clk input 1
ad_alt_intf signal tx_data output 128*(PCORE_QUAD_DUAL_N+1) data
ad_alt_intf signal tx_data output 128*(QUAD_OR_DUAL_N+1) data
# dma interface
@ -101,9 +101,9 @@ ad_alt_intf signal dac_dunf input 1
proc p_axi_ad9144 {} {
set p_pcore_quad_dual_n [get_parameter_value "PCORE_QUAD_DUAL_N"]
set p_pcore_quad_dual_n [get_parameter_value "QUAD_OR_DUAL_N"]
if {[get_parameter_value PCORE_QUAD_DUAL_N] == 1} {
if {[get_parameter_value QUAD_OR_DUAL_N] == 1} {
ad_alt_intf signal dac_valid_2 output 1
ad_alt_intf signal dac_enable_2 output 1
ad_alt_intf signal dac_ddata_2 input 64 dac_data_2

6
library/axi_ad9152/axi_ad9152.v
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@ -83,8 +83,8 @@ module axi_ad9152 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter ID = 0;
parameter DAC_DATAPATH_DISABLE = 0;
// jesd interface
// tx_clk is (line-rate/40)
@ -174,7 +174,7 @@ module axi_ad9152 (
// core
axi_ad9152_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
axi_ad9152_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),

14
library/axi_ad9152/axi_ad9152_channel.v
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@ -69,8 +69,8 @@ module axi_ad9152_channel (
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -495,7 +495,7 @@ module axi_ad9152_channel (
end
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -510,7 +510,7 @@ module axi_ad9152_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
@ -525,7 +525,7 @@ module axi_ad9152_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
@ -540,7 +540,7 @@ module axi_ad9152_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
@ -556,7 +556,7 @@ module axi_ad9152_channel (
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),

10
library/axi_ad9152/axi_ad9152_core.v
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@ -80,8 +80,8 @@ module axi_ad9152_core (
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -163,7 +163,7 @@ module axi_ad9152_core (
// dac channel
axi_ad9152_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 (
axi_ad9152_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0),
@ -184,7 +184,7 @@ module axi_ad9152_core (
// dac channel
axi_ad9152_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 (
axi_ad9152_channel #(.CHANNEL_ID(1), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1),
@ -205,7 +205,7 @@ module axi_ad9152_core (
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
up_dac_common #(.ID(ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),

12
library/axi_ad9234/axi_ad9234.v
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@ -81,9 +81,9 @@ module axi_ad9234 (
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
@ -204,7 +204,7 @@ module axi_ad9234 (
// channel
axi_ad9234_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
axi_ad9234_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
@ -227,7 +227,7 @@ module axi_ad9234 (
// channel
axi_ad9234_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
axi_ad9234_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
@ -250,7 +250,7 @@ module axi_ad9234 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

6
library/axi_ad9234/axi_ad9234_channel.v
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@ -72,8 +72,8 @@ module axi_ad9234_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
@ -120,7 +120,7 @@ module axi_ad9234_channel (
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

12
library/axi_ad9250/axi_ad9250.v
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@ -83,9 +83,9 @@ module axi_ad9250 (
s_axi_rresp,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
@ -208,7 +208,7 @@ module axi_ad9250 (
// channel
axi_ad9250_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
axi_ad9250_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
@ -231,7 +231,7 @@ module axi_ad9250 (
// channel
axi_ad9250_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
axi_ad9250_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
@ -254,7 +254,7 @@ module axi_ad9250 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

6
library/axi_ad9250/axi_ad9250_channel.v
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@ -72,8 +72,8 @@ module axi_ad9250_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
@ -136,7 +136,7 @@ module axi_ad9250_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

24
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -32,19 +32,19 @@ add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# axi4 slave

20
library/axi_ad9265/axi_ad9265.v
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@ -88,10 +88,10 @@ module axi_ad9265 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
@ -203,8 +203,8 @@ module axi_ad9265 (
// channel
axi_ad9265_channel #(
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
.CHANNEL_ID(0),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -230,8 +230,8 @@ module axi_ad9265 (
// main (device interface)
axi_ad9265_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
.DEVICE_TYPE (DEVICE_TYPE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
@ -253,7 +253,7 @@ module axi_ad9265 (
// adc delay control
up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
@ -273,7 +273,7 @@ module axi_ad9265 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

10
library/axi_ad9265/axi_ad9265_channel.v
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@ -73,8 +73,8 @@ module axi_ad9265_channel (
// parameters
parameter CHID = 0;
parameter DP_DISABLE = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
@ -128,7 +128,7 @@ module axi_ad9265_channel (
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_data_s = adc_data;
end else begin
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
@ -144,7 +144,7 @@ module axi_ad9265_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
@ -159,7 +159,7 @@ module axi_ad9265_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

14
library/axi_ad9265/axi_ad9265_if.v
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@ -70,8 +70,8 @@ module axi_ad9265_if (
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
@ -131,9 +131,9 @@ module axi_ad9265_if (
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
@ -153,9 +153,9 @@ module axi_ad9265_if (
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
@ -173,7 +173,7 @@ module axi_ad9265_if (
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),

28
library/axi_ad9361/axi_ad9361.v
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@ -153,12 +153,12 @@ module axi_ad9361 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_DAC_IODELAY_ENABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
parameter DAC_DATAPATH_DISABLE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
// physical interface (receive)
@ -346,9 +346,9 @@ module axi_ad9361 (
// device interface
axi_ad9361_dev_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_DAC_IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
.DEVICE_TYPE (DEVICE_TYPE),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_dev_if (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
@ -386,7 +386,7 @@ module axi_ad9361 (
// TDD interface
axi_ad9361_tdd_if #(.MODE_OF_ENABLE(1)) i_tdd_if(
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if(
.clk(clk),
.rst(rst),
.tdd_rx_vco_en(tdd_rx_vco_en_s),
@ -444,8 +444,8 @@ module axi_ad9361 (
// receive
axi_ad9361_rx #(
.PCORE_ID (PCORE_ID),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx (
.adc_rst (rst),
.adc_clk (clk),
@ -491,8 +491,8 @@ module axi_ad9361 (
// transmit
axi_ad9361_tx #(
.PCORE_ID (PCORE_ID),
.DP_DISABLE (PCORE_DAC_DP_DISABLE))
.ID (ID),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.dac_clk (clk),
.dac_valid (dac_valid_s),

34
library/axi_ad9361/axi_ad9361_dev_if.v
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@ -94,9 +94,9 @@ module axi_ad9361_dev_if (
// this parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_DAC_IODELAY_ENABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
localparam PCORE_7SERIES = 0;
localparam PCORE_VIRTEX6 = 1;
@ -377,9 +377,9 @@ module axi_ad9361_dev_if (
generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
ad_lvds_in #(
.BUFTYPE (PCORE_DEVICE_TYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data (
.rx_clk (l_clk),
.rx_data_in_p (rx_data_in_p[l_inst]),
@ -399,9 +399,9 @@ module axi_ad9361_dev_if (
// receive frame interface, ibuf -> idelay -> iddr
ad_lvds_in #(
.BUFTYPE (PCORE_DEVICE_TYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame (
.rx_clk (l_clk),
.rx_data_in_p (rx_frame_in_p),
@ -421,10 +421,10 @@ module axi_ad9361_dev_if (
generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
ad_lvds_out #(
.BUFTYPE (PCORE_DEVICE_TYPE),
.IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]),
@ -444,10 +444,10 @@ module axi_ad9361_dev_if (
// transmit frame interface, oddr -> obuf
ad_lvds_out #(
.BUFTYPE (PCORE_DEVICE_TYPE),
.IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_p_frame),
@ -465,10 +465,10 @@ module axi_ad9361_dev_if (
// transmit clock interface, oddr -> obuf
ad_lvds_out #(
.BUFTYPE (PCORE_DEVICE_TYPE),
.IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (1'b0),
@ -486,7 +486,7 @@ module axi_ad9361_dev_if (
// device clock interface (receive clock)
ad_lvds_clk #(
.BUFTYPE (PCORE_DEVICE_TYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_clk (
.clk_in_p (rx_clk_in_p),
.clk_in_n (rx_clk_in_n),

6
library/axi_ad9361/axi_ad9361_dev_if_alt.v
View File

@ -96,9 +96,9 @@ module axi_ad9361_dev_if (
// this parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_DAC_IODELAY_ENABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
localparam PCORE_7SERIES = 0;
localparam PCORE_VIRTEX6 = 1;

24
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -53,19 +53,19 @@ add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FI
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# axi4 slave

32
library/axi_ad9361/axi_ad9361_rx.v
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@ -99,8 +99,8 @@ module axi_ad9361_rx (
// parameters
parameter DP_DISABLE = 0;
parameter PCORE_ID = 0;
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
// adc interface
@ -205,9 +205,9 @@ module axi_ad9361_rx (
// channel 0 (i)
axi_ad9361_rx_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (DP_DISABLE))
.Q_OR_I_N(0),
.CHANNEL_ID(0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -238,9 +238,9 @@ module axi_ad9361_rx (
// channel 1 (q)
axi_ad9361_rx_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (DP_DISABLE))
.Q_OR_I_N(1),
.CHANNEL_ID(1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -271,9 +271,9 @@ module axi_ad9361_rx (
// channel 2 (i)
axi_ad9361_rx_channel #(
.IQSEL(0),
.CHID(2),
.DP_DISABLE (DP_DISABLE))
.Q_OR_I_N(0),
.CHANNEL_ID(2),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -304,9 +304,9 @@ module axi_ad9361_rx (
// channel 3 (q)
axi_ad9361_rx_channel #(
.IQSEL(1),
.CHID(3),
.DP_DISABLE (DP_DISABLE))
.Q_OR_I_N(1),
.CHANNEL_ID(3),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -336,7 +336,7 @@ module axi_ad9361_rx (
// common processor control
up_adc_common #(.PCORE_ID (PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID (ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -377,7 +377,7 @@ module axi_ad9361_rx (
// adc delay control
up_delay_cntrl #(.IO_WIDTH(7), .IO_BASEADDR(6'h02)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(7), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

18
library/axi_ad9361/axi_ad9361_rx_channel.v
View File

@ -78,9 +78,9 @@ module axi_ad9361_rx_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
@ -142,7 +142,7 @@ module axi_ad9361_rx_channel (
assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data;
assign adc_dcfilter_data_out = adc_dcfilter_data_s;
axi_ad9361_rx_pnmon #(.IQSEL (IQSEL), .PRBS_SEL (CHID)) i_rx_pnmon (
axi_ad9361_rx_pnmon #(.Q_OR_I_N (Q_OR_I_N), .PRBS_SEL (CHANNEL_ID)) i_rx_pnmon (
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data_i (adc_data),
@ -152,7 +152,7 @@ module axi_ad9361_rx_channel (
.adc_pn_err (adc_pn_err_s));
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_valid_s = adc_valid;
assign adc_dfmt_data_s = {4'd0, adc_data_s};
end else begin
@ -169,7 +169,7 @@ module axi_ad9361_rx_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
assign adc_dcfilter_data_s = adc_dfmt_data_s;
end else begin
@ -186,11 +186,11 @@ module axi_ad9361_rx_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_iqcor_valid = adc_dcfilter_valid_s;
assign adc_iqcor_data = adc_dcfilter_data_s;
end else begin
ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor (
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s),
.data_in (adc_dcfilter_data_s),
@ -203,7 +203,7 @@ module axi_ad9361_rx_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID (CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

6
library/axi_ad9361/axi_ad9361_rx_pnmon.v
View File

@ -57,7 +57,7 @@ module axi_ad9361_rx_pnmon (
// parameters
parameter IQSEL = 0;
parameter Q_OR_I_N = 0;
parameter PRBS_SEL = 0;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
@ -255,8 +255,8 @@ module axi_ad9361_rx_pnmon (
// device specific, assuming lower nibble is lost-
assign adc_pn0_data_i_s = (IQSEL == 1) ? adc_data_q : adc_data_i;
assign adc_pn0_data_q_s = (IQSEL == 1) ? adc_data_i : adc_data_q;
assign adc_pn0_data_i_s = (Q_OR_I_N == 1) ? adc_data_q : adc_data_i;
assign adc_pn0_data_q_s = (Q_OR_I_N == 1) ? adc_data_i : adc_data_q;
assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s);
assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]};
assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;

4
library/axi_ad9361/axi_ad9361_tdd_if.v
View File

@ -65,7 +65,7 @@ module axi_ad9361_tdd_if(
// parameters
parameter MODE_OF_ENABLE = 0;
parameter LEVEL_OR_PULSE_N = 0; // the control signals are edge (pulse) or level sensitive
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
@ -111,7 +111,7 @@ module axi_ad9361_tdd_if(
tdd_tx_rf_en_d <= tdd_tx_rf_en;
end
assign ad9361_enable_s = (MODE_OF_ENABLE == PULSE_MODE) ?
assign ad9361_enable_s = (LEVEL_OR_PULSE_N == PULSE_MODE) ?
((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) |
(~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) :
(tdd_rx_rf_en | tdd_tx_rf_en);

34
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -100,8 +100,8 @@ module axi_ad9361_tx (
// parameters
parameter DP_DISABLE = 0;
parameter PCORE_ID = 0;
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
// dac interface
@ -189,7 +189,7 @@ module axi_ad9361_tx (
// master/slave
assign dac_data_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in;
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
always @(posedge dac_clk) begin
dac_data_sync <= dac_data_sync_s;
@ -235,9 +235,9 @@ module axi_ad9361_tx (
// dac channel
axi_ad9361_tx_channel #(
.CHID (0),
.IQSEL (0),
.DP_DISABLE (DP_DISABLE))
.CHANNEL_ID (0),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -264,9 +264,9 @@ module axi_ad9361_tx (
// dac channel
axi_ad9361_tx_channel #(
.CHID (1),
.IQSEL (1),
.DP_DISABLE (DP_DISABLE))
.CHANNEL_ID (1),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -293,9 +293,9 @@ module axi_ad9361_tx (
// dac channel
axi_ad9361_tx_channel #(
.CHID (2),
.IQSEL (0),
.DP_DISABLE (DP_DISABLE))
.CHANNEL_ID (2),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -322,9 +322,9 @@ module axi_ad9361_tx (
// dac channel
axi_ad9361_tx_channel #(
.CHID (3),
.IQSEL (1),
.DP_DISABLE (DP_DISABLE))
.CHANNEL_ID (3),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -350,7 +350,7 @@ module axi_ad9361_tx (
// dac common processor interface
up_dac_common #(.PCORE_ID (PCORE_ID)) i_up_dac_common (
up_dac_common #(.ID (ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -389,7 +389,7 @@ module axi_ad9361_tx (
// dac delay control
up_delay_cntrl #(.IO_WIDTH(8), .IO_BASEADDR(6'h12)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(8), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

16
library/axi_ad9361/axi_ad9361_tx_channel.v
View File

@ -73,10 +73,10 @@ module axi_ad9361_tx_channel (
// parameters
parameter CHID = 32'h0;
parameter IQSEL = 0;
parameter DP_DISABLE = 0;
localparam PRBS_SEL = CHID;
parameter CHANNEL_ID = 32'h0;
parameter Q_OR_I_N = 0;
parameter DATAPATH_DISABLE = 0;
localparam PRBS_SEL = CHANNEL_ID;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
localparam PRBS_P15 = 2;
@ -281,11 +281,11 @@ module axi_ad9361_tx_channel (
end
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_iqcor_valid_s = dac_valid;
assign dac_iqcor_data_s = {dac_data_out, 4'd0};
end else begin
ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor (
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
.clk (dac_clk),
.valid (dac_valid),
.data_in ({dac_data_out, 4'd0}),
@ -361,7 +361,7 @@ module axi_ad9361_tx_channel (
// dds
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_s = 16'd0;
end else begin
ad_dds i_dds (
@ -377,7 +377,7 @@ module axi_ad9361_tx_channel (
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),

12
library/axi_ad9434/axi_ad9434.v
View File

@ -86,9 +86,9 @@ module axi_ad9434 (
localparam SERIES7 = 0;
localparam SERIES6 = 1;
parameter PCORE_ID = 0;
parameter PCORE_DEVTYPE = SERIES7;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = SERIES7;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
@ -178,8 +178,8 @@ module axi_ad9434 (
assign adc_enable = 1'b1;
axi_ad9434_if #(
.PCORE_DEVTYPE(PCORE_DEVTYPE),
.PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP))
.DEVICE_TYPE(DEVICE_TYPE),
.IO_DELAY_GROUP(IO_DELAY_GROUP))
i_if(
.adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n),
@ -210,7 +210,7 @@ module axi_ad9434 (
.up_drp_locked(up_drp_locked_s));
// common processor control
axi_ad9434_core #(.PCORE_ID(PCORE_ID))
axi_ad9434_core #(.ID(ID))
i_core (
.adc_clk(adc_clk),
.adc_data(adc_data_if_s),

8
library/axi_ad9434/axi_ad9434_core.v
View File

@ -93,7 +93,7 @@ module axi_ad9434_core (
adc_status);
// parameters
parameter PCORE_ID = 0;
parameter ID = 0;
// device interface
input adc_clk;
@ -200,7 +200,7 @@ module axi_ad9434_core (
end
up_adc_common #(
.PCORE_ID(PCORE_ID))
.ID(ID))
i_adc_common(
.mmcm_rst (mmcm_rst),
@ -246,7 +246,7 @@ module axi_ad9434_core (
.up_rack (up_rack_s[0]));
up_adc_channel #(
.PCORE_ADC_CHID(0))
.ADC_CHANNEL_ID(0))
i_adc_channel(
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -295,7 +295,7 @@ module axi_ad9434_core (
// adc delay control
up_delay_cntrl #(.IO_WIDTH(13), .IO_BASEADDR(6'h02)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

30
library/axi_ad9434/axi_ad9434_if.v
View File

@ -71,7 +71,7 @@ module axi_ad9434_if (
// mmcm reset
mmcm_rst,
// drp interface for MMCM
// drp interface for MMCM_OR_BUFR_N
up_rstn,
up_drp_sel,
up_drp_wr,
@ -82,11 +82,11 @@ module axi_ad9434_if (
up_drp_locked);
// parameters
parameter PCORE_DEVTYPE = 0; // 0 - 7Series / 1 - 6Series
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// buffer type based on the target device.
localparam PCORE_BUFTYPE = PCORE_DEVTYPE;
localparam DEVICE_TYPE = DEVICE_TYPE;
localparam SDR = 0;
// adc interface (clk, data, over-range)
@ -151,11 +151,11 @@ module axi_ad9434_if (
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
ad_serdes_in #(
.DEVICE_TYPE(PCORE_DEVTYPE),
.DEVICE_TYPE(DEVICE_TYPE),
.IODELAY_CTRL(0),
.IODELAY_GROUP(PCORE_IODELAY_GROUP),
.IF_TYPE(SDR),
.PARALLEL_WIDTH(4))
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR),
.DATA_WIDTH(4))
i_adc_data (
.rst(adc_rst),
.clk(adc_clk_in),
@ -182,11 +182,11 @@ module axi_ad9434_if (
// over-range interface
ad_serdes_in #(
.DEVICE_TYPE(PCORE_DEVTYPE),
.DEVICE_TYPE(DEVICE_TYPE),
.IODELAY_CTRL(1),
.IODELAY_GROUP(PCORE_IODELAY_GROUP),
.IF_TYPE(SDR),
.PARALLEL_WIDTH(4))
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR),
.DATA_WIDTH(4))
i_adc_data (
.rst(adc_rst),
.clk(adc_clk_in),
@ -209,9 +209,9 @@ module axi_ad9434_if (
.delay_rst(delay_rst),
.delay_locked(delay_locked));
// clock input buffers and MMCM
// clock input buffers and MMCM_OR_BUFR_N
ad_serdes_clk #(
.MMCM_DEVICE_TYPE (PCORE_DEVTYPE),
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (2),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
@ -236,7 +236,7 @@ module axi_ad9434_if (
// adc overange
assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
// adc status: adc is up, if both the MMCM and DELAY blocks are up
// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
always @(posedge adc_div_clk) begin
if(adc_rst == 1'b1) begin
adc_status_m1 <= 1'b0;

16
library/axi_ad9467/axi_ad9467.v
View File

@ -87,9 +87,9 @@ module axi_ad9467(
// parameters
parameter PCORE_ID = 0;
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface
@ -192,8 +192,8 @@ module axi_ad9467(
// main (device interface)
axi_ad9467_if #(
.PCORE_BUFTYPE (PCORE_BUFTYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
.DEVICE_TYPE (DEVICE_TYPE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
@ -215,7 +215,7 @@ module axi_ad9467(
// channel
axi_ad9467_channel #(.CHID(0)) i_channel (
axi_ad9467_channel #(.CHANNEL_ID(0)) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
@ -238,7 +238,7 @@ module axi_ad9467(
// adc delay control
up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
@ -258,7 +258,7 @@ module axi_ad9467(
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

4
library/axi_ad9467/axi_ad9467_channel.v
View File

@ -69,7 +69,7 @@ module axi_ad9467_channel(
// parameters
parameter CHID = 0;
parameter CHANNEL_ID = 0;
// adc interface
@ -127,7 +127,7 @@ module axi_ad9467_channel(
.dfmt_type(adc_dfmt_type_s),
.dfmt_se(adc_dfmt_se_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

14
library/axi_ad9467/axi_ad9467_if.v
View File

@ -74,8 +74,8 @@ module axi_ad9467_if (
// buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// adc interface (clk, data, over-range)
@ -165,9 +165,9 @@ module axi_ad9467_if (
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
@ -187,9 +187,9 @@ module axi_ad9467_if (
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
@ -207,7 +207,7 @@ module axi_ad9467_if (
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),

10
library/axi_ad9625/axi_ad9625.v
View File

@ -81,9 +81,9 @@ module axi_ad9625 (
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
@ -177,7 +177,7 @@ module axi_ad9625 (
assign adc_valid = 1'b1;
axi_ad9625_if #(.PCORE_ID(PCORE_ID)) i_if (
axi_ad9625_if #(.ID(ID)) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
@ -214,7 +214,7 @@ module axi_ad9625 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

2
library/axi_ad9625/axi_ad9625_channel.v
View File

@ -131,7 +131,7 @@ module axi_ad9625_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

6
library/axi_ad9625/axi_ad9625_if.v
View File

@ -59,7 +59,7 @@ module axi_ad9625_if (
adc_raddr_in,
adc_raddr_out);
parameter PCORE_ID = 0;
parameter ID = 0;
// jesd interface
// rx_clk is ref_clk/4
@ -127,7 +127,7 @@ module axi_ad9625_if (
// synchronization mode, multiple instances
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
always @(posedge rx_clk) begin
adc_data <= adc_rdata_s;
@ -219,7 +219,7 @@ module axi_ad9625_if (
// alignment fifo
ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(192)) i_mem (
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(192)) i_mem (
.clka (rx_clk),
.wea (1'b1),
.addra (adc_waddr),

28
library/axi_ad9643/axi_ad9643.v
View File

@ -91,10 +91,10 @@ module axi_ad9643 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
@ -224,9 +224,9 @@ module axi_ad9643 (
// channel
axi_ad9643_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
.Q_OR_I_N(0),
.CHANNEL_ID(0),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -253,9 +253,9 @@ module axi_ad9643 (
// channel
axi_ad9643_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
.Q_OR_I_N(1),
.CHANNEL_ID(1),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -282,8 +282,8 @@ module axi_ad9643 (
// main (device interface)
axi_ad9643_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
.DEVICE_TYPE (DEVICE_TYPE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
@ -309,7 +309,7 @@ module axi_ad9643 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -350,7 +350,7 @@ module axi_ad9643 (
// adc delay control
up_delay_cntrl #(.IO_WIDTH(15), .IO_BASEADDR(6'h02)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(15), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),

16
library/axi_ad9643/axi_ad9643_channel.v
View File

@ -72,9 +72,9 @@ module axi_ad9643_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
@ -133,7 +133,7 @@ module axi_ad9643_channel (
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_data_s = {2'd0, adc_data};
end else begin
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
@ -149,7 +149,7 @@ module axi_ad9643_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
@ -167,10 +167,10 @@ module axi_ad9643_channel (
assign adc_dcfilter_data_out = adc_dcfilter_data_s;
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_iqcor_data = adc_dcfilter_data_s;
end else begin
ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor (
ad_iqcor #(.Q_OR_I_N(Q_OR_I_N)) i_ad_iqcor (
.clk (adc_clk),
.valid (1'b1),
.data_in (adc_dcfilter_data_s),
@ -183,7 +183,7 @@ module axi_ad9643_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

14
library/axi_ad9643/axi_ad9643_if.v
View File

@ -79,8 +79,8 @@ module axi_ad9643_if (
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
@ -201,9 +201,9 @@ module axi_ad9643_if (
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
@ -223,9 +223,9 @@ module axi_ad9643_if (
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
@ -243,7 +243,7 @@ module axi_ad9643_if (
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),

28
library/axi_ad9652/axi_ad9652.v
View File

@ -90,10 +90,10 @@ module axi_ad9652 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
@ -221,9 +221,9 @@ module axi_ad9652 (
// channel
axi_ad9652_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
.Q_OR_I_N(0),
.CHANNEL_ID(0),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -250,9 +250,9 @@ module axi_ad9652 (
// channel
axi_ad9652_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
.Q_OR_I_N(1),
.CHANNEL_ID(1),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -279,8 +279,8 @@ module axi_ad9652 (
// main (device interface)
axi_ad9652_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
.DEVICE_TYPE (DEVICE_TYPE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
@ -305,7 +305,7 @@ module axi_ad9652 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -346,7 +346,7 @@ module axi_ad9652 (
// adc delay control
up_delay_cntrl #(.IO_WIDTH(17), .IO_BASEADDR(6'h02)) i_delay_cntrl (
up_delay_cntrl #(.DATA_WIDTH(17), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),

14
library/axi_ad9652/axi_ad9652_channel.v
View File

@ -74,9 +74,9 @@ module axi_ad9652_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
@ -131,7 +131,7 @@ module axi_ad9652_channel (
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_data;
end else begin
ad_dcfilter i_ad_dcfilter (
@ -149,10 +149,10 @@ module axi_ad9652_channel (
assign adc_dcfilter_data_out = adc_dcfilter_data_s;
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign adc_iqcor_data = adc_dcfilter_data_s;
end else begin
ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor (
ad_iqcor #(.Q_OR_I_N(Q_OR_I_N)) i_ad_iqcor (
.clk (adc_clk),
.valid (1'b1),
.data_in (adc_dcfilter_data_s),
@ -165,7 +165,7 @@ module axi_ad9652_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

14
library/axi_ad9652/axi_ad9652_if.v
View File

@ -78,8 +78,8 @@ module axi_ad9652_if (
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
@ -170,9 +170,9 @@ module axi_ad9652_if (
generate
for (l_inst = 0; l_inst <= 15; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
@ -192,9 +192,9 @@ module axi_ad9652_if (
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
@ -212,7 +212,7 @@ module axi_ad9652_if (
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),

20
library/axi_ad9671/axi_ad9671.v
View File

@ -85,16 +85,16 @@ module axi_ad9671 (
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_4L_2L_N = 1;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter QUAD_OR_DUAL_N = 1;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
input rx_clk;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
input rx_sof;
// dma interface
@ -201,8 +201,8 @@ module axi_ad9671 (
// main (device interface)
axi_ad9671_if #(
.PCORE_4L_2L_N(PCORE_4L_2L_N),
.PCORE_ID(PCORE_ID)
.QUAD_OR_DUAL_N(QUAD_OR_DUAL_N),
.ID(ID)
) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
@ -240,7 +240,7 @@ module axi_ad9671 (
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_channel
axi_ad9671_channel #(.CHID(n)) i_channel (
axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid_s),
@ -268,7 +268,7 @@ module axi_ad9671 (
// common processor control
up_adc_common #(
.PCORE_ID(PCORE_ID)
.ID(ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
@ -311,7 +311,7 @@ module axi_ad9671 (
// up bus interface
up_axi #(
.PCORE_ADDR_WIDTH (14)
.ADDRESS_WIDTH (14)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),

4
library/axi_ad9671/axi_ad9671_channel.v
View File

@ -74,7 +74,7 @@ module axi_ad9671_channel (
// parameters
parameter CHID = 0;
parameter CHANNEL_ID = 0;
// adc interface
@ -135,7 +135,7 @@ module axi_ad9671_channel (
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

38
library/axi_ad9671/axi_ad9671_hw.tcl
View File

@ -31,26 +31,26 @@ add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
add_parameter PCORE_4L_2L_N INTEGER 0
set_parameter_property PCORE_4L_2L_N DEFAULT_VALUE 1
set_parameter_property PCORE_4L_2L_N DISPLAY_NAME PCORE_4L_2L_N
set_parameter_property PCORE_4L_2L_N TYPE INTEGER
set_parameter_property PCORE_4L_2L_N UNITS None
set_parameter_property PCORE_4L_2L_N HDL_PARAMETER true
add_parameter QUAD_OR_DUAL_N INTEGER 0
set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 1
set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
set_parameter_property QUAD_OR_DUAL_N UNITS None
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
# axi4 slave
@ -91,7 +91,7 @@ add_interface_port xcvr_clk rx_clk clk Input 1
add_interface xcvr_data conduit end
set_interface_property xcvr_data associatedClock xcvr_clk
add_interface_port xcvr_data rx_data data Input 64*PCORE_4L_2L_N+64
add_interface_port xcvr_data rx_data data Input 64*QUAD_OR_DUAL_N+64
add_interface_port xcvr_data rx_sof data_sof Input 1
add_interface xcvr_sync conduit end

14
library/axi_ad9671/axi_ad9671_if.v
View File

@ -80,15 +80,15 @@ module axi_ad9671_if (
// parameters
parameter PCORE_4L_2L_N = 1;
parameter PCORE_ID = 0;
parameter QUAD_OR_DUAL_N = 1;
parameter ID = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input rx_sof;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
// adc data output
@ -181,8 +181,8 @@ module axi_ad9671_if (
assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in;
assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_sync_s = (ID == 0) ? adc_sync_out : adc_sync_in;
always @(posedge rx_clk) begin
adc_data_a <= adc_rdata[ 15: 0];
@ -217,7 +217,7 @@ module axi_ad9671_if (
end
always @(posedge rx_clk) begin
if (PCORE_4L_2L_N == 1'b1) begin
if (QUAD_OR_DUAL_N == 1'b1) begin
int_valid <= 1'b1;
int_data <= rx_data;
end else begin
@ -236,7 +236,7 @@ module axi_ad9671_if (
end
end
ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(128)) i_mem (
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem (
.clka(rx_clk),
.wea(int_valid),
.addra(adc_waddr),

12
library/axi_ad9680/axi_ad9680.v
View File

@ -81,9 +81,9 @@ module axi_ad9680 (
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
@ -206,7 +206,7 @@ module axi_ad9680 (
// channel
axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
axi_ad9680_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
@ -229,7 +229,7 @@ module axi_ad9680 (
// channel
axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
axi_ad9680_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
@ -252,7 +252,7 @@ module axi_ad9680 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),

6
library/axi_ad9680/axi_ad9680_channel.v
View File

@ -72,8 +72,8 @@ module axi_ad9680_channel (
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
@ -136,7 +136,7 @@ module axi_ad9680_channel (
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

12
library/axi_ad9680/axi_ad9680_hw.tcl
View File

@ -32,12 +32,12 @@ add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
# axi4 slave

16
library/axi_ad9739a/axi_ad9739a.v
View File

@ -85,12 +85,12 @@ module axi_ad9739a (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter DAC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// dac interface
@ -175,7 +175,7 @@ module axi_ad9739a (
// device interface
axi_ad9739a_if #(.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE)) i_if (
axi_ad9739a_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
@ -207,7 +207,7 @@ module axi_ad9739a (
// core
axi_ad9739a_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
axi_ad9739a_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_data_00 (dac_data_00_s),

38
library/axi_ad9739a/axi_ad9739a_channel.v
View File

@ -84,8 +84,8 @@ module axi_ad9739a_channel (
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -397,7 +397,7 @@ module axi_ad9739a_channel (
end
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_00_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -412,7 +412,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_01_s = 16'd0;
end else begin
ad_dds i_dds_1 (
@ -427,7 +427,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_02_s = 16'd0;
end else begin
ad_dds i_dds_2 (
@ -442,7 +442,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_03_s = 16'd0;
end else begin
ad_dds i_dds_3 (
@ -457,7 +457,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_04_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -472,7 +472,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_05_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -487,7 +487,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_06_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -502,7 +502,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_07_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -517,7 +517,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_08_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -532,7 +532,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_09_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -547,7 +547,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_10_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -562,7 +562,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_11_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -577,7 +577,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_12_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -592,7 +592,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_13_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -607,7 +607,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_14_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -622,7 +622,7 @@ module axi_ad9739a_channel (
endgenerate
generate
if (DP_DISABLE == 1) begin
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_15_s = 16'd0;
end else begin
ad_dds i_dds_0 (
@ -638,7 +638,7 @@ module axi_ad9739a_channel (
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),

10
library/axi_ad9739a/axi_ad9739a_core.v
View File

@ -86,8 +86,8 @@ module axi_ad9739a_core (
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
@ -170,8 +170,8 @@ module axi_ad9739a_core (
// dac channel
axi_ad9739a_channel #(
.CHID(0),
.DP_DISABLE(DP_DISABLE))
.CHANNEL_ID(0),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
@ -208,7 +208,7 @@ module axi_ad9739a_core (
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
up_dac_common #(.ID(ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),

14
library/axi_ad9739a/axi_ad9739a_if.v
View File

@ -82,7 +82,7 @@ module axi_ad9739a_if (
// parameters
parameter PCORE_DEVICE_TYPE = 0;
parameter DEVICE_TYPE = 0;
// dac interface
@ -143,9 +143,9 @@ module axi_ad9739a_if (
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES(1),
.SERDES_OR_DDR_N(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_serdes_out_data_a (
.rst (dac_rst),
.clk (dac_clk),
@ -164,9 +164,9 @@ module axi_ad9739a_if (
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES(1),
.SERDES_OR_DDR_N(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_serdes_out_data_b (
.rst (dac_rst),
.clk (dac_clk),
@ -185,9 +185,9 @@ module axi_ad9739a_if (
// dac clock output serdes & buffer
ad_serdes_out #(
.SERDES(1),
.SERDES_OR_DDR_N(1),
.DATA_WIDTH(1),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
.DEVICE_TYPE (DEVICE_TYPE))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),

6
library/axi_adcfifo/axi_adcfifo.v
View File

@ -114,7 +114,7 @@ module axi_adcfifo (
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'hffffffff;
parameter AXI_ADDRESS_LIMIT = 32'hffffffff;
parameter AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
// adc interface
@ -215,7 +215,7 @@ module axi_adcfifo (
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT))
i_wr (
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
@ -258,7 +258,7 @@ module axi_adcfifo (
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT))
i_rd (
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),

36
library/axi_adcfifo/axi_adcfifo_dma.v
View File

@ -62,9 +62,9 @@ module axi_adcfifo_dma (
parameter DMA_READY_ENABLE = 1;
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDR_WIDTH = 8;
localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
localparam DMA_ADDRESS_WIDTH = 8;
localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3));
// adc write
@ -86,32 +86,32 @@ module axi_adcfifo_dma (
// internal registers
reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0;
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0;
reg axi_dready = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s;
wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s;
wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
@ -152,7 +152,7 @@ module axi_adcfifo_dma (
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0];
axi_addr_diff <= axi_addr_diff_s[DMA_ADDRESS_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
@ -211,10 +211,10 @@ module axi_adcfifo_dma (
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (AXI_ADDR_WIDTH),
.DATA_WIDTH_A (AXI_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
.A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
.A_DATA_WIDTH (AXI_DATA_WIDTH),
.B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
.B_DATA_WIDTH (DMA_DATA_WIDTH))
i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),

2
library/axi_adcfifo/axi_adcfifo_rd.v
View File

@ -91,7 +91,7 @@ module axi_adcfifo_rd (
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
parameter AXI_ADDRESS_LIMIT = 32'h00000000;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 6'd3;

6
library/axi_adcfifo/axi_adcfifo_wr.v
View File

@ -97,7 +97,7 @@ module axi_adcfifo_wr (
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
parameter AXI_ADDRESS_LIMIT = 32'h00000000;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 8'd6;
@ -259,7 +259,7 @@ module axi_adcfifo_wr (
adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
if (adc_xfer_init == 1'b1) begin
adc_xfer_limit <= 1'd1;
end else if ((adc_xfer_addr >= AXI_ADDRLIMIT) || (adc_xfer_enable == 1'b0)) begin
end else if ((adc_xfer_addr >= AXI_ADDRESS_LIMIT) || (adc_xfer_enable == 1'b0)) begin
adc_xfer_limit <= 1'd0;
end
if (adc_xfer_init == 1'b1) begin
@ -464,7 +464,7 @@ module axi_adcfifo_wr (
// buffer
ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDR_WIDTH(8)) i_mem (
ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDRESS_WIDTH(8)) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),

26
library/axi_clkgen/axi_clkgen.v
View File

@ -68,13 +68,13 @@ module axi_clkgen (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_CLKIN_PERIOD = 5.0;
parameter PCORE_VCO_DIV = 11;
parameter PCORE_VCO_MUL = 49;
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter CLKIN_PERIOD = 5.0;
parameter VCO_DIV = 11;
parameter VCO_MUL = 49;
parameter CLK0_DIV = 6;
parameter CLK1_DIV = 6;
// clocks
@ -189,12 +189,12 @@ module axi_clkgen (
// mmcm instantiations
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (PCORE_CLKIN_PERIOD),
.MMCM_VCO_DIV (PCORE_VCO_DIV),
.MMCM_VCO_MUL (PCORE_VCO_MUL),
.MMCM_CLK0_DIV (PCORE_CLK0_DIV),
.MMCM_CLK1_DIV (PCORE_CLK1_DIV))
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (CLKIN_PERIOD),
.MMCM_VCO_DIV (VCO_DIV),
.MMCM_VCO_MUL (VCO_MUL),
.MMCM_CLK0_DIV (CLK0_DIV),
.MMCM_CLK1_DIV (CLK1_DIV))
i_mmcm_drp (
.clk (clk),
.mmcm_rst (mmcm_rst),

40
library/axi_dmac/2d_transfer.v
View File

@ -43,34 +43,34 @@ module dmac_2d_transfer (
input req_valid,
output reg req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_x_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_y_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_dest_stride,
input [C_DMA_LENGTH_WIDTH-1:0] req_src_stride,
input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [DMA_LENGTH_WIDTH-1:0] req_x_length,
input [DMA_LENGTH_WIDTH-1:0] req_y_length,
input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
input req_sync_transfer_start,
output reg req_eot,
output reg out_req_valid,
input out_req_ready,
output [31:C_BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:C_BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [C_DMA_LENGTH_WIDTH-1:0] out_req_length,
output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [DMA_LENGTH_WIDTH-1:0] out_req_length,
output reg out_req_sync_transfer_start,
input out_eot
);
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_BYTES_PER_BEAT_WIDTH_SRC = 3;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = 3;
parameter DMA_LENGTH_WIDTH = 24;
parameter BYTES_PER_BEAT_WIDTH_SRC = 3;
parameter BYTES_PER_BEAT_WIDTH_DEST = 3;
reg [31:C_BYTES_PER_BEAT_WIDTH_DEST] dest_address;
reg [31:C_BYTES_PER_BEAT_WIDTH_SRC] src_address;
reg [C_DMA_LENGTH_WIDTH-1:0] x_length;
reg [C_DMA_LENGTH_WIDTH-1:0] y_length;
reg [C_DMA_LENGTH_WIDTH-1:0] dest_stride;
reg [C_DMA_LENGTH_WIDTH-1:0] src_stride;
reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address;
reg [DMA_LENGTH_WIDTH-1:0] x_length;
reg [DMA_LENGTH_WIDTH-1:0] y_length;
reg [DMA_LENGTH_WIDTH-1:0] dest_stride;
reg [DMA_LENGTH_WIDTH-1:0] src_stride;
reg [1:0] req_id;
reg [1:0] eot_id;
@ -126,8 +126,8 @@ begin
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC];
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin

26
library/axi_dmac/address_generator.v
View File

@ -41,11 +41,11 @@ module dmac_address_generator (
input req_valid,
output reg req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input sync_id,
input eot,
@ -65,11 +65,11 @@ module dmac_address_generator (
);
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
parameter ID_WIDTH = 3;
parameter DMA_DATA_WIDTH = 64;
parameter BEATS_PER_BURST_WIDTH = 4;
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8);
localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
`include "inc_id.h"
@ -77,12 +77,12 @@ assign burst = 2'b01;
assign prot = 3'b000;
assign cache = 4'b0011;
assign len = length;
assign size = $clog2(C_DMA_DATA_WIDTH/8);
assign size = $clog2(DMA_DATA_WIDTH/8);
reg [7:0] length = 'h0;
reg [31-C_BYTES_PER_BEAT_WIDTH:0] address = 'h00;
reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {C_BYTES_PER_BEAT_WIDTH{1'b0}}};
reg [31-BYTES_PER_BEAT_WIDTH:0] address = 'h00;
reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}};
reg addr_valid_d1;
reg last = 1'b0;

170
library/axi_dmac/axi_dmac.v
View File

@ -72,7 +72,7 @@ module axi_dmac (
// Write address
output [31:0] m_dest_axi_awaddr,
output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
output [ 2:0] m_dest_axi_awsize,
output [ 1:0] m_dest_axi_awburst,
output [ 2:0] m_dest_axi_awprot,
@ -81,8 +81,8 @@ module axi_dmac (
input m_dest_axi_awready,
// Write data
output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
input m_dest_axi_wready,
output m_dest_axi_wvalid,
output m_dest_axi_wlast,
@ -95,7 +95,7 @@ module axi_dmac (
// Unused read interface
output m_dest_axi_arvalid,
output [31:0] m_dest_axi_araddr,
output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
output [ 2:0] m_dest_axi_arsize,
output [ 1:0] m_dest_axi_arburst,
output [ 3:0] m_dest_axi_arcache,
@ -103,21 +103,21 @@ module axi_dmac (
input m_dest_axi_arready,
input m_dest_axi_rvalid,
input [ 1:0] m_dest_axi_rresp,
input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
output m_dest_axi_rready,
// Read address
input m_src_axi_arready,
output m_src_axi_arvalid,
output [31:0] m_src_axi_araddr,
output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
output [ 2:0] m_src_axi_arsize,
output [ 1:0] m_src_axi_arburst,
output [ 2:0] m_src_axi_arprot,
output [ 3:0] m_src_axi_arcache,
// Read data and response
input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
output m_src_axi_rready,
input m_src_axi_rvalid,
input [ 1:0] m_src_axi_rresp,
@ -125,15 +125,15 @@ module axi_dmac (
// Unused write interface
output m_src_axi_awvalid,
output [31:0] m_src_axi_awaddr,
output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
output [ 2:0] m_src_axi_awsize,
output [ 1:0] m_src_axi_awburst,
output [ 3:0] m_src_axi_awcache,
output [ 2:0] m_src_axi_awprot,
input m_src_axi_awready,
output m_src_axi_wvalid,
output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
output m_src_axi_wlast,
input m_src_axi_wready,
input m_src_axi_bvalid,
@ -144,7 +144,7 @@ module axi_dmac (
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
@ -152,14 +152,14 @@ module axi_dmac (
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
@ -168,34 +168,34 @@ module axi_dmac (
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output fifo_rd_xfer_req
);
parameter PCORE_ID = 0;
parameter ID = 0;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_2D_TRANSFER = 1;
parameter DMA_DATA_WIDTH_SRC = 64;
parameter DMA_DATA_WIDTH_DEST = 64;
parameter DMA_LENGTH_WIDTH = 24;
parameter 2D_TRANSFER = 1;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
parameter C_CLKS_ASYNC_SRC_DEST = 1;
parameter C_CLKS_ASYNC_DEST_REQ = 1;
parameter ASYNC_CLK_REQ_SRC = 1;
parameter ASYNC_CLK_SRC_DEST = 1;
parameter ASYNC_CLK_DEST_REQ = 1;
parameter C_AXI_SLICE_DEST = 0;
parameter C_AXI_SLICE_SRC = 0;
parameter C_SYNC_TRANSFER_START = 0;
parameter C_CYCLIC = 1;
parameter AXI_SLICE_DEST = 0;
parameter AXI_SLICE_SRC = 0;
parameter SYNC_TRANSFER_START = 0;
parameter CYCLIC = 1;
parameter C_DMA_AXI_PROTOCOL_DEST = 0;
parameter C_DMA_AXI_PROTOCOL_SRC = 0;
parameter C_DMA_TYPE_DEST = 0;
parameter C_DMA_TYPE_SRC = 2;
parameter DMA_AXI_PROTOCOL_DEST = 0;
parameter DMA_AXI_PROTOCOL_SRC = 0;
parameter DMA_TYPE_DEST = 0;
parameter DMA_TYPE_SRC = 2;
parameter C_MAX_BYTES_PER_BURST = 128;
parameter C_FIFO_SIZE = 4; // In bursts
parameter MAX_BYTES_PER_BURST = 128;
parameter FIFO_SIZE = 4; // In bursts
localparam DMA_TYPE_AXI_MM = 0;
localparam DMA_TYPE_AXI_STREAM = 1;
@ -203,26 +203,26 @@ localparam DMA_TYPE_FIFO = 2;
localparam PCORE_VERSION = 'h00040062;
localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
localparam BYTES_PER_BEAT_WIDTH_DEST = C_DMA_DATA_WIDTH_DEST > 1024 ? 8 :
C_DMA_DATA_WIDTH_DEST > 512 ? 7 :
C_DMA_DATA_WIDTH_DEST > 256 ? 6 :
C_DMA_DATA_WIDTH_DEST > 128 ? 5 :
C_DMA_DATA_WIDTH_DEST > 64 ? 4 :
C_DMA_DATA_WIDTH_DEST > 32 ? 3 :
C_DMA_DATA_WIDTH_DEST > 16 ? 2 :
C_DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = C_DMA_DATA_WIDTH_SRC > 1024 ? 8 :
C_DMA_DATA_WIDTH_SRC > 512 ? 7 :
C_DMA_DATA_WIDTH_SRC > 256 ? 6 :
C_DMA_DATA_WIDTH_SRC > 128 ? 5 :
C_DMA_DATA_WIDTH_SRC > 64 ? 4 :
C_DMA_DATA_WIDTH_SRC > 32 ? 3 :
C_DMA_DATA_WIDTH_SRC > 16 ? 2 :
C_DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
DMA_DATA_WIDTH_DEST > 512 ? 7 :
DMA_DATA_WIDTH_DEST > 256 ? 6 :
DMA_DATA_WIDTH_DEST > 128 ? 5 :
DMA_DATA_WIDTH_DEST > 64 ? 4 :
DMA_DATA_WIDTH_DEST > 32 ? 3 :
DMA_DATA_WIDTH_DEST > 16 ? 2 :
DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
DMA_DATA_WIDTH_SRC > 512 ? 7 :
DMA_DATA_WIDTH_SRC > 256 ? 6 :
DMA_DATA_WIDTH_SRC > 128 ? 5 :
DMA_DATA_WIDTH_SRC > 64 ? 4 :
DMA_DATA_WIDTH_SRC > 32 ? 3 :
DMA_DATA_WIDTH_SRC > 16 ? 2 :
DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
// Register interface signals
reg [31:0] up_rdata = 'd0;
@ -263,12 +263,12 @@ reg up_axis_xlast = 1'b1;
reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
reg up_dma_cyclic = C_CYCLIC;
wire up_dma_sync_transfer_start = C_SYNC_TRANSFER_START ? 1'b1 : 1'b0;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
reg up_dma_cyclic = CYCLIC;
wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
// ID signals from the DMAC, just for debugging
wire [2:0] dest_request_id;
@ -298,7 +298,7 @@ assign m_src_axi_wstrb = 'd0;
assign m_src_axi_wlast = 'd0;
up_axi #(
.PCORE_ADDR_WIDTH (12)
.ADDRESS_WIDTH (12)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
@ -386,15 +386,15 @@ begin
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
12'h103: begin
if (C_CYCLIC) up_dma_cyclic <= up_wdata[0];
if (CYCLIC) up_dma_cyclic <= up_wdata[0];
up_axis_xlast <= up_wdata[1];
end
12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h109: up_dma_src_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
endcase
end
end
@ -409,7 +409,7 @@ begin
up_rack <= up_rreq;
case (up_raddr)
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= PCORE_ID;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h020: up_rdata <= up_irq_mask;
12'h021: up_rdata <= up_irq_pending;
@ -421,9 +421,9 @@ begin
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= C_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= C_2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= C_2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h107: up_rdata <= 2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= 2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= 2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h10a: up_rdata <= up_transfer_done_bitmap;
12'h10b: up_rdata <= up_transfer_id_eot;
12'h10c: up_rdata <= 'h00; // Status
@ -460,7 +460,7 @@ wire dma_req_valid;
wire dma_req_ready;
wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
wire [C_DMA_LENGTH_WIDTH-1:0] dma_req_length;
wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;
wire dma_req_eot;
wire dma_req_sync_transfer_start;
wire up_req_eot;
@ -469,12 +469,12 @@ assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
generate if (C_2D_TRANSFER == 1) begin
generate if (2D_TRANSFER == 1) begin
dmac_2d_transfer #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
) i_2d_transfer (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
@ -513,20 +513,20 @@ assign up_req_eot = dma_req_eot;
end endgenerate
dmac_request_arb #(
.C_DMA_DATA_WIDTH_SRC(C_DMA_DATA_WIDTH_SRC),
.C_DMA_DATA_WIDTH_DEST(C_DMA_DATA_WIDTH_DEST),
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.C_DMA_TYPE_DEST(C_DMA_TYPE_DEST),
.C_DMA_TYPE_SRC(C_DMA_TYPE_SRC),
.C_CLKS_ASYNC_REQ_SRC(C_CLKS_ASYNC_REQ_SRC),
.C_CLKS_ASYNC_SRC_DEST(C_CLKS_ASYNC_SRC_DEST),
.C_CLKS_ASYNC_DEST_REQ(C_CLKS_ASYNC_DEST_REQ),
.C_AXI_SLICE_DEST(C_AXI_SLICE_DEST),
.C_AXI_SLICE_SRC(C_AXI_SLICE_SRC),
.C_MAX_BYTES_PER_BURST(C_MAX_BYTES_PER_BURST),
.C_FIFO_SIZE(C_FIFO_SIZE)
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.DMA_TYPE_DEST(DMA_TYPE_DEST),
.DMA_TYPE_SRC(DMA_TYPE_SRC),
.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
.AXI_SLICE_DEST(AXI_SLICE_DEST),
.AXI_SLICE_SRC(AXI_SLICE_SRC),
.MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
.FIFO_SIZE(FIFO_SIZE)
) i_request_arb (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),

48
library/axi_dmac/axi_dmac_hw.tcl
View File

@ -45,12 +45,12 @@ add_fileset_file axi_dmac_constr.sdc SDC PATH axi_dmac_constr.sdc
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0
set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
@ -80,26 +80,26 @@ set_parameter_property C_2D_TRANSFER TYPE INTEGER
set_parameter_property C_2D_TRANSFER UNITS None
set_parameter_property C_2D_TRANSFER HDL_PARAMETER true
add_parameter C_CLKS_ASYNC_REQ_SRC INTEGER 0
set_parameter_property C_CLKS_ASYNC_REQ_SRC DEFAULT_VALUE 1
set_parameter_property C_CLKS_ASYNC_REQ_SRC DISPLAY_NAME C_CLKS_ASYNC_REQ_SRC
set_parameter_property C_CLKS_ASYNC_REQ_SRC TYPE INTEGER
set_parameter_property C_CLKS_ASYNC_REQ_SRC UNITS None
set_parameter_property C_CLKS_ASYNC_REQ_SRC HDL_PARAMETER true
add_parameter ASYNC_CLK_REQ_SRC INTEGER 0
set_parameter_property ASYNC_CLK_REQ_SRC DEFAULT_VALUE 1
set_parameter_property ASYNC_CLK_REQ_SRC DISPLAY_NAME ASYNC_CLK_REQ_SRC
set_parameter_property ASYNC_CLK_REQ_SRC TYPE INTEGER
set_parameter_property ASYNC_CLK_REQ_SRC UNITS None
set_parameter_property ASYNC_CLK_REQ_SRC HDL_PARAMETER true
add_parameter C_CLKS_ASYNC_SRC_DEST INTEGER 0
set_parameter_property C_CLKS_ASYNC_SRC_DEST DEFAULT_VALUE 1
set_parameter_property C_CLKS_ASYNC_SRC_DEST DISPLAY_NAME C_CLKS_ASYNC_SRC_DEST
set_parameter_property C_CLKS_ASYNC_SRC_DEST TYPE INTEGER
set_parameter_property C_CLKS_ASYNC_SRC_DEST UNITS None
set_parameter_property C_CLKS_ASYNC_SRC_DEST HDL_PARAMETER true
add_parameter ASYNC_CLK_SRC_DEST INTEGER 0
set_parameter_property ASYNC_CLK_SRC_DEST DEFAULT_VALUE 1
set_parameter_property ASYNC_CLK_SRC_DEST DISPLAY_NAME ASYNC_CLK_SRC_DEST
set_parameter_property ASYNC_CLK_SRC_DEST TYPE INTEGER
set_parameter_property ASYNC_CLK_SRC_DEST UNITS None
set_parameter_property ASYNC_CLK_SRC_DEST HDL_PARAMETER true
add_parameter C_CLKS_ASYNC_DEST_REQ INTEGER 0
set_parameter_property C_CLKS_ASYNC_DEST_REQ DEFAULT_VALUE 1
set_parameter_property C_CLKS_ASYNC_DEST_REQ DISPLAY_NAME C_CLKS_ASYNC_DEST_REQ
set_parameter_property C_CLKS_ASYNC_DEST_REQ TYPE INTEGER
set_parameter_property C_CLKS_ASYNC_DEST_REQ UNITS None
set_parameter_property C_CLKS_ASYNC_DEST_REQ HDL_PARAMETER true
add_parameter ASYNC_CLK_DEST_REQ INTEGER 0
set_parameter_property ASYNC_CLK_DEST_REQ DEFAULT_VALUE 1
set_parameter_property ASYNC_CLK_DEST_REQ DISPLAY_NAME ASYNC_CLK_DEST_REQ
set_parameter_property ASYNC_CLK_DEST_REQ TYPE INTEGER
set_parameter_property ASYNC_CLK_DEST_REQ UNITS None
set_parameter_property ASYNC_CLK_DEST_REQ HDL_PARAMETER true
add_parameter C_AXI_SLICE_DEST INTEGER 0
set_parameter_property C_AXI_SLICE_DEST DEFAULT_VALUE 0

30
library/axi_dmac/data_mover.v
View File

@ -40,8 +40,8 @@ module dmac_data_mover (
input clk,
input resetn,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
@ -52,30 +52,30 @@ module dmac_data_mover (
output s_axi_ready,
input s_axi_valid,
input [C_DATA_WIDTH-1:0] s_axi_data,
input [DATA_WIDTH-1:0] s_axi_data,
input m_axi_ready,
output m_axi_valid,
output [C_DATA_WIDTH-1:0] m_axi_data,
output [DATA_WIDTH-1:0] m_axi_data,
output m_axi_last,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_DISABLE_WAIT_FOR_ID = 1;
parameter C_BEATS_PER_BURST_WIDTH = 4;
localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
parameter ID_WIDTH = 3;
parameter DATA_WIDTH = 64;
parameter DISABLE_WAIT_FOR_ID = 1;
parameter BEATS_PER_BURST_WIDTH = 4;
localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
`include "inc_id.h"
reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00;
reg [C_BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;
reg [C_ID_WIDTH-1:0] id = 'h00;
reg [C_ID_WIDTH-1:0] id_next = 'h00;
reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00;
reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;
reg [ID_WIDTH-1:0] id = 'h00;
reg [ID_WIDTH-1:0] id_next = 'h00;
reg pending_burst = 1'b0;
reg active = 1'b0;
@ -108,7 +108,7 @@ always @(posedge clk) begin
if (enable) begin
enabled <= 1'b1;
end else begin
if (C_DISABLE_WAIT_FOR_ID == 0) begin
if (DISABLE_WAIT_FOR_ID == 0) begin
// We are not allowed to just deassert valid, so wait until the
// current beat has been accepted
if (~s_axi_valid || m_axi_ready)

50
library/axi_dmac/dest_axi_mm.v
View File

@ -42,9 +42,9 @@ module dmac_dest_mm_axi (
input req_valid,
output req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [C_BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
input enable,
output enabled,
@ -57,18 +57,18 @@ module dmac_dest_mm_axi (
output [1:0] response_resp,
output response_resp_eot,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
output [C_ID_WIDTH-1:0] address_id,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
input response_eot,
input fifo_valid,
output fifo_ready,
input [C_DMA_DATA_WIDTH-1:0] fifo_data,
input [DMA_DATA_WIDTH-1:0] fifo_data,
// Write address
input m_axi_awready,
@ -81,8 +81,8 @@ module dmac_dest_mm_axi (
output [ 3:0] m_axi_awcache,
// Write data
output [C_DMA_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output [DMA_DATA_WIDTH-1:0] m_axi_wdata,
output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
@ -93,12 +93,12 @@ module dmac_dest_mm_axi (
output m_axi_bready
);
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter ID_WIDTH = 3;
parameter DMA_DATA_WIDTH = 64;
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8);
parameter BEATS_PER_BURST_WIDTH = 4;
reg [(C_DMA_DATA_WIDTH/8)-1:0] wstrb;
reg [(DMA_DATA_WIDTH/8)-1:0] wstrb;
wire address_req_valid;
wire address_req_ready;
@ -113,7 +113,7 @@ wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
splitter #(
.C_NUM_M(2)
.NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
@ -130,10 +130,10 @@ splitter #(
);
dmac_address_generator #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
@ -164,9 +164,9 @@ dmac_address_generator #(
);
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DMA_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
@ -197,14 +197,14 @@ begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= {(C_DMA_DATA_WIDTH/8){1'b1}};
wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
end
end
assign m_axi_wstrb = wstrb;
dmac_response_handler #(
.C_ID_WIDTH(C_ID_WIDTH)
.ID_WIDTH(ID_WIDTH)
) i_response_handler (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),

28
library/axi_dmac/dest_axi_stream.v
View File

@ -46,24 +46,24 @@ module dmac_dest_axi_stream (
output sync_id_ret,
output xfer_req,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input m_axis_ready,
output m_axis_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output m_axis_last,
output fifo_ready,
input fifo_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_xlast,
output response_valid,
@ -72,9 +72,9 @@ module dmac_dest_axi_stream (
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter ID_WIDTH = 3;
parameter S_AXIS_DATA_WIDTH = 64;
parameter BEATS_PER_BURST_WIDTH = 4;
reg req_xlast_d = 1'b0;
@ -97,10 +97,10 @@ end
assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
@ -128,7 +128,7 @@ dmac_data_mover # (
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
.ID_WIDTH(ID_WIDTH)
) i_response_generator (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),

28
library/axi_dmac/dest_fifo_inf.v
View File

@ -45,14 +45,14 @@ module dmac_dest_fifo_inf (
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input en,
output [C_DATA_WIDTH-1:0] dout,
output [DATA_WIDTH-1:0] dout,
output valid,
output underflow,
@ -60,11 +60,11 @@ module dmac_dest_fifo_inf (
output fifo_ready,
input fifo_valid,
input [C_DATA_WIDTH-1:0] fifo_data,
input [DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output response_valid,
input response_ready,
@ -72,9 +72,9 @@ module dmac_dest_fifo_inf (
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter ID_WIDTH = 3;
parameter DATA_WIDTH = 64;
parameter BEATS_PER_BURST_WIDTH = 4;
assign sync_id_ret = sync_id;
wire data_enabled;
@ -100,10 +100,10 @@ assign data_ready = en_d1 & (data_valid | ~enable);
assign valid = en_d1 & data_valid & enable;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
@ -131,7 +131,7 @@ dmac_data_mover # (
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
.ID_WIDTH(ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),

294
library/axi_dmac/request_arb.v
View File

@ -2,9 +2,9 @@
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <lars@metafoo.de>
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -22,16 +22,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -42,9 +42,9 @@ module dmac_request_arb (
input req_valid,
output req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_length,
input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [DMA_LENGTH_WIDTH-1:0] req_length,
input req_xlast,
input req_sync_transfer_start,
@ -70,8 +70,8 @@ module dmac_request_arb (
input m_axi_awready,
// Write data
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata,
output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata,
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
@ -92,7 +92,7 @@ module dmac_request_arb (
output [ 3:0] m_axi_arcache,
// Read data and response
input [C_DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata,
input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp,
@ -101,7 +101,7 @@ module dmac_request_arb (
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
@ -109,14 +109,14 @@ module dmac_request_arb (
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
@ -125,69 +125,69 @@ module dmac_request_arb (
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output fifo_rd_xfer_req,
output [C_ID_WIDTH-1:0] dbg_dest_request_id,
output [C_ID_WIDTH-1:0] dbg_dest_address_id,
output [C_ID_WIDTH-1:0] dbg_dest_data_id,
output [C_ID_WIDTH-1:0] dbg_dest_response_id,
output [C_ID_WIDTH-1:0] dbg_src_request_id,
output [C_ID_WIDTH-1:0] dbg_src_address_id,
output [C_ID_WIDTH-1:0] dbg_src_data_id,
output [C_ID_WIDTH-1:0] dbg_src_response_id,
output [ID_WIDTH-1:0] dbg_dest_request_id,
output [ID_WIDTH-1:0] dbg_dest_address_id,
output [ID_WIDTH-1:0] dbg_dest_data_id,
output [ID_WIDTH-1:0] dbg_dest_response_id,
output [ID_WIDTH-1:0] dbg_src_request_id,
output [ID_WIDTH-1:0] dbg_src_address_id,
output [ID_WIDTH-1:0] dbg_src_data_id,
output [ID_WIDTH-1:0] dbg_src_response_id,
output [7:0] dbg_status
);
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter DMA_DATA_WIDTH_SRC = 64;
parameter DMA_DATA_WIDTH_DEST = 64;
parameter DMA_LENGTH_WIDTH = 24;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = $clog2(C_DMA_DATA_WIDTH_DEST/8);
parameter C_BYTES_PER_BEAT_WIDTH_SRC = $clog2(C_DMA_DATA_WIDTH_SRC/8);
parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8);
parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8);
parameter C_DMA_TYPE_DEST = DMA_TYPE_MM_AXI;
parameter C_DMA_TYPE_SRC = DMA_TYPE_FIFO;
parameter DMA_TYPE_DEST = DMA_TYPE_MM_AXI;
parameter DMA_TYPE_SRC = DMA_TYPE_FIFO;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
parameter C_CLKS_ASYNC_SRC_DEST = 1;
parameter C_CLKS_ASYNC_DEST_REQ = 1;
parameter ASYNC_CLK_REQ_SRC = 1;
parameter ASYNC_CLK_SRC_DEST = 1;
parameter ASYNC_CLK_DEST_REQ = 1;
parameter C_AXI_SLICE_DEST = 0;
parameter C_AXI_SLICE_SRC = 0;
parameter AXI_SLICE_DEST = 0;
parameter AXI_SLICE_SRC = 0;
parameter C_MAX_BYTES_PER_BURST = 128;
parameter C_FIFO_SIZE = 4;
parameter MAX_BYTES_PER_BURST = 128;
parameter FIFO_SIZE = 4;
parameter C_ID_WIDTH = $clog2(C_FIFO_SIZE * 2);
parameter ID_WIDTH = $clog2(FIFO_SIZE*2);
localparam DMA_TYPE_MM_AXI = 0;
localparam DMA_TYPE_STREAM_AXI = 1;
localparam DMA_TYPE_FIFO = 2;
localparam DMA_ADDR_WIDTH_DEST = 32 - C_BYTES_PER_BEAT_WIDTH_DEST;
localparam DMA_ADDR_WIDTH_SRC = 32 - C_BYTES_PER_BEAT_WIDTH_SRC;
localparam DMA_ADDRESS_WIDTH_DEST = 32 - BYTES_PER_BEAT_WIDTH_DEST;
localparam DMA_ADDRESS_WIDTH_SRC = 32 - BYTES_PER_BEAT_WIDTH_SRC;
localparam DMA_DATA_WIDTH = C_DMA_DATA_WIDTH_SRC < C_DMA_DATA_WIDTH_DEST ?
C_DMA_DATA_WIDTH_DEST : C_DMA_DATA_WIDTH_SRC;
localparam DMA_DATA_WIDTH = DMA_DATA_WIDTH_SRC < DMA_DATA_WIDTH_DEST ?
DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC;
// Bytes per burst is the same for both dest and src, but bytes per beat may
// differ, so beats per burst may also differ
parameter BYTES_PER_BURST_WIDTH = $clog2(C_MAX_BYTES_PER_BURST);
localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_SRC;
localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_DEST;
parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST);
localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
localparam BURSTS_PER_TRANSFER_WIDTH = C_DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
reg [0:2**C_ID_WIDTH-1] eot_mem;
reg [0:2**ID_WIDTH-1] eot_mem;
wire request_eot;
wire [C_ID_WIDTH-1:0] request_id;
wire [C_ID_WIDTH-1:0] response_id;
wire [ID_WIDTH-1:0] request_id;
wire [ID_WIDTH-1:0] response_id;
wire enabled_src;
wire enabled_dest;
@ -217,9 +217,9 @@ wire dest_clk;
wire dest_resetn;
wire dest_req_valid;
wire dest_req_ready;
wire [DMA_ADDR_WIDTH_DEST-1:0] dest_req_address;
wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_address;
wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length;
wire [C_BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire dest_req_xlast;
wire dest_response_valid;
@ -228,15 +228,15 @@ wire dest_response_empty;
wire [1:0] dest_response_resp;
wire dest_response_resp_eot;
wire [C_ID_WIDTH-1:0] dest_request_id;
wire [C_ID_WIDTH-1:0] dest_response_id;
wire [ID_WIDTH-1:0] dest_request_id;
wire [ID_WIDTH-1:0] dest_response_id;
wire dest_valid;
wire dest_ready;
wire [C_DMA_DATA_WIDTH_DEST-1:0] dest_data;
wire [DMA_DATA_WIDTH_DEST-1:0] dest_data;
wire dest_fifo_repacked_valid;
wire dest_fifo_repacked_ready;
wire [C_DMA_DATA_WIDTH_DEST-1:0] dest_fifo_repacked_data;
wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_repacked_data;
wire dest_fifo_valid;
wire dest_fifo_ready;
wire [DMA_DATA_WIDTH-1:0] dest_fifo_data;
@ -245,7 +245,7 @@ wire src_clk;
wire src_resetn;
wire src_req_valid;
wire src_req_ready;
wire [DMA_ADDR_WIDTH_SRC-1:0] src_req_address;
wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_address;
wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
wire src_req_sync_transfer_start;
@ -254,15 +254,15 @@ wire src_response_ready;
wire src_response_empty;
wire [1:0] src_response_resp;
wire [C_ID_WIDTH-1:0] src_request_id;
wire [C_ID_WIDTH-1:0] src_response_id;
wire [ID_WIDTH-1:0] src_request_id;
wire [ID_WIDTH-1:0] src_response_id;
wire src_valid;
wire src_ready;
wire [C_DMA_DATA_WIDTH_SRC-1:0] src_data;
wire [DMA_DATA_WIDTH_SRC-1:0] src_data;
wire src_fifo_valid;
wire src_fifo_ready;
wire [C_DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;
wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;
wire src_fifo_repacked_valid;
wire src_fifo_repacked_ready;
wire [DMA_DATA_WIDTH-1:0] src_fifo_repacked_data;
@ -339,11 +339,11 @@ begin
end
end
generate if (C_CLKS_ASYNC_REQ_SRC) begin
generate if (ASYNC_CLK_REQ_SRC) begin
wire src_async_resetn_source;
if (C_DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
assign src_async_resetn_source = m_src_axi_aresetn;
end else begin
assign src_async_resetn_source = req_aresetn;
@ -363,10 +363,10 @@ end else begin
assign src_resetn = req_aresetn;
end endgenerate
generate if (C_CLKS_ASYNC_DEST_REQ) begin
generate if (ASYNC_CLK_DEST_REQ) begin
wire dest_async_resetn_source;
if (C_DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
assign dest_async_resetn_source = m_dest_axi_aresetn;
end else begin
assign dest_async_resetn_source = req_aresetn;
@ -386,12 +386,12 @@ end else begin
assign dest_resetn = req_aresetn;
end endgenerate
generate if (C_DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
assign dest_clk = m_dest_axi_aclk;
wire [C_ID_WIDTH-1:0] dest_data_id;
wire [C_ID_WIDTH-1:0] dest_address_id;
wire [ID_WIDTH-1:0] dest_data_id;
wire [ID_WIDTH-1:0] dest_address_id;
wire dest_address_eot = eot_mem[dest_address_id];
wire dest_data_eot = eot_mem[dest_data_id];
wire dest_response_eot = eot_mem[dest_response_id];
@ -400,10 +400,10 @@ assign dbg_dest_address_id = dest_address_id;
assign dbg_dest_data_id = dest_data_id;
dmac_dest_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_DEST)
.ID_WIDTH(ID_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST)
) i_dest_dma_mm (
.m_axi_aclk(m_dest_axi_aclk),
.m_axi_aresetn(dest_resetn),
@ -477,11 +477,11 @@ assign m_axi_bready = 1'b0;
end
if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
assign dest_clk = m_axis_aclk;
wire [C_ID_WIDTH-1:0] data_id;
wire [ID_WIDTH-1:0] data_id;
wire data_eot = eot_mem[data_id];
wire response_eot = eot_mem[dest_response_id];
@ -490,9 +490,9 @@ assign dbg_dest_address_id = 'h00;
assign dbg_dest_data_id = data_id;
dmac_dest_axi_stream #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_S_AXIS_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
.ID_WIDTH(ID_WIDTH),
.S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
) i_dest_dma_stream (
.s_axis_aclk(m_axis_aclk),
.s_axis_aresetn(dest_resetn),
@ -535,13 +535,13 @@ end else begin
assign m_axis_valid = 1'b0;
assign m_axis_data = 'h00;
end
end
if (C_DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
assign dest_clk = fifo_rd_clk;
wire [C_ID_WIDTH-1:0] data_id;
wire [ID_WIDTH-1:0] data_id;
wire data_eot = eot_mem[data_id];
wire response_eot = eot_mem[dest_response_id];
@ -550,9 +550,9 @@ assign dbg_dest_address_id = 'h00;
assign dbg_dest_data_id = data_id;
dmac_dest_fifo_inf #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
) i_dest_dma_fifo (
.clk(fifo_rd_clk),
.resetn(dest_resetn),
@ -597,12 +597,12 @@ assign fifo_rd_underflow = 1'b0;
end endgenerate
generate if (C_DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
assign src_clk = m_src_axi_aclk;
wire [C_ID_WIDTH-1:0] src_data_id;
wire [C_ID_WIDTH-1:0] src_address_id;
wire [ID_WIDTH-1:0] src_data_id;
wire [ID_WIDTH-1:0] src_address_id;
wire src_address_eot = eot_mem[src_address_id];
wire src_data_eot = eot_mem[src_data_id];
@ -610,10 +610,10 @@ assign dbg_src_address_id = src_address_id;
assign dbg_src_data_id = src_data_id;
dmac_src_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_SRC)
.ID_WIDTH(ID_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC)
) i_src_dma_mm (
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(src_resetn),
@ -671,9 +671,9 @@ assign m_axi_arcache = 'h00;
assign m_axi_arprot = 'h00;
assign m_axi_rready = 1'b0;
end
end
if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
assign src_clk = s_axis_aclk;
@ -687,9 +687,9 @@ assign src_response_valid = 1'b0;
assign src_response_resp = 2'b0;
dmac_src_axi_stream #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_S_AXIS_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
.ID_WIDTH(ID_WIDTH),
.S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
) i_src_dma_stream (
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(src_resetn),
@ -726,7 +726,7 @@ assign s_axis_ready = 1'b0;
end
if (C_DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
assign src_clk = fifo_wr_clk;
@ -740,9 +740,9 @@ assign src_response_valid = 1'b0;
assign src_response_resp = 2'b0;
dmac_src_fifo_inf #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
) i_src_dma_fifo (
.clk(fifo_wr_clk),
.resetn(src_resetn),
@ -781,8 +781,8 @@ assign fifo_wr_xfer_req = 1'b0;
end endgenerate
sync_bits #(
.NUM_BITS(C_ID_WIDTH),
.CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC)
.NUM_OF_BITS(ID_WIDTH),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_sync_src_request_id (
.out_clk(src_clk),
.out_resetn(src_resetn),
@ -791,8 +791,8 @@ sync_bits #(
);
sync_bits #(
.NUM_BITS(C_ID_WIDTH),
.CLK_ASYNC(C_CLKS_ASYNC_SRC_DEST)
.NUM_OF_BITS(ID_WIDTH),
.ASYNC_CLK(ASYNC_CLK_SRC_DEST)
) i_sync_dest_request_id (
.out_clk(dest_clk),
.out_resetn(dest_resetn),
@ -801,8 +801,8 @@ sync_bits #(
);
sync_bits #(
.NUM_BITS(C_ID_WIDTH),
.CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ)
.NUM_OF_BITS(ID_WIDTH),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_sync_req_response_id (
.out_clk(req_aclk),
.out_resetn(req_aresetn),
@ -811,9 +811,9 @@ sync_bits #(
);
axi_register_slice #(
.DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.FORWARD_REGISTERED(C_AXI_SLICE_SRC),
.BACKWARD_REGISTERED(C_AXI_SLICE_SRC)
.DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.FORWARD_REGISTERED(AXI_SLICE_SRC),
.BACKWARD_REGISTERED(AXI_SLICE_SRC)
) i_src_slice (
.clk(src_clk),
.resetn(src_resetn),
@ -826,8 +826,8 @@ axi_register_slice #(
);
util_axis_resize #(
.C_S_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.C_M_DATA_WIDTH(DMA_DATA_WIDTH)
.SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.MASTER_DATA_WIDTH(DMA_DATA_WIDTH)
) i_src_repack (
.clk(src_clk),
.resetn(src_resetn & src_enable),
@ -840,9 +840,9 @@ util_axis_resize #(
);
util_axis_fifo #(
.C_DATA_WIDTH(DMA_DATA_WIDTH),
.C_ADDRESS_WIDTH($clog2(C_MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * C_FIFO_SIZE)),
.C_CLKS_ASYNC(C_CLKS_ASYNC_SRC_DEST)
.DATA_WIDTH(DMA_DATA_WIDTH),
.ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)),
.ASYNC_CLK(ASYNC_CLK_SRC_DEST)
) i_fifo (
.s_axis_aclk(src_clk),
.s_axis_aresetn(src_resetn),
@ -859,8 +859,8 @@ util_axis_fifo #(
);
util_axis_resize #(
.C_S_DATA_WIDTH(DMA_DATA_WIDTH),
.C_M_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST)
.SLAVE_DATA_WIDTH(DMA_DATA_WIDTH),
.MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST)
) i_dest_repack (
.clk(dest_clk),
.resetn(dest_resetn & dest_enable),
@ -874,11 +874,11 @@ util_axis_resize #(
wire _dest_valid;
wire _dest_ready;
wire [C_DMA_DATA_WIDTH_DEST-1:0] _dest_data;
wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data;
axi_register_slice #(
.DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.FORWARD_REGISTERED(C_AXI_SLICE_DEST)
.DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.FORWARD_REGISTERED(AXI_SLICE_DEST)
) i_dest_slice2 (
.clk(dest_clk),
.resetn(dest_resetn),
@ -891,9 +891,9 @@ axi_register_slice #(
);
axi_register_slice #(
.DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.FORWARD_REGISTERED(C_AXI_SLICE_DEST),
.BACKWARD_REGISTERED(C_AXI_SLICE_DEST)
.DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.FORWARD_REGISTERED(AXI_SLICE_DEST),
.BACKWARD_REGISTERED(AXI_SLICE_DEST)
) i_dest_slice (
.clk(dest_clk),
.resetn(dest_resetn),
@ -926,7 +926,7 @@ end
assign req_ready = _req_ready & _req_valid & enable;
splitter #(
.C_NUM_M(3)
.NUM_M(3)
) i_req_splitter (
.clk(req_aclk),
.resetn(req_aresetn),
@ -945,9 +945,9 @@ splitter #(
);
util_axis_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + C_BYTES_PER_BEAT_WIDTH_DEST + 1),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
.DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1),
.ADDRESS_WIDTH(0),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_dest_req_fifo (
.s_axis_aclk(req_aclk),
.s_axis_aresetn(req_aresetn),
@ -956,8 +956,8 @@ util_axis_fifo #(
.s_axis_empty(req_dest_empty),
.s_axis_data({
req_dest_address,
req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST],
req_length[C_BYTES_PER_BEAT_WIDTH_DEST-1:0],
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0],
req_xlast
}),
.m_axis_aclk(dest_clk),
@ -973,9 +973,9 @@ util_axis_fifo #(
);
util_axis_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
.DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
.ADDRESS_WIDTH(0),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_src_req_fifo (
.s_axis_aclk(req_aclk),
.s_axis_aresetn(req_aresetn),
@ -984,7 +984,7 @@ util_axis_fifo #(
.s_axis_empty(req_src_empty),
.s_axis_data({
req_src_address,
req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC],
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC],
req_sync_transfer_start
}),
.m_axis_aclk(src_clk),
@ -999,9 +999,9 @@ util_axis_fifo #(
);
util_axis_fifo #(
.C_DATA_WIDTH(3),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
.DATA_WIDTH(3),
.ADDRESS_WIDTH(0),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_dest_response_fifo (
.s_axis_aclk(dest_clk),
.s_axis_aresetn(dest_resetn),
@ -1018,9 +1018,9 @@ util_axis_fifo #(
/* Unused for now
util_axis_fifo #(
.C_DATA_WIDTH(2),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
.DATA_WIDTH(2),
.ADDRESS_WIDTH(0),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_src_response_fifo (
.s_axis_aclk(src_clk),
.s_axis_aresetn(src_resetn),
@ -1038,8 +1038,8 @@ assign src_response_empty = 1'b1;
assign src_response_ready = 1'b1;
dmac_request_generator #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
.ID_WIDTH(ID_WIDTH),
.BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
) i_req_gen (
.req_aclk(req_aclk),
.req_aresetn(req_aresetn),
@ -1049,7 +1049,7 @@ dmac_request_generator #(
.req_valid(req_gen_valid),
.req_ready(req_gen_ready),
.req_burst_count(req_length[C_DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
.req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
.enable(do_enable),
.pause(pause),
@ -1058,8 +1058,8 @@ dmac_request_generator #(
);
sync_bits #(
.NUM_BITS(3),
.CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ)
.NUM_OF_BITS(3),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_sync_control_dest (
.out_clk(dest_clk),
.out_resetn(dest_resetn),
@ -1068,8 +1068,8 @@ sync_bits #(
);
sync_bits #(
.NUM_BITS(2),
.CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ)
.NUM_OF_BITS(2),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_sync_status_dest (
.out_clk(req_aclk),
.out_resetn(req_aresetn),
@ -1078,8 +1078,8 @@ sync_bits #(
);
sync_bits #(
.NUM_BITS(3),
.CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC)
.NUM_OF_BITS(3),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_sync_control_src (
.out_clk(src_clk),
.out_resetn(src_resetn),
@ -1088,8 +1088,8 @@ sync_bits #(
);
sync_bits #(
.NUM_BITS(3),
.CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC)
.NUM_OF_BITS(3),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_sync_status_src (
.out_clk(req_aclk),
.out_resetn(req_aresetn),

16
library/axi_dmac/request_generator.v
View File

@ -40,12 +40,12 @@ module dmac_request_generator (
input req_aclk,
input req_aresetn,
output [C_ID_WIDTH-1:0] request_id,
input [C_ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] request_id,
input [ID_WIDTH-1:0] response_id,
input req_valid,
output reg req_ready,
input [C_BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
input enable,
input pause,
@ -53,8 +53,8 @@ module dmac_request_generator (
output eot
);
parameter C_ID_WIDTH = 3;
parameter C_BURSTS_PER_TRANSFER_WIDTH = 17;
parameter ID_WIDTH = 3;
parameter BURSTS_PER_TRANSFER_WIDTH = 17;
`include "inc_id.h"
@ -65,9 +65,9 @@ parameter C_BURSTS_PER_TRANSFER_WIDTH = 17;
* care that only the requested ammount of bytes is transfered.
*/
reg [C_BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
reg [C_ID_WIDTH-1:0] id;
wire [C_ID_WIDTH-1:0] id_next = inc_id(id);
reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
reg [ID_WIDTH-1:0] id;
wire [ID_WIDTH-1:0] id_next = inc_id(id);
assign eot = burst_count == 'h00;
assign request_id = id;

6
library/axi_dmac/response_generator.v
View File

@ -43,8 +43,8 @@ module dmac_response_generator (
input enable,
output reg enabled,
input [C_ID_WIDTH-1:0] request_id,
output reg [C_ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
@ -55,7 +55,7 @@ module dmac_response_generator (
output [1:0] resp_resp
);
parameter C_ID_WIDTH = 3;
parameter ID_WIDTH = 3;
`include "inc_id.h"
`include "resp.h"

6
library/axi_dmac/response_handler.v
View File

@ -44,8 +44,8 @@ module dmac_response_handler (
output bready,
input [1:0] bresp,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input sync_id,
input enable,
@ -59,7 +59,7 @@ module dmac_response_handler (
output [1:0] resp_resp
);
parameter C_ID_WIDTH = 3;
parameter ID_WIDTH = 3;
`include "resp.h"
`include "inc_id.h"

14
library/axi_dmac/splitter.v
View File

@ -43,24 +43,24 @@ module splitter (
input s_valid,
output s_ready,
output [C_NUM_M-1:0] m_valid,
input [C_NUM_M-1:0] m_ready
output [NUM_M-1:0] m_valid,
input [NUM_M-1:0] m_ready
);
parameter C_NUM_M = 2;
parameter NUM_M = 2;
reg [C_NUM_M-1:0] acked;
reg [NUM_M-1:0] acked;
assign s_ready = &(m_ready | acked);
assign m_valid = s_valid ? ~acked : {C_NUM_M{1'b0}};
assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
always @(posedge clk)
begin
if (resetn == 1'b0) begin
acked <= {C_NUM_M{1'b0}};
acked <= {NUM_M{1'b0}};
end else begin
if (s_valid & s_ready)
acked <= {C_NUM_M{1'b0}};
acked <= {NUM_M{1'b0}};
else
acked <= acked | (m_ready & m_valid);
end

40
library/axi_dmac/src_axi_mm.v
View File

@ -42,8 +42,8 @@ module dmac_src_mm_axi (
input req_valid,
output req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input enable,
output enabled,
@ -55,17 +55,17 @@ module dmac_src_mm_axi (
input response_ready,
output [1:0] response_resp,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
output [C_ID_WIDTH-1:0] address_id,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
output fifo_valid,
input fifo_ready,
output [C_DMA_DATA_WIDTH-1:0] fifo_data,
output [DMA_DATA_WIDTH-1:0] fifo_data,
// Read address
input m_axi_arready,
@ -78,16 +78,16 @@ module dmac_src_mm_axi (
output [ 3:0] m_axi_arcache,
// Read data and response
input [C_DMA_DATA_WIDTH-1:0] m_axi_rdata,
input [DMA_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp
);
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter ID_WIDTH = 3;
parameter DMA_DATA_WIDTH = 64;
parameter BYTES_PER_BEAT_WIDTH = 3;
parameter BEATS_PER_BURST_WIDTH = 4;
`include "resp.h"
@ -105,7 +105,7 @@ assign response_valid = 1'b0;
assign response_resp = RESP_OKAY;
splitter #(
.C_NUM_M(2)
.NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
@ -122,10 +122,10 @@ splitter #(
);
dmac_address_generator #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
@ -156,9 +156,9 @@ dmac_address_generator #(
);
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DMA_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),

26
library/axi_dmac/src_axi_stream.v
View File

@ -45,30 +45,30 @@ module dmac_src_axi_stream (
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
output s_axis_ready,
input s_axis_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
input fifo_ready,
output fifo_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter ID_WIDTH = 3;
parameter S_AXIS_DATA_WIDTH = 64;
parameter LENGTH_WIDTH = 24;
parameter BEATS_PER_BURST_WIDTH = 4;
reg needs_sync = 1'b0;
wire sync = s_axis_user[0];
@ -90,10 +90,10 @@ begin
end
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),

24
library/axi_dmac/src_fifo_inf.v
View File

@ -45,29 +45,29 @@ module dmac_src_fifo_inf (
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
input en,
input [C_DATA_WIDTH-1:0] din,
input [DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
output xfer_req,
input fifo_ready,
output fifo_valid,
output [C_DATA_WIDTH-1:0] fifo_data,
output [DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter ID_WIDTH = 3;
parameter DATA_WIDTH = 64;
parameter BEATS_PER_BURST_WIDTH = 4;
wire ready;
@ -104,10 +104,10 @@ end
assign sync_id_ret = sync_id;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(clk),
.resetn(resetn),

26
library/axi_generic_adc/axi_generic_adc.v
View File

@ -1,6 +1,6 @@
module axi_generic_adc (
input adc_clk,
output [NUM_CHANNELS-1:0] adc_enable,
output [NUM_OF_CHANNELS-1:0] adc_enable,
input adc_dovf,
input s_axi_aclk,
@ -24,8 +24,8 @@ module axi_generic_adc (
input s_axi_rready
);
parameter NUM_CHANNELS = 2;
parameter PCORE_ID = 0;
parameter NUM_OF_CHANNELS = 2;
parameter ID = 0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
@ -43,9 +43,9 @@ wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS];
wire up_rack_s[0:NUM_CHANNELS];
wire up_wack_s[0:NUM_CHANNELS];
wire [31:0] up_rdata_s[0:NUM_OF_CHANNELS];
wire up_rack_s[0:NUM_OF_CHANNELS];
wire up_wack_s[0:NUM_OF_CHANNELS];
reg [31:0] up_rdata_r;
reg up_rack_r;
@ -60,7 +60,7 @@ begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= NUM_CHANNELS; j=j+1) begin
for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
@ -79,7 +79,7 @@ always @(negedge up_rstn or posedge up_clk) begin
end
end
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -110,11 +110,11 @@ up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS]),
.up_wack (up_wack_s[NUM_OF_CHANNELS]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS]),
.up_rack (up_rack_s[NUM_CHANNELS]));
.up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
.up_rack (up_rack_s[NUM_OF_CHANNELS]));
// up bus interface
@ -150,8 +150,8 @@ up_axi i_up_axi (
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i=i+1) begin
up_adc_channel #(.PCORE_ADC_CHID(i)) i_up_adc_channel (
for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin
up_adc_channel #(.ADC_CHANNEL_ID(i)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable[i]),

2
library/axi_hdmi_rx/axi_hdmi_rx.v
View File

@ -77,7 +77,7 @@ module axi_hdmi_rx (
// parameters
parameter PCORE_ID = 0;
parameter ID = 0;
// hdmi interface

2
library/axi_hdmi_rx/axi_hdmi_rx_core.v
View File

@ -321,7 +321,7 @@ module axi_hdmi_rx_core (
// super sampling, 422 to 444
ad_ss_422to444 #(.Cr_Cb_N(0), .DELAY_DATA_WIDTH(2)) i_ss (
ad_ss_422to444 #(.CR_CB_N(0), .DELAY_DATA_WIDTH(2)) i_ss (
.clk (hdmi_clk),
.s422_de (hdmi_de_422),
.s422_sync ({hdmi_sof_422, hdmi_de_422}),

18
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -101,10 +101,10 @@ module axi_hdmi_tx (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_Cr_Cb_N = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
parameter ID = 0;
parameter CR_CB_N = 0;
parameter DEVICE_TYPE = 0;
parameter EMBEDDED_SYNC = 0;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
@ -326,8 +326,8 @@ module axi_hdmi_tx (
// hdmi interface
axi_hdmi_tx_core #(
.Cr_Cb_N(PCORE_Cr_Cb_N),
.EMBEDDED_SYNC(PCORE_EMBEDDED_SYNC))
.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
@ -373,7 +373,7 @@ module axi_hdmi_tx (
// hdmi output clock
generate
if (PCORE_DEVICE_TYPE == XILINX_ULTRASCALE) begin
if (DEVICE_TYPE == XILINX_ULTRASCALE) begin
ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
.SR (1'b0),
.D1 (1'b1),
@ -381,7 +381,7 @@ module axi_hdmi_tx (
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
if (PCORE_DEVICE_TYPE == ALTERA_5SERIES) begin
if (DEVICE_TYPE == ALTERA_5SERIES) begin
altddio_out #(.WIDTH(1)) i_clk_oddr (
.aclr (1'b0),
.aset (1'b0),
@ -395,7 +395,7 @@ module axi_hdmi_tx (
.oe_out (),
.dataout (hdmi_out_clk));
end
if (PCORE_DEVICE_TYPE == XILINX_7SERIES) begin
if (DEVICE_TYPE == XILINX_7SERIES) begin
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),

26
library/axi_hdmi_tx/axi_hdmi_tx_alt.v
View File

@ -118,11 +118,11 @@ module axi_hdmi_tx_alt (
s_axi_rlast,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_Cr_Cb_N = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
parameter ID = 0;
parameter AXI_ID_WIDTH = 3;
parameter DEVICE_TYPE = 0;
parameter CR_CB_N = 0;
parameter EMBEDDED_SYNC = 0;
// hdmi interface
@ -167,7 +167,7 @@ module axi_hdmi_tx_alt (
input s_axi_aresetn;
input s_axi_awvalid;
input [13:0] s_axi_awaddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
input [(AXI_ID_WIDTH-1):0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst;
@ -182,11 +182,11 @@ module axi_hdmi_tx_alt (
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
output [(AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
input [(AXI_ID_WIDTH-1):0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst;
@ -197,7 +197,7 @@ module axi_hdmi_tx_alt (
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output [(AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
@ -214,10 +214,10 @@ module axi_hdmi_tx_alt (
// hdmi tx lite version
axi_hdmi_tx #(
.PCORE_ID (PCORE_ID),
.PCORE_Cr_Cb_N (PCORE_Cr_Cb_N),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC))
.ID (ID),
.CR_CB_N (CR_CB_N),
.DEVICE_TYPE (DEVICE_TYPE),
.EMBEDDED_SYNC (EMBEDDED_SYNC))
i_hdmi_tx (
.hdmi_clk (hdmi_clk),
.hdmi_out_clk (hdmi_out_clk),

6
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -101,7 +101,7 @@ module axi_hdmi_tx_core (
// parameters
parameter Cr_Cb_N = 0;
parameter CR_CB_N = 0;
parameter EMBEDDED_SYNC = 0;
// hdmi interface
@ -539,7 +539,7 @@ module axi_hdmi_tx_core (
// data memory
ad_mem #(.DATA_WIDTH(48), .ADDR_WIDTH(9)) i_mem (
ad_mem #(.DATA_WIDTH(48), .ADDRESS_WIDTH(9)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
@ -567,7 +567,7 @@ module axi_hdmi_tx_core (
// sub sampling, 444 to 422
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .Cr_Cb_N(Cr_Cb_N)) i_ss_444to422 (
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.s444_de (hdmi_24_data_e),
.s444_sync ({hdmi_24_hsync,

68
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
View File

@ -33,40 +33,40 @@ add_fileset_file axi_hdmi_tx_alt.v VERILOG PATH axi_hdmi_tx_alt.v TOP_LEVEL_F
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 16
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 16
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
add_parameter PCORE_AXI_ID_WIDTH INTEGER 0
set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3
set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH
set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER
set_parameter_property PCORE_AXI_ID_WIDTH UNITS None
set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true
add_parameter AXI_ID_WIDTH INTEGER 0
set_parameter_property AXI_ID_WIDTH DEFAULT_VALUE 3
set_parameter_property AXI_ID_WIDTH DISPLAY_NAME AXI_ID_WIDTH
set_parameter_property AXI_ID_WIDTH TYPE INTEGER
set_parameter_property AXI_ID_WIDTH UNITS None
set_parameter_property AXI_ID_WIDTH HDL_PARAMETER true
add_parameter PCORE_Cr_Cb_N INTEGER 0
set_parameter_property PCORE_Cr_Cb_N DEFAULT_VALUE 0
set_parameter_property PCORE_Cr_Cb_N DISPLAY_NAME PCORE_Cr_Cb_N
set_parameter_property PCORE_Cr_Cb_N TYPE INTEGER
set_parameter_property PCORE_Cr_Cb_N UNITS None
set_parameter_property PCORE_Cr_Cb_N HDL_PARAMETER true
add_parameter CR_CB_N INTEGER 0
set_parameter_property CR_CB_N DEFAULT_VALUE 0
set_parameter_property CR_CB_N DISPLAY_NAME CR_CB_N
set_parameter_property CR_CB_N TYPE INTEGER
set_parameter_property CR_CB_N UNITS None
set_parameter_property CR_CB_N HDL_PARAMETER true
add_parameter PCORE_EMBEDDED_SYNC INTEGER 0
set_parameter_property PCORE_EMBEDDED_SYNC DEFAULT_VALUE 0
set_parameter_property PCORE_EMBEDDED_SYNC DISPLAY_NAME PCORE_EMBEDDED_SYNC
set_parameter_property PCORE_EMBEDDED_SYNC TYPE INTEGER
set_parameter_property PCORE_EMBEDDED_SYNC UNITS None
set_parameter_property PCORE_EMBEDDED_SYNC HDL_PARAMETER true
add_parameter EMBEDDED_SYNC INTEGER 0
set_parameter_property EMBEDDED_SYNC DEFAULT_VALUE 0
set_parameter_property EMBEDDED_SYNC DISPLAY_NAME EMBEDDED_SYNC
set_parameter_property EMBEDDED_SYNC TYPE INTEGER
set_parameter_property EMBEDDED_SYNC UNITS None
set_parameter_property EMBEDDED_SYNC HDL_PARAMETER true
# axi4 slave
@ -97,7 +97,7 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_awid awid Input AXI_ID_WIDTH
add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2
@ -105,15 +105,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_bid bid Output AXI_ID_WIDTH
add_interface_port s_axi s_axi_arid arid Input AXI_ID_WIDTH
add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_rid rid Output AXI_ID_WIDTH
add_interface_port s_axi s_axi_rlast rlast Output 1
# hdmi interface

6
library/axi_jesd_gt/axi_jesd_gt.v
View File

@ -41,7 +41,7 @@ module axi_jesd_gt #(
parameter integer ID = 0,
parameter integer NUM_OF_LANES = 8,
parameter integer GTH_GTX_N = 0,
parameter integer GTH_OR_GTX_N = 0,
parameter integer QPLL0_ENABLE = 1,
parameter integer QPLL0_REFCLK_DIV = 1,
parameter [26:0] QPLL0_CFG = 27'h0680181,
@ -1445,7 +1445,7 @@ module axi_jesd_gt #(
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane_1
ad_gt_channel_1 #(
.ID (n),
.GTH_GTX_N (GTH_GTX_N),
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.PMA_RSV (PMA_RSV[n]),
.CPLL_FBDIV (CPLL_FBDIV[n]),
.RX_OUT_DIV (RX_OUT_DIV[n]),
@ -1540,7 +1540,7 @@ module axi_jesd_gt #(
ad_gt_common_1 #(
.ID (0),
.GTH_GTX_N (GTH_GTX_N),
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL0_ENABLE (QPLL0_ENABLE),
.QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV),
.QPLL0_CFG (QPLL0_CFG),

8
library/axi_jesd_xcvr/axi_jesd_xcvr.v
View File

@ -97,8 +97,8 @@ module axi_jesd_xcvr (
s_axi_rresp,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4;
@ -249,8 +249,8 @@ module axi_jesd_xcvr (
// processor
up_xcvr #(
.PCORE_ID(PCORE_ID),
.PCORE_DEVICE_TYPE(PCORE_DEVICE_TYPE))
.ID(ID),
.DEVICE_TYPE(DEVICE_TYPE))
i_up_xcvr (
.rst (rst),
.rx_clk (rx_clk),

24
library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
View File

@ -24,19 +24,19 @@ add_fileset_file axi_jesd_xcvr_constr.sdc SDC PATH axi_jesd_xcvr_constr.sdc
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
add_parameter PCORE_NUM_OF_TX_LANES INTEGER 0
set_parameter_property PCORE_NUM_OF_TX_LANES DEFAULT_VALUE 4

16
library/axi_mc_controller/axi_mc_controller.v
View File

@ -309,7 +309,7 @@ control_registers control_reg_inst(
.calibrate_adcs_o(),
.pwm_open_o(pwm_open_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
up_adc_channel #(.ADC_CHANNEL_ID(0)) adc_channel0(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c0),
@ -355,7 +355,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.up_rdata (rdata_c0_s),
.up_rack (rack_c0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
up_adc_channel #(.ADC_CHANNEL_ID(1)) adc_channel1(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c1),
@ -401,7 +401,7 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.up_rdata (rdata_c1_s),
.up_rack (rack_c1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
up_adc_channel #(.ADC_CHANNEL_ID(2)) adc_channel2(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c2),
@ -447,7 +447,7 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.up_rdata (rdata_c2_s),
.up_rack (rack_c2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
up_adc_channel #(.ADC_CHANNEL_ID(3)) adc_channel3(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c3),
@ -493,7 +493,7 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.up_rdata (rdata_c3_s),
.up_rack (rack_c3_s));
up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
up_adc_channel #(.ADC_CHANNEL_ID(4)) adc_channel4(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c4),
@ -539,7 +539,7 @@ up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.up_rdata (rdata_c4_s),
.up_rack (rack_c4_s));
up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
up_adc_channel #(.ADC_CHANNEL_ID(5)) adc_channel5(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c5),
@ -585,7 +585,7 @@ up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.up_rdata (rdata_c5_s),
.up_rack (rack_c5_s));
up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
up_adc_channel #(.ADC_CHANNEL_ID(6)) adc_channel6(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c6),
@ -631,7 +631,7 @@ up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.up_rdata (rdata_c6_s),
.up_rack (rack_c6_s));
up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
up_adc_channel #(.ADC_CHANNEL_ID(7)) adc_channel7(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c7),

8
library/axi_mc_current_monitor/axi_mc_current_monitor.v
View File

@ -197,7 +197,7 @@ ad7401 vbus_if(
.data_rd_ready_o(),
.adc_mdata_i(adc_vbus_dat_i));
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel_ia(
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_ia),
@ -243,7 +243,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
up_adc_channel #(.ADC_CHANNEL_ID(1)) i_up_adc_channel_ib(
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_ib),
@ -289,7 +289,7 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus(
up_adc_channel #(.ADC_CHANNEL_ID(2)) i_up_adc_channel_vbus(
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_vbus),
@ -335,7 +335,7 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus(
.up_rdata (up_rdata_2_s),
.up_rack (up_rack_2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_stub(
up_adc_channel #(.ADC_CHANNEL_ID(3)) i_up_adc_channel_stub(
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_stub),

6
library/axi_mc_speed/axi_mc_speed.v
View File

@ -134,7 +134,7 @@ end
// HALL sensors debouncers
debouncer
#( .DEBOUNCER_LEN(400))
#( .DEBOUNCER_LENGTH(400))
position_0(
.clk_i(ref_clk),
.rst_i(adc_rst),
@ -142,7 +142,7 @@ position_0(
.sig_o(position_s[0]));
debouncer
#( .DEBOUNCER_LEN(400))
#( .DEBOUNCER_LENGTH(400))
position_1(
.clk_i(ref_clk),
.rst_i(adc_rst),
@ -150,7 +150,7 @@ position_1(
.sig_o(position_s[1]));
debouncer
#( .DEBOUNCER_LEN(400))
#( .DEBOUNCER_LENGTH(400))
position_2(
.clk_i(ref_clk),
.rst_i(adc_rst),

10
library/axi_mc_speed/debouncer.v
View File

@ -60,7 +60,7 @@
module debouncer
//----------- Paramters Declarations -------------------------------------------
#(
parameter DEBOUNCER_LEN = 4
parameter DEBOUNCER_LENGTH = 4
)
//----------- Ports Declarations -----------------------------------------------
(
@ -72,7 +72,7 @@ module debouncer
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DEBOUNCER_LEN-1:0] shift_reg;
reg [DEBOUNCER_LENGTH-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
@ -87,12 +87,12 @@ begin
end
else
begin
shift_reg <= {shift_reg[DEBOUNCER_LEN-2:0], sig_i};
if(shift_reg == {DEBOUNCER_LEN{1'b1}})
shift_reg <= {shift_reg[DEBOUNCER_LENGTH-2:0], sig_i};
if(shift_reg == {DEBOUNCER_LENGTH{1'b1}})
begin
sig_o <= 1'b1;
end
else if(shift_reg == {DEBOUNCER_LEN{1'b0}})
else if(shift_reg == {DEBOUNCER_LENGTH{1'b0}})
begin
sig_o <= 1'b0;
end

38
library/common/ad_addsub.v
View File

@ -53,34 +53,34 @@ module ad_addsub (
// parameters
parameter A_WIDTH = 32;
parameter CONST_VALUE = 32'h1;
parameter ADD_SUB = 0;
parameter A_DATA_WIDTH = 32;
parameter B_DATA_VALUE = 32'h1;
parameter ADD_OR_SUB_N = 0;
localparam ADDER = 0;
localparam SUBSTRACTER = 1;
localparam ADDER = 1;
localparam SUBSTRACTER = 0;
// I/O definitions
input clk;
input [(A_WIDTH-1):0] A;
input [(A_WIDTH-1):0] Amax;
output [(A_WIDTH-1):0] out;
input [(A_DATA_WIDTH-1):0] A;
input [(A_DATA_WIDTH-1):0] Amax;
output [(A_DATA_WIDTH-1):0] out;
input CE;
// registers
reg [(A_WIDTH-1):0] out = 'b0;
reg [A_WIDTH:0] out_d = 'b0;
reg [A_WIDTH:0] out_d2 = 'b0;
reg [(A_WIDTH-1):0] A_d = 'b0;
reg [(A_WIDTH-1):0] A_d2 = 'b0;
reg [(A_WIDTH-1):0] Amax_d = 'b0;
reg [(A_WIDTH-1):0] Amax_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] out = 'b0;
reg [A_DATA_WIDTH:0] out_d = 'b0;
reg [A_DATA_WIDTH:0] out_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
reg [(A_WIDTH-1):0] B_reg = CONST_VALUE;
reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE;
// latch the inputs
@ -94,7 +94,7 @@ module ad_addsub (
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
if ( ADD_OR_SUB_N == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
@ -104,14 +104,14 @@ module ad_addsub (
// Resolve
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
if ( ADD_OR_SUB_N == ADDER ) begin
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_WIDTH] == 1'b1 ) begin
if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;

2
library/common/ad_axis_dma_rx.v
View File

@ -315,7 +315,7 @@ module ad_axis_dma_rx (
// buffer (mainly for clock domain transfer)
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),

2
library/common/ad_axis_dma_tx.v
View File

@ -266,7 +266,7 @@ module ad_axis_dma_tx (
// memory
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (
.clka (dma_clk),
.wea (dma_wr),
.addra (dma_waddr),

4
library/common/ad_csc_1_mul.v
View File

@ -103,8 +103,8 @@ module ad_csc_1_mul (
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (17),
.WIDTH_B (9))
.A_DATA_WIDTH (17),
.B_DATA_WIDTH (9))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),

6
library/common/ad_gt_channel.v
View File

@ -104,7 +104,7 @@ module ad_gt_channel (
// parameters
parameter integer GTH_GTX_N = 0;
parameter integer GTH_OR_GTX_N = 0;
parameter [31:0] PMA_RSV = 32'h00018480;
parameter integer CPLL_FBDIV = 2;
parameter integer RX_OUT_DIV = 1;
@ -248,7 +248,7 @@ module ad_gt_channel (
assign tx_out_clk = tx_out_clk_s;
end
if (GTH_GTX_N == 0) begin
if (GTH_OR_GTX_N == 0) begin
assign rx_sys_clk_sel_s = rx_sys_clk_sel;
assign tx_sys_clk_sel_s = tx_sys_clk_sel;
@ -700,7 +700,7 @@ module ad_gt_channel (
.TXQPISENN ());
end
if (GTH_GTX_N == 1) begin
if (GTH_OR_GTX_N == 1) begin
assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;

8
library/common/ad_gt_channel_1.v
View File

@ -146,7 +146,7 @@ module ad_gt_channel_1 (
// parameters
parameter integer ID = 0;
parameter integer GTH_GTX_N = 0;
parameter integer GTH_OR_GTX_N = 0;
parameter [31:0] PMA_RSV = 32'h00018480;
parameter integer CPLL_FBDIV = 2;
parameter integer RX_OUT_DIV = 1;
@ -320,7 +320,7 @@ module ad_gt_channel_1 (
.rx_data (rx_data));
ad_gt_channel #(
.GTH_GTX_N (GTH_GTX_N),
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.PMA_RSV (PMA_RSV),
.CPLL_FBDIV (CPLL_FBDIV),
.RX_OUT_DIV (RX_OUT_DIV),
@ -380,7 +380,7 @@ module ad_gt_channel_1 (
.up_drp_rxrate (up_drp_rxrate_s));
ad_gt_es #(
.GTH_GTX_N (GTH_GTX_N))
.GTH_OR_GTX_N (GTH_OR_GTX_N))
i_es (
.lpm_dfe_n (lpm_dfe_n_s),
.up_rstn (up_rstn),
@ -421,7 +421,7 @@ module ad_gt_channel_1 (
up_gt_channel #(
.ID (ID),
.GTH_GTX_N (GTH_GTX_N))
.GTH_OR_GTX_N (GTH_OR_GTX_N))
i_up (
.pll_rst (pll_rst),
.lpm_dfe_n (lpm_dfe_n_s),

6
library/common/ad_gt_common.v
View File

@ -59,7 +59,7 @@ module ad_gt_common (
// parameters
parameter integer GTH_GTX_N = 0;
parameter integer GTH_OR_GTX_N = 0;
parameter integer QPLL_ENABLE = 1;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [26:0] QPLL_CFG = 27'h06801C1;
@ -96,7 +96,7 @@ module ad_gt_common (
assign up_drp_ready = 1'd0;
end
if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 0)) begin
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin
GTXE2_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_QPLLREFCLK_SEL (3'b001),
@ -155,7 +155,7 @@ module ad_gt_common (
.RCALENB (1'd1));
end
if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 1)) begin
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin
GTHE3_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION (2),

8
library/common/ad_gt_common_1.v
View File

@ -66,7 +66,7 @@ module ad_gt_common_1 (
// parameters
parameter integer ID = 0;
parameter integer GTH_GTX_N = 0;
parameter integer GTH_OR_GTX_N = 0;
parameter integer QPLL0_ENABLE = 1;
parameter integer QPLL0_REFCLK_DIV = 2;
parameter [26:0] QPLL0_CFG = 27'h06801C1;
@ -146,7 +146,7 @@ module ad_gt_common_1 (
// instantiations
ad_gt_common #(
.GTH_GTX_N (GTH_GTX_N),
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL_ENABLE (QPLL0_ENABLE),
.QPLL_REFCLK_DIV (QPLL0_REFCLK_DIV),
.QPLL_CFG (QPLL0_CFG),
@ -167,7 +167,7 @@ module ad_gt_common_1 (
.up_drp_ready (up_drp_qpll0_ready_s));
ad_gt_common #(
.GTH_GTX_N (GTH_GTX_N),
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL_ENABLE (QPLL1_ENABLE),
.QPLL_REFCLK_DIV (QPLL1_REFCLK_DIV),
.QPLL_CFG (QPLL1_CFG),
@ -188,7 +188,7 @@ module ad_gt_common_1 (
.up_drp_ready (up_drp_qpll1_ready_s));
up_gt #(
.GTH_GTX_N (GTH_GTX_N),
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.ID (ID))
i_up (
.up_drp_qpll0_sel (up_drp_qpll0_sel_s),

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