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jesd204_tpl: reduce address width of TPLs 

Registers from this component can fit in the 2k address range.
Since Vivado's minimal address range is 4k, use that instead.
This will allow placing the independent TPLs to base addresses
that mach the addresses from the monolithic blocks ensuring no software
intervention.
main
Laszlo Nagy 2018-11-20 13:57:03 +00:00 committed by Laszlo Nagy
parent 26c0121f4d
commit 57f83f86ab
4 changed files with 14 additions and 12 deletions
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4
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
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@ -57,7 +57,7 @@ module ad_ip_jesd204_tpl_adc #(
input s_axi_awvalid,
output s_axi_awready,
input [15:0] s_axi_awaddr,
input [11:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
@ -71,7 +71,7 @@ module ad_ip_jesd204_tpl_adc #(
input s_axi_arvalid,
output s_axi_arready,
input [15:0] s_axi_araddr,
input [11:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,

8
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
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@ -32,7 +32,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [11:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
@ -43,7 +43,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [11:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
@ -124,7 +124,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.up_rstn (up_rstn),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awaddr ({4'b0,s_axi_awaddr}),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
@ -134,7 +134,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_araddr ({4'b0,s_axi_araddr}),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),

4
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
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@ -57,7 +57,7 @@ module ad_ip_jesd204_tpl_dac #(
input s_axi_awvalid,
output s_axi_awready,
input [15:0] s_axi_awaddr,
input [11:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
@ -71,7 +71,7 @@ module ad_ip_jesd204_tpl_dac #(
input s_axi_arvalid,
output s_axi_arready,
input [15:0] s_axi_araddr,
input [11:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,

10
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
View File

@ -33,7 +33,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
input s_axi_awvalid,
output s_axi_awready,
input [15:0] s_axi_awaddr,
input [11:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
@ -43,7 +43,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
input s_axi_arvalid,
output s_axi_arready,
input [15:0] s_axi_araddr,
input [11:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
@ -111,7 +111,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.up_rstn (up_rstn),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awaddr ({4'b0,s_axi_awaddr}),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
@ -121,7 +121,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_araddr ({4'b0,s_axi_araddr}),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
@ -162,6 +162,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
// dac common processor interface
up_dac_common #(
.COMMON_ID(6'h0),
.ID (ID),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (1),
@ -214,6 +215,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
up_dac_channel #(
.COMMON_ID(6'h1),
.CHANNEL_ID (i),
.USERPORTS_DISABLE (1),
.IQCORRECTION_DISABLE (1)