From 581892b22a3896bcfdd0295f7140e41e88ef3e03 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 3 Oct 2014 12:32:08 +0300
Subject: [PATCH] axi_ad9265: Updated project with new up independent
 read/write

---
 library/axi_ad9265/axi_ad9265.v         | 51 +++++++++++++++----------
 library/axi_ad9265/axi_ad9265_channel.v | 30 +++++++++------
 2 files changed, 49 insertions(+), 32 deletions(-)

diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v
index 0348df605..9ca647851 100644
--- a/library/axi_ad9265/axi_ad9265.v
+++ b/library/axi_ad9265/axi_ad9265.v
@@ -143,7 +143,8 @@ module axi_ad9265 (
   reg             up_status_pn_oos = 'd0;
   reg             up_status_or = 'd0;
   reg     [31:0]  up_rdata = 'd0;
-  reg             up_ack = 'd0;
+  reg             up_wack = 'd0;
+  reg             up_rack = 'd0;
 
   // internal clocks & resets
 
@@ -167,12 +168,14 @@ module axi_ad9265 (
   wire    [ 4:0]  delay_rdata_s;
   wire            delay_ack_t_s;
   wire            delay_locked_s;
-  wire            up_sel_s;
-  wire            up_wr_s;
-  wire    [13:0]  up_addr_s;
-  wire    [31:0]  up_wdata_s;
+  wire    [13:0]  up_raddr_s;
   wire    [31:0]  up_rdata_s[0:1];
-  wire            up_ack_s[0:1];
+  wire            up_rack_s[0:1];
+  wire            up_wack_s[0:1];
+  wire            up_wreq_s;
+  wire    [13:0]  up_waddr_s;
+  wire    [31:0]  up_wdata_s;
+  wire            up_rreq_s;
 
   // signal name changes
 
@@ -187,13 +190,15 @@ module axi_ad9265 (
       up_status_pn_oos <= 'd0;
       up_status_or <= 'd0;
       up_rdata <= 'd0;
-      up_ack <= 'd0;
+      up_rack <= 'd0;
+      up_wack <= 'd0;
     end else begin
       up_status_pn_err <= up_status_pn_err_s;
       up_status_pn_oos <= up_status_pn_oos_s;
       up_status_or <= up_status_or_s;
       up_rdata <= up_rdata_s[0] | up_rdata_s[1];
-      up_ack <= up_ack_s[0] | up_ack_s[1];
+      up_rack <= up_rack_s[0] | up_rack_s[1];
+      up_wack <= up_wack_s[0] | up_wack_s[1];
     end
   end
 
@@ -215,12 +220,14 @@ module axi_ad9265 (
     .up_adc_or (up_status_or_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_sel (up_sel_s),
-    .up_wr (up_wr_s),
-    .up_addr (up_addr_s),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
     .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_s[0]),
-    .up_ack (up_ack_s[0]));
+    .up_rack (up_rack_s[0]));
 
   // main (device interface)
 
@@ -288,12 +295,14 @@ module axi_ad9265 (
     .up_adc_gpio_out (),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_sel (up_sel_s),
-    .up_wr (up_wr_s),
-    .up_addr (up_addr_s),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
     .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_s[1]),
-    .up_ack (up_ack_s[1]));
+    .up_rack (up_rack_s[1]));
 
   // up bus interface
 
@@ -317,12 +326,14 @@ module axi_ad9265 (
     .up_axi_rresp (s_axi_rresp),
     .up_axi_rdata (s_axi_rdata),
     .up_axi_rready (s_axi_rready),
-    .up_sel (up_sel_s),
-    .up_wr (up_wr_s),
-    .up_addr (up_addr_s),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
     .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
     .up_rdata (up_rdata),
-    .up_ack (up_ack));
+    .up_rack (up_rack));
 
 endmodule
 
diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v
index 04313f4f2..765319746 100644
--- a/library/axi_ad9265/axi_ad9265_channel.v
+++ b/library/axi_ad9265/axi_ad9265_channel.v
@@ -62,12 +62,14 @@ module axi_ad9265_channel (
 
   up_rstn,
   up_clk,
-  up_sel,
-  up_wr,
-  up_addr,
+  up_wreq,
+  up_waddr,
   up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
   up_rdata,
-  up_ack);
+  up_rack);
 
   // parameters
 
@@ -94,12 +96,14 @@ module axi_ad9265_channel (
 
   input           up_rstn;
   input           up_clk;
-  input           up_sel;
-  input           up_wr;
-  input   [13:0]  up_addr;
+  input           up_wreq;
+  input   [13:0]  up_waddr;
   input   [31:0]  up_wdata;
+  output          up_wack;
+  input           up_rreq;
+  input   [13:0]  up_raddr;
   output  [31:0]  up_rdata;
-  output          up_ack;
+  output          up_rack;
 
   // internal signals
 
@@ -192,12 +196,14 @@ module axi_ad9265_channel (
     .adc_usr_decimation_n (16'd1),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_sel (up_sel),
-    .up_wr (up_wr),
-    .up_addr (up_addr),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
     .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
     .up_rdata (up_rdata),
-    .up_ack (up_ack));
+    .up_rack (up_rack));
 
 endmodule