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util_rfifo: updates

main
Rejeesh Kutty 2016-05-16 10:57:02 -04:00
parent 82d43783f1
commit 58a2a3259c
2 changed files with 333 additions and 88 deletions
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398
library/util_rfifo/util_rfifo.v
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@ -34,131 +34,353 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// allows conversions between the dac (or similar) interface to the dma (or similar).
// * asymmetric bus widths in the range allowed by the fifo
// * frequency -- dma can run slower at reduced channels
// * drop or add channels -- pre processing samples
// * interface axis -- allows axi-stream interface
//
// in all cases bandwidth requirements must be met (read <= write).
//
// axis-interface support
// * connect dma_rd as axis_ready, make sure data is present (use dma_rd as
// enable for the data pipe line). leave axis_valid open!
// * make sure read bandwidth <= write bandwidth (or interpolate samples)
//
// the fifo is external- connect all the fifo_* signals to a fifo generator IP.
// configure the IP to match the buswidths & clocks.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
module util_rfifo ( module util_rfifo (
// dac interface // d-in interface
dac_clk, din_rstn,
dac_rd, din_clk,
dac_rdata, din_enable_0,
dac_runf, din_valid_0,
din_data_0,
din_enable_1,
din_valid_1,
din_data_1,
din_enable_2,
din_valid_2,
din_data_2,
din_enable_3,
din_valid_3,
din_data_3,
din_enable_4,
din_valid_4,
din_data_4,
din_enable_5,
din_valid_5,
din_data_5,
din_enable_6,
din_valid_6,
din_data_6,
din_enable_7,
din_valid_7,
din_data_7,
din_unf,
// dma interface // d-out interface
dma_clk, dout_rst,
dma_rd, dout_clk,
dma_rdata, dout_enable_0,
dma_runf, dout_valid_0,
dout_data_0,
// fifo interface dout_enable_1,
dout_valid_1,
fifo_rst, dout_data_1,
fifo_rstn, dout_enable_2,
fifo_wr, dout_valid_2,
fifo_wdata, dout_data_2,
fifo_wfull, dout_enable_3,
fifo_rd, dout_valid_3,
fifo_rdata, dout_data_3,
fifo_rempty, dout_enable_4,
fifo_runf); dout_valid_4,
dout_data_4,
dout_enable_5,
dout_valid_5,
dout_data_5,
dout_enable_6,
dout_valid_6,
dout_data_6,
dout_enable_7,
dout_valid_7,
dout_data_7,
dout_unf);
// parameters // parameters
parameter DAC_DATA_WIDTH = 32; parameter NUM_OF_CHANNELS = 4;
parameter DMA_DATA_WIDTH = 64; parameter DIN_DATA_WIDTH = 32;
parameter DOUT_DATA_WIDTH = 64;
parameter DIN_ADDRESS_WIDTH = 8;
// dac interface localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4;
localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
input dac_clk; // d-in interface
input dac_rd;
output [DAC_DATA_WIDTH-1:0] dac_rdata;
output dac_runf;
// dma interface input din_rstn;
input din_clk;
output din_enable_0;
output din_valid_0;
input [DIN_DATA_WIDTH-1:0] din_data_0;
output din_enable_1;
output din_valid_1;
input [DIN_DATA_WIDTH-1:0] din_data_1;
output din_enable_2;
output din_valid_2;
input [DIN_DATA_WIDTH-1:0] din_data_2;
output din_enable_3;
output din_valid_3;
input [DIN_DATA_WIDTH-1:0] din_data_3;
output din_enable_4;
output din_valid_4;
input [DIN_DATA_WIDTH-1:0] din_data_4;
output din_enable_5;
output din_valid_5;
input [DIN_DATA_WIDTH-1:0] din_data_5;
output din_enable_6;
output din_valid_6;
input [DIN_DATA_WIDTH-1:0] din_data_6;
output din_enable_7;
output din_valid_7;
input [DIN_DATA_WIDTH-1:0] din_data_7;
input din_unf;
input dma_clk; // dout interface
output dma_rd;
input [DMA_DATA_WIDTH-1:0] dma_rdata;
input dma_runf;
// fifo interface input dout_rst;
input dout_clk;
output fifo_rst; input dout_enable_0;
output fifo_rstn; input dout_valid_0;
output fifo_wr; output [DOUT_DATA_WIDTH-1:0] dout_data_0;
output [DMA_DATA_WIDTH-1:0] fifo_wdata; input dout_enable_1;
input fifo_wfull; input dout_valid_1;
output fifo_rd; output [DOUT_DATA_WIDTH-1:0] dout_data_1;
input [DAC_DATA_WIDTH-1:0] fifo_rdata; input dout_enable_2;
input fifo_rempty; input dout_valid_2;
input fifo_runf; output [DOUT_DATA_WIDTH-1:0] dout_data_2;
input dout_enable_3;
input dout_valid_3;
output [DOUT_DATA_WIDTH-1:0] dout_data_3;
input dout_enable_4;
input dout_valid_4;
output [DOUT_DATA_WIDTH-1:0] dout_data_4;
input dout_enable_5;
input dout_valid_5;
output [DOUT_DATA_WIDTH-1:0] dout_data_5;
input dout_enable_6;
input dout_valid_6;
output [DOUT_DATA_WIDTH-1:0] dout_data_6;
input dout_enable_7;
input dout_valid_7;
output [DOUT_DATA_WIDTH-1:0] dout_data_7;
output dout_unf;
// internal registers // internal registers
reg [ 1:0] dac_runf_m = 'd0; reg [(DATA_WIDTH-1):0] din_wdata = 'd0;
reg dac_runf = 'd0; reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0;
reg dma_rd = 'd0; reg din_wr = 'd0;
reg [ 6:0] din_req_cnt = 'd0;
reg [ 7:0] din_enable_m1 = 'd0;
reg [ 7:0] din_enable = 'd0;
reg din_req_t_m1 = 'd0;
reg din_req_t_m2 = 'd0;
reg din_req_t_m3 = 'd0;
reg [(T_DOUT_DATA_WIDTH+1):0] dout_data = 'd0;
reg [(DATA_WIDTH-1):0] dout_rdata = 'd0;
reg [ 7:0] dout_enable = 'd0;
reg dout_req_t = 'd0;
reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0;
reg dout_unf_m1 = 'd0;
reg dout_unf = 'd0;
// dac underflow // internal signals
always @(posedge dac_clk) begin wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;
dac_runf_m[0] <= dma_runf | fifo_runf; wire din_req_s;
dac_runf_m[1] <= dac_runf_m[0]; wire [ 7:0] dout_enable_s;
dac_runf <= dac_runf_m[1]; wire [ 7:0] dout_valid_s;
end wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;
wire [(DATA_WIDTH-1):0] dout_rdata_s;
// dma read // variables
always @(posedge dma_clk) begin genvar n;
dma_rd <= ~fifo_wfull;
end
// write // enables & valids
assign fifo_wr = dma_rd; assign din_enable_7 = din_enable[7];
assign din_enable_6 = din_enable[6];
assign din_enable_5 = din_enable[5];
assign din_enable_4 = din_enable[4];
assign din_enable_3 = din_enable[3];
assign din_enable_2 = din_enable[2];
assign din_enable_1 = din_enable[1];
assign din_enable_0 = din_enable[0];
assign din_valid_7 = din_req_cnt[6];
assign din_valid_6 = din_req_cnt[6];
assign din_valid_5 = din_req_cnt[6];
assign din_valid_4 = din_req_cnt[6];
assign din_valid_3 = din_req_cnt[6];
assign din_valid_2 = din_req_cnt[6];
assign din_valid_1 = din_req_cnt[6];
assign din_valid_0 = din_req_cnt[6];
assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
din_data_3, din_data_2, din_data_1, din_data_0};
// dout_width >= din_width only
genvar s;
generate generate
for (s = 0; s < DMA_DATA_WIDTH; s = s + 1) begin: g_wdata for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
assign fifo_wdata[s] = dma_rdata[(DMA_DATA_WIDTH-1)-s]; if (M_MEM_RATIO == 1) begin
always @(posedge din_clk) begin
if (din_req_cnt[6] == 1'b1) begin
din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
end
end
end else begin
always @(posedge din_clk) begin
if (din_req_cnt[6] == 1'b1) begin
din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
{din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
end
end
end
end end
endgenerate endgenerate
// read always @(posedge din_clk or negedge din_rstn) begin
if (din_rstn == 1'b0) begin
din_waddr <= 'd0;
din_wr <= 1'd0;
end else begin
if (din_wr == 1'b1) begin
din_waddr <= din_waddr + 1'b1;
end
case (M_MEM_RATIO)
8: din_wr <= din_req_cnt[6] & din_req_cnt[2] & din_req_cnt[1] & din_req_cnt[0];
4: din_wr <= din_req_cnt[6] & din_req_cnt[1] & din_req_cnt[0];
2: din_wr <= din_req_cnt[6] & din_req_cnt[0];
default: din_wr <= din_req_cnt[6];
endcase
end
end
assign fifo_rd = ~fifo_rempty & dac_rd; always @(posedge din_clk or negedge din_rstn) begin
if (din_rstn == 1'b0) begin
din_req_cnt <= 'd0;
end else begin
if (din_req_s == 1'b1) begin
case (M_MEM_RATIO)
8: din_req_cnt <= 7'h40;
4: din_req_cnt <= 7'h60;
2: din_req_cnt <= 7'h70;
default: din_req_cnt <= 7'h78;
endcase
end else if (din_req_cnt[6] == 1'b1) begin
din_req_cnt <= din_req_cnt + 1'b1;
end
end
end
assign din_req_s = din_req_t_m3 ^ din_req_t_m2;
always @(posedge din_clk or negedge din_rstn) begin
if (din_rstn == 1'b0) begin
din_enable_m1 <= 'd0;
din_enable <= 'd0;
din_req_t_m1 <= 'd0;
din_req_t_m2 <= 'd0;
din_req_t_m3 <= 'd0;
end else begin
din_enable_m1 <= dout_enable;
din_enable <= din_enable_m1;
din_req_t_m1 <= dout_req_t;
din_req_t_m2 <= din_req_t_m1;
din_req_t_m3 <= din_req_t_m2;
end
end
// read interface (bus expansion and/or clock conversion)
assign dout_enable_s = { dout_enable_7, dout_enable_6, dout_enable_5, dout_enable_4,
dout_enable_3, dout_enable_2, dout_enable_1, dout_enable_0};
assign dout_valid_s = { dout_valid_7, dout_valid_6, dout_valid_5, dout_valid_4,
dout_valid_3, dout_valid_2, dout_valid_1, dout_valid_0};
genvar m;
generate generate
for (m = 0; m < DAC_DATA_WIDTH; m = m + 1) begin: g_rdata if (NUM_OF_CHANNELS >= 8) begin
assign dac_rdata[m] = fifo_rdata[(DAC_DATA_WIDTH-1)-m]; assign dout_data_s = dout_rdata;
end else begin
assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata;
end end
endgenerate endgenerate
// reset & resetn assign dout_data_7 = dout_data[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
assign dout_data_6 = dout_data[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
assign dout_data_5 = dout_data[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
assign dout_data_4 = dout_data[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
assign dout_data_3 = dout_data[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
assign dout_data_2 = dout_data[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
assign dout_data_1 = dout_data[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
assign dout_data_0 = dout_data[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
assign fifo_rst = 1'b0; generate
assign fifo_rstn = 1'b1; for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_out
always @(posedge dout_clk) begin
if (dout_rst == 1'b1) begin
dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= 'd0;
end else if (dout_valid_s[n] == 1'b1) begin
dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
dout_data_s[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)];
end
end
end
endgenerate
always @(posedge dout_clk) begin
dout_rdata <= dout_rdata_s;
end
always @(posedge dout_clk) begin
if (dout_rst == 1'b1) begin
dout_enable <= 'd0;
dout_req_t <= 'd0;
dout_raddr <= 'd0;
end else begin
dout_enable <= dout_enable_s;
if (dout_valid_s[0] == 1'b1) begin
if (dout_raddr[2:0] == 3'd0) begin
dout_req_t <= ~dout_req_t;
end
dout_raddr <= dout_raddr + 1'b1;
end
end
end
always @(posedge dout_clk) begin
if (dout_rst == 1'b1) begin
dout_unf_m1 <= 'd0;
dout_unf <= 'd0;
end else begin
dout_unf_m1 <= din_unf;
dout_unf <= dout_unf_m1;
end
end
// instantiations
ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
.clka (din_clk),
.wea (din_wr),
.addra (din_waddr),
.dina (din_wdata),
.clkb (dout_clk),
.addrb (dout_raddr),
.doutb (dout_rdata_s));
endmodule endmodule

23
library/util_rfifo/util_rfifo_ip.tcl
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@ -5,11 +5,34 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_rfifo adi_ip_create util_rfifo
adi_ip_files util_rfifo [list \ adi_ip_files util_rfifo [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"util_rfifo.v" ] "util_rfifo.v" ]
adi_ip_properties_lite util_rfifo adi_ip_properties_lite util_rfifo
adi_ip_constraints util_rfifo [list \
"util_rfifo_constr.xdc" ]
ipx::remove_all_bus_interface [ipx::current_core] ipx::remove_all_bus_interface [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]