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ad9265_fmc: Updated project to the new flow

main
Adrian Costina 2015-03-24 10:37:06 +02:00
parent 919c02b57a
commit 58a5e0142c
5 changed files with 161 additions and 278 deletions
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224
projects/ad9265_fmc/common/ad9265_bd.tcl
View File

@ -1,28 +1,12 @@
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
# ad9265
set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p]
set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n]
set adc_data_or_p [create_bd_port -dir I adc_data_or_p]
set adc_data_or_n [create_bd_port -dir I adc_data_or_n]
set adc_data_in_n [create_bd_port -dir I -from 7 -to 0 adc_data_in_n]
set adc_data_in_p [create_bd_port -dir I -from 7 -to 0 adc_data_in_p]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_csn0 [create_bd_port -dir O spi_csn0]
set spi_csn1 [create_bd_port -dir O spi_csn1]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
# interrupts
set ad9265_spi [create_bd_port -dir O ad9265_spi]
set ad9265_dma_irq [create_bd_port -dir O ad9265_dma_irq]
create_bd_port -dir I adc_clk_in_p
create_bd_port -dir I adc_clk_in_n
create_bd_port -dir I adc_data_or_p
create_bd_port -dir I adc_data_or_n
create_bd_port -dir I -from 7 -to 0 adc_data_in_n
create_bd_port -dir I -from 7 -to 0 adc_data_in_p
# adc peripheral
@ -42,188 +26,66 @@ set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma
if {$sys_zynq == 1} {
set axi_ad9265_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9265_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9265_dma_interconnect
}
# spi
if {$sys_zynq == 0} {
set axi_ad9265_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9265_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9265_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9265_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9265_spi
} else {
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
}
# additions to default configuration
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_MI {10}] $axi_cpu_interconnect
} else {
set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
}
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_SI {9}] $axi_mem_interconnect
}
# clock for ila
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
set_property LEFT 31 [get_bd_ports GPIO_I]
set_property LEFT 31 [get_bd_ports GPIO_O]
set_property LEFT 31 [get_bd_ports GPIO_T]
set sys_ila_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_ila_clk $sys_ila_clk_source
} else {
set ila_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 ila_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200}] $ila_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $ila_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $ila_clkgen
set_property -dict [list CONFIG.USE_RESET {false}] $ila_clkgen
connect_bd_net -net sys_200m_clk [get_bd_pins ila_clkgen/clk_in1]
set sys_ila_clk_source [get_bd_pins ila_clkgen/clk_out1]
connect_bd_net -net sys_ila_clk $sys_ila_clk_source
}
# connections (spi)
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9265_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9265_spi/ss_o]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9265_spi/sck_i]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9265_spi/sck_o]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9265_spi/io0_i]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9265_spi/io0_o]
connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9265_spi/io1_i]
} else {
connect_bd_net -net spi_csn0 [get_bd_ports spi_csn0] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn1 [get_bd_ports spi_csn1] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
}
ad_connect sys_ila_clk sys_ps7/FCLK_CLK2
# connections (ad9265)
connect_bd_net -net axi_ad9265_adc_clk_in_n [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9265/adc_clk_in_p]
connect_bd_net -net axi_ad9265_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9265/adc_clk_in_n]
connect_bd_net -net axi_ad9265_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9265/adc_data_in_n]
connect_bd_net -net axi_ad9265_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9265/adc_data_in_p]
connect_bd_net -net axi_ad9265_adc_data_or_p [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9265/adc_or_in_p]
connect_bd_net -net axi_ad9265_adc_data_or_n [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9265/adc_or_in_n]
ad_connect adc_clk_in_p axi_ad9265/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9265/adc_clk_in_n
ad_connect adc_data_in_n axi_ad9265/adc_data_in_n
ad_connect adc_data_in_p axi_ad9265/adc_data_in_p
ad_connect adc_data_or_p axi_ad9265/adc_or_in_p
ad_connect adc_data_or_n axi_ad9265/adc_or_in_n
set adc_125m_clk_source [get_bd_pins axi_ad9265/adc_clk]
ad_connect ad9265_clk axi_ad9265/adc_clk
connect_bd_net -net adc_125m_clk [get_bd_pins axi_ad9265_dma/fifo_wr_clk] $adc_125m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265/delay_clk]
ad_connect ad9265_clk axi_ad9265_dma/fifo_wr_clk
ad_connect sys_200m_clk axi_ad9265/delay_clk
connect_bd_net -net axi_ad9265_dma_valid [get_bd_pins axi_ad9265/adc_valid] [get_bd_pins axi_ad9265_dma/fifo_wr_en]
connect_bd_net -net axi_ad9265_dma_data [get_bd_pins axi_ad9265/adc_data] [get_bd_pins axi_ad9265_dma/fifo_wr_din]
connect_bd_net -net axi_ad9265_dma_dovf [get_bd_pins axi_ad9265/adc_dovf] [get_bd_pins axi_ad9265_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports ad9265_dma_irq]
# interconnect (cpu)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma/s_axi_aresetn]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9265_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9265/s_axi]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9265_spi/axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_spi/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_spi/s_axi_aresetn]
connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_ports ad9265_spi]
}
# interconnect (mem/adc)
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9265_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9265_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_ad9265_dma_interconnect_s0 [get_bd_intf_pins axi_ad9265_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9265_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9265_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9265_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma_interconnect/S00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma_interconnect/ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma_interconnect/M00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
}
ad_connect axi_ad9265/adc_valid axi_ad9265_dma/fifo_wr_en
ad_connect axi_ad9265/adc_data axi_ad9265_dma/fifo_wr_din
ad_connect axi_ad9265/adc_dovf axi_ad9265_dma/fifo_wr_overflow
# ila (with fifo to prevent timing failure)
p_sys_wfifo [current_bd_instance .] ila_wfifo 16 32
connect_bd_net -net adc_125m_clk [get_bd_pins ila_wfifo/m_clk] $adc_125m_clk_source
connect_bd_net -net sys_ila_clk [get_bd_pins ila_wfifo/s_clk] $sys_ila_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins ila_wfifo/rstn] $sys_100m_resetn_source
ad_connect ad9265_clk ila_wfifo/adc_clk
ad_connect sys_ila_clk ila_wfifo/dma_clk
ad_connect sys_cpu_resetn ila_wfifo/adc_rst
set ila_ad9265_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_ad9265_mon]
set ila_ad9265_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_ad9265_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {32}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9265_mon
connect_bd_net -net axi_ad9265_dma_valid [get_bd_pins ila_wfifo/m_wr] [get_bd_pins axi_ad9265/adc_valid]
connect_bd_net -net axi_ad9265_dma_data [get_bd_pins ila_wfifo/m_wdata] [get_bd_pins axi_ad9265/adc_data]
connect_bd_net -net axi_ad9265_adc_dovf [get_bd_pins ila_wfifo/m_wovf] [get_bd_pins axi_ad9265/adc_dunf]
connect_bd_net -net ila_fifo_wr [get_bd_pins ila_wfifo/s_wr] [get_bd_pins ila_ad9265_mon/PROBE0]
connect_bd_net -net ila_fifo_wdata [get_bd_pins ila_wfifo/s_wdata] [get_bd_pins ila_ad9265_mon/PROBE1]
connect_bd_net -net sys_ila_clk [get_bd_pins ila_ad9265_mon/clk] $sys_ila_clk_source
ad_connect ila_wfifo/adc_wr axi_ad9265/adc_valid
ad_connect ila_wfifo/adc_wdata axi_ad9265/adc_data
ad_connect ila_wfifo/adc_wovf axi_ad9265/adc_dunf
ad_connect ila_wfifo/dma_wr ila_ad9265_mon/PROBE0
ad_connect ila_wfifo/dma_wdata ila_ad9265_mon/PROBE1
ad_connect sys_ila_clk ila_ad9265_mon/clk
# address mapping
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9265/s_axi/axi_lite] SEG_data_ad9265_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9265_dma/s_axi/axi_lite] SEG_data_ad9265_dma
ad_cpu_interconnect 0x44A00000 axi_ad9265
ad_cpu_interconnect 0x44A30000 axi_ad9265_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9265_spi/axi_lite/Reg] SEG_data_ad9265_spi
}
# interconnect (adc)
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9265_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9265_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
}
ad_mem_hp2_interconnect ad9265_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect ad9265_clk axi_ad9265_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad9265_dma/m_dest_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-13 axi_ad9265_dma/irq

1
projects/ad9265_fmc/zc706/system_bd.tcl
View File

@ -1,3 +1,4 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/ad9265_bd.tcl

2
projects/ad9265_fmc/zc706/system_constr.xdc
View File

@ -31,3 +31,5 @@ set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks
create_clock -name adc_clk -period 3.33 [get_ports adc_clk_in_p]
set_false_path -through [get_pins i_system_wrapper/system_i/ila_wfifo/wfifo_ctl/inst/fifo_rst_reg/C]

1
projects/ad9265_fmc/zc706/system_project.tcl
View File

@ -1,6 +1,7 @@
# load script
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set project_name ad9265_fmc_zc706

211
projects/ad9265_fmc/zc706/system_top.v
View File

@ -40,28 +40,28 @@
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
@ -88,29 +88,29 @@ module system_top (
spi_sdio
);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
@ -140,22 +140,32 @@ inout spi_sdio;
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire [15:0] ps_intrs;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
// instantiations
assign spi_csn_adc = spi0_csn[0];
assign spi_csn_clk = spi0_csn[1];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
ad_iobuf #(.DATA_WIDTH(15)) iobuf_gpio_bd (
.di (gpio_o),
.do (gpio_i),
.dt (gpio_t),
.dio (gpio_bd));
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9265_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
@ -165,30 +175,30 @@ ad9265_spi i_spi (
);
system_wrapper i_system_wrapper (
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ddr_addr(ddr_addr),
.ddr_ba(ddr_ba),
.ddr_cas_n(ddr_cas_n),
.ddr_ck_n(ddr_ck_n),
.ddr_ck_p(ddr_ck_p),
.ddr_cke(ddr_cke),
.ddr_cs_n(ddr_cs_n),
.ddr_dm(ddr_dm),
.ddr_dq(ddr_dq),
.ddr_dqs_n(ddr_dqs_n),
.ddr_dqs_p(ddr_dqs_p),
.ddr_odt(ddr_odt),
.ddr_ras_n(ddr_ras_n),
.ddr_reset_n(ddr_reset_n),
.ddr_we_n(ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
@ -196,22 +206,19 @@ system_wrapper i_system_wrapper (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9265_spi (ps_intrs[2]),
.ad9265_dma_irq (ps_intrs[13]),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.spdif (spdif),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
@ -219,14 +226,24 @@ system_wrapper i_system_wrapper (
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn0(spi_csn[0]),
.spi_csn1(spi_csn[1]),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule