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ad_tdd_control: Add an on/off switch to the receive datapath 

For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
main
Istvan Csomortani 2016-07-28 13:29:09 +03:00
parent 7988d2c7a2
commit 58b220ba81
3 changed files with 146 additions and 20 deletions
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27
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -192,6 +192,8 @@ module axi_ad9361_tdd (
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_rx_dp_on_1_s;
wire [23:0] tdd_rx_dp_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
@ -202,6 +204,8 @@ module axi_ad9361_tdd (
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_rx_dp_on_2_s;
wire [23:0] tdd_rx_dp_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
@ -209,6 +213,7 @@ module axi_ad9361_tdd (
wire [23:0] tdd_counter_status;
wire tdd_rx_dp_en_s;
wire tdd_tx_dp_en_s;
assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
@ -237,10 +242,10 @@ module axi_ad9361_tdd (
always @(posedge clk) begin
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_rf_en;
tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_rf_en;
tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_rf_en;
tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_rf_en;
tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_dp_en_s;
tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_dp_en_s;
tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_dp_en_s;
tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_dp_en_s;
end else begin
tdd_rx_valid_i0 <= rx_valid_i0;
tdd_rx_valid_q0 <= rx_valid_q0;
@ -249,7 +254,6 @@ module axi_ad9361_tdd (
end
end
// instantiations
up_tdd_cntrl i_up_tdd_cntrl(
@ -271,6 +275,8 @@ module axi_ad9361_tdd (
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
@ -281,6 +287,8 @@ module axi_ad9361_tdd (
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
@ -301,8 +309,8 @@ module axi_ad9361_tdd (
// for the axi_ad9361 core
ad_tdd_control #(
.TX_DATA_PATH_DELAY(14),
.CONTROL_PATH_DELAY(3))
.TX_DATA_PATH_DELAY(),
.CONTROL_PATH_DELAY())
i_tdd_control(
.clk(clk),
.rst(rst),
@ -320,6 +328,8 @@ module axi_ad9361_tdd (
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
@ -330,10 +340,13 @@ module axi_ad9361_tdd (
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_rx_dp_en(tdd_rx_dp_en_s),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en),
.tdd_tx_vco_en(tdd_tx_vco_en),

81
library/common/ad_tdd_control.v
View File

@ -61,6 +61,8 @@ module ad_tdd_control(
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_rx_dp_on_1,
tdd_rx_dp_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
@ -71,6 +73,8 @@ module ad_tdd_control(
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_rx_dp_on_2,
tdd_rx_dp_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
@ -80,6 +84,7 @@ module ad_tdd_control(
// TDD control signals
tdd_tx_dp_en,
tdd_rx_dp_en,
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
@ -113,6 +118,8 @@ module ad_tdd_control(
input [23:0] tdd_vco_tx_off_1;
input [23:0] tdd_rx_on_1;
input [23:0] tdd_rx_off_1;
input [23:0] tdd_rx_dp_on_1;
input [23:0] tdd_rx_dp_off_1;
input [23:0] tdd_tx_on_1;
input [23:0] tdd_tx_off_1;
input [23:0] tdd_tx_dp_on_1;
@ -123,6 +130,8 @@ module ad_tdd_control(
input [23:0] tdd_vco_tx_off_2;
input [23:0] tdd_rx_on_2;
input [23:0] tdd_rx_off_2;
input [23:0] tdd_rx_dp_on_2;
input [23:0] tdd_rx_dp_off_2;
input [23:0] tdd_tx_on_2;
input [23:0] tdd_tx_off_2;
input [23:0] tdd_tx_dp_on_2;
@ -130,17 +139,19 @@ module ad_tdd_control(
input tdd_sync;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
output tdd_tx_vco_en; // power up RF Rx
output tdd_rx_rf_en; // power up RF Tx
output tdd_tx_rf_en; // enable Tx datapath
output tdd_rx_vco_en; // initiate vco tx2rx switch
output tdd_tx_vco_en; // initiate vco rx2tx switch
output tdd_rx_rf_en; // power up RF Rx
output tdd_tx_rf_en; // power up RF Tx
output tdd_tx_dp_en; // enable Tx datapath
output tdd_rx_dp_en; // enable Rx datapath
output [23:0] tdd_counter_status;
// tdd control related
reg tdd_tx_dp_en = 1'b0;
reg tdd_rx_dp_en = 1'b0;
reg tdd_rx_vco_en = 1'b0;
reg tdd_tx_vco_en = 1'b0;
reg tdd_rx_rf_en = 1'b0;
@ -160,6 +171,8 @@ module ad_tdd_control(
reg counter_at_tdd_vco_tx_off_1 = 1'b0;
reg counter_at_tdd_rx_on_1 = 1'b0;
reg counter_at_tdd_rx_off_1 = 1'b0;
reg counter_at_tdd_rx_dp_on_1 = 1'b0;
reg counter_at_tdd_rx_dp_off_1 = 1'b0;
reg counter_at_tdd_tx_on_1 = 1'b0;
reg counter_at_tdd_tx_off_1 = 1'b0;
reg counter_at_tdd_tx_dp_on_1 = 1'b0;
@ -170,6 +183,8 @@ module ad_tdd_control(
reg counter_at_tdd_vco_tx_off_2 = 1'b0;
reg counter_at_tdd_rx_on_2 = 1'b0;
reg counter_at_tdd_rx_off_2 = 1'b0;
reg counter_at_tdd_rx_dp_on_2 = 1'b0;
reg counter_at_tdd_rx_dp_off_2 = 1'b0;
reg counter_at_tdd_tx_on_2 = 1'b0;
reg counter_at_tdd_tx_off_2 = 1'b0;
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
@ -499,6 +514,48 @@ module ad_tdd_control(
end
end
// start/stop rx data path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_dp_on_1 <= 1'b0;
end else if(tdd_counter == tdd_rx_dp_on_1) begin
counter_at_tdd_rx_dp_on_1 <= 1'b1;
end else begin
counter_at_tdd_rx_dp_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_dp_on_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_on_2)) begin
counter_at_tdd_rx_dp_on_2 <= 1'b1;
end else begin
counter_at_tdd_rx_dp_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_dp_off_1 <= 1'b0;
end else if(tdd_counter == tdd_rx_dp_off_1) begin
counter_at_tdd_rx_dp_off_1 <= 1'b1;
end else begin
counter_at_tdd_rx_dp_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_dp_off_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_off_2)) begin
counter_at_tdd_rx_dp_off_2 <= 1'b1;
end else begin
counter_at_tdd_rx_dp_off_2 <= 1'b0;
end
end
// control-path delay compensation
ad_addsub #(
@ -817,5 +874,19 @@ module ad_tdd_control(
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_rx_dp_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin
tdd_rx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin
tdd_rx_dp_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_dp_en <= tdd_rx_only;
end else begin
tdd_rx_dp_en <= tdd_rx_dp_en;
end
end
endmodule

58
library/common/up_tdd_cntrl.v
View File

@ -61,6 +61,8 @@ module up_tdd_cntrl (
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_rx_dp_on_1,
tdd_rx_dp_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
@ -71,6 +73,8 @@ module up_tdd_cntrl (
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_rx_dp_on_2,
tdd_rx_dp_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
@ -115,6 +119,8 @@ module up_tdd_cntrl (
output [23:0] tdd_vco_tx_off_1;
output [23:0] tdd_rx_on_1;
output [23:0] tdd_rx_off_1;
output [23:0] tdd_rx_dp_on_1;
output [23:0] tdd_rx_dp_off_1;
output [23:0] tdd_tx_on_1;
output [23:0] tdd_tx_off_1;
output [23:0] tdd_tx_dp_on_1;
@ -125,6 +131,8 @@ module up_tdd_cntrl (
output [23:0] tdd_vco_tx_off_2;
output [23:0] tdd_rx_on_2;
output [23:0] tdd_rx_off_2;
output [23:0] tdd_rx_dp_on_2;
output [23:0] tdd_rx_dp_off_2;
output [23:0] tdd_tx_on_2;
output [23:0] tdd_tx_off_2;
output [23:0] tdd_tx_dp_on_2;
@ -170,6 +178,8 @@ module up_tdd_cntrl (
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_rx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
@ -180,6 +190,8 @@ module up_tdd_cntrl (
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_rx_dp_off_2 = 24'h0;
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
@ -219,18 +231,24 @@ module up_tdd_cntrl (
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
up_tdd_rx_dp_on_1 <= 24'h0;
up_tdd_rx_dp_off_1 <= 24'h0;
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
up_tdd_tx_dp_off_1 <= 24'h0;
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
up_tdd_rx_dp_on_2 <= 24'h0;
up_tdd_rx_dp_off_2 <= 24'h0;
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
up_tdd_tx_dp_off_2 <= 24'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@ -281,9 +299,15 @@ module up_tdd_cntrl (
up_tdd_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
up_tdd_rx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_tdd_rx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
@ -308,14 +332,20 @@ module up_tdd_cntrl (
up_tdd_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_tx_off_2 <= up_wdata[23:0];
up_tdd_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
up_tdd_rx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
end
end
@ -351,8 +381,10 @@ module up_tdd_cntrl (
8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1};
8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
@ -361,8 +393,10 @@ module up_tdd_cntrl (
8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2};
8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
default: up_rdata <= 32'h0;
endcase
end
@ -396,7 +430,7 @@ module up_tdd_cntrl (
tdd_terminal_type
}));
up_xfer_cntrl #(.DATA_WIDTH(528)) i_xfer_tdd_counter_values (
up_xfer_cntrl #(.DATA_WIDTH(624)) i_xfer_tdd_counter_values (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
@ -409,6 +443,8 @@ module up_tdd_cntrl (
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
up_tdd_rx_dp_on_1,
up_tdd_rx_dp_off_1,
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
@ -419,6 +455,8 @@ module up_tdd_cntrl (
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
up_tdd_rx_dp_on_2,
up_tdd_rx_dp_off_2,
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
@ -435,6 +473,8 @@ module up_tdd_cntrl (
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_rx_dp_on_1,
tdd_rx_dp_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
@ -445,6 +485,8 @@ module up_tdd_cntrl (
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_rx_dp_on_2,
tdd_rx_dp_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));