diff --git a/docs/FMC_eval_board_template.xlsx b/docs/FMC_eval_board_template.xlsx deleted file mode 100755 index 33ef17060..000000000 Binary files a/docs/FMC_eval_board_template.xlsx and /dev/null differ diff --git a/docs/extensions/adi_links.py b/docs/extensions/adi_links.py index 6615e7280..1f318b21c 100644 --- a/docs/extensions/adi_links.py +++ b/docs/extensions/adi_links.py @@ -10,6 +10,18 @@ dft_url_part = 'https://www.analog.com/products' dft_url_xilinx = 'https://www.xilinx.com' dft_url_intel = 'https://www.intel.com' +git_repos = [ + # url_path name + ['hdl', "HDL"], + ['testbenches', "Testbenches"], + ['linux', "Linux"], + ['no-os', "no-OS"], + ['libiio', "libiio"], + ['scopy', "Scopy"], + ['iio-oscilloscope', "IIO Oscilloscope"] +] +vendors = ['xilinx', 'intel'] + def get_url_config(name, inliner): app = inliner.document.settings.env.app return getattr(app.config, "url_"+name) @@ -100,12 +112,11 @@ def setup(app): app.add_role("datasheet", datasheet()) app.add_role("dokuwiki", dokuwiki()) app.add_role("ez", ez()) - app.add_role("git-hdl", git('hdl', "HDL")) - app.add_role("git-testbenches", git('testbenches', "Testbenches")) - app.add_role("git-linux", git('linux', "Linux")) app.add_role("part", part()) - app.add_role("xilinx", vendor('xilinx')) - app.add_role("intel", vendor('intel')) + for name in vendors: + app.add_role(name, vendor(name)) + for path, name in git_repos: + app.add_role("git-"+path, git(path, name)) app.add_config_value('url_datasheet', dft_url_datasheet, 'env') app.add_config_value('url_dokuwiki', dft_url_dokuwiki, 'env') diff --git a/docs/index.rst b/docs/index.rst index 30d5f99e1..31126fb53 100755 --- a/docs/index.rst +++ b/docs/index.rst @@ -3,6 +3,12 @@ HDL Reference Designs =============================================================================== +.. toctree:: + :caption: User guide + :hidden: + + user_guide/index + .. toctree:: :caption: Libraries :hidden: @@ -10,12 +16,6 @@ HDL Reference Designs library/spi_engine/index library/axi_dmac/index -.. toctree:: - :caption: Contributing - :hidden: - - contributing/guidelines - .. attention:: Work-in-progress, not all content available at the diff --git a/docs/contributing/guidelines.rst b/docs/user_guide/docs_guidelines.rst similarity index 93% rename from docs/contributing/guidelines.rst rename to docs/user_guide/docs_guidelines.rst index e7c142bb5..9b4bdf656 100644 --- a/docs/contributing/guidelines.rst +++ b/docs/user_guide/docs_guidelines.rst @@ -1,4 +1,6 @@ -Guidelines +.. _docs_guidelines: + +Documentation guidelines ================================================================================ A brief set-of-rules for the documentation. @@ -56,8 +58,12 @@ while respecting word-breaks: cat imported.txt | fold -sw 80 > imported.rst -Or use the pandoc command provided in the next topic, since it will also fold -at column 80. +Or use :code:`pandoc`: + +.. code:: bash + + pandoc imported.txt -f dokuwiki -t rst --columns=80 -s -o imported.rst + Tables -------------------------------------------------------------------------------- @@ -69,15 +75,11 @@ and imported (using the file option), because they are faster to create, easier to maintain and the 80 column-width rule can be respected with list-tables. -Converting dokuwiki tables to list-table would be very time consuming, however -there is a pandoc `list-table filter `_, -see :ref:`installing_pandoc` for install instructions. - You can use the following command: .. code:: bash - pandoc -f dokuwiki -t rst --columns=80 -s -o --list-tables + pandoc imported.txt -f dokuwiki -t rst --columns=80 -s -o imported.rst --list-tables The :code:`list-tables` parameter requires *pandoc-types* >= 1.23, if it is not an option, you shall remove it and export in the *grid* table format. @@ -178,6 +180,11 @@ consider requesting or creating one. links, but without the undescore in the end. +Color role +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To print text in red or green, use :code:`:red:\`text\`` and :code:`:green:\`text\``. + Git role ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -385,25 +392,3 @@ Global options for HDL directives Use the `hide_collapsible_content` to set the default state of the collapsibles, if you set to False, they be expanded by default. - -Installing pandoc --------------------------------------------------------------------------------- - -The recommended way to import dokuwiki to reST is to use -`pandoc `_. - -To ensure a up-to date version, considering installing from source: - -.. code:: - - curl --proto '=https' --tlsv1.2 -sSf https://get-ghcup.haskell.org | sh - cabal v2-update - cabal v2-install pandoc-cli - -If custom pandoc haskell filters are needed, also install as a library: - -.. code:: - - cabal v2-install --lib pandoc-types --package-env . - -The tested *pandoc* version is 3.1.5, with *pandoc-types* version 2.13. diff --git a/docs/user_guide/index.rst b/docs/user_guide/index.rst new file mode 100644 index 000000000..eb36ea1f6 --- /dev/null +++ b/docs/user_guide/index.rst @@ -0,0 +1,14 @@ +.. _user_guide: + +User Guide +=============================================================================== + +.. toctree:: + :hidden: + + Porting reference designs + Documentation guidelines + +#. :ref:`porting_project`: How to port a project to a non-supported carrier +#. :ref:`docs_guidelines`: Documentation guidelines + diff --git a/docs/user_guide/porting_project.rst b/docs/user_guide/porting_project.rst new file mode 100644 index 000000000..fcd48a21f --- /dev/null +++ b/docs/user_guide/porting_project.rst @@ -0,0 +1,307 @@ +.. _porting_project: + +Porting ADI's HDL reference designs +=============================================================================== + +In general, a given reference design for an FMC board is deployed to just a few +carriers, although several :git-hdl:`FPGA boards ` +are supported in ADI's HDL repository. The simple reason behind this practice is +that it would create a tremendous maintenance workload, that would require a lot +of human resources, and would increase the required time for testing. The +general rule of thumb is to support a given project with a fairly popular +carrier (e.g. ZC706 or A10SoC), which is powerful enough to showcase the board +features and maximum performance. + +All the HDL projects were designed to maximize source code reuse, minimize +maintainability and simplify portability. The result of these design goals is +that porting a given project to another carrier is fairly simple if the user +respects a couple of guidelines. + +The main scope of this wiki page is to discuss these guidelines and provide +simple indications for users who wants to port a project to a non-supported +carrier. + +Quick Compatibility Check +------------------------------------------------------------------------------- + +.. note:: + + All ADI's FPGA Mezzanine Cards (FMC) are designed to respect all the + specifications and requirements defined in the ANSI/VITA 57.1 FPGA Mezzanine + Card Standard (if not otherwise stated on board's wiki page). If the new FPGA + carrier is fully compliant with this standard, there will be no obstacles + preventing the user to port the project to the required carrier card. + +There are two types of FMC connectors: LPC (Low Pin Count) and HPC (High Pin +Count). In general, an FMC board is using the FMC connector type that has enough +pins for the required interfaces between the I/O devices and FPGA. A carrier +with an FMC HPC connector can host FMC boards with an LPC or HPC connector, but +a carrier with an FMC LPC can host a board just with an FMC LPC connector. + +.. tip:: + + First, always check out the already available :git-hdl:`base designs `. + If your board is present among our supported base designs, you do not need to + verify the following things and you can jump to the Project creation + section. + +The most important things to check before porting are related to the ANSI/VITA +57.1 standard (the list is not necessarily exhaustive): + +- Power and ground lines - 3P3V/3P3VAUX/12P0V/GND +- VADJ - adjustable voltage level power from the carrier, each board has a + specific requirement for VADJ +- Dedicated pins for clock signals - all the clock dedicated pins should be + connected to a clock capable pin of the FPGA (I/O pin which is capable to + receive and/or transmit a clock signal) +- Dedicated pins for transceiver lines (DPx_[M2C|C2M]_[P|N]) + +.. attention:: + + To check all the requirements, please refer to the ANSI/VITA 57.1 standard. + The above few hints do not cover all the FMC standards and you + may miss something that can prevent the porting of the project. + + +.. tip:: + + Make sure that you have reviewed all the documentation and design files in + order to know the electrical specifications and/or requirements of the + FMC board. If you're not sure, ask! + +Base design files +------------------------------------------------------------------------------- + +At :ref:`architecture` it is described a generic base design and possible +components of it. The user should look at it as a suggestion only. + +.. tip:: + + In :git-hdl:`/projects/common `/ + you can find templates for the *system_top.v*, *Makefile*, etc. to help you + when creating a new project. + +Example with a Xilinx board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +In this section, we are presenting all the necessary steps to create a base +design for the Xilinx ZCU102 development board. + +First, you need to create a new directory in *~/projects/common* with the name +of the carrier. + +.. code:: bash + + cd projects/common + mkdir zcu102 + +The **zcu102** directory must contain the following files: + +- **zcu102_system_bd.tcl** - This script describes the base block design +- **zcu102_system_constr.xdc** - I/O constraint file for the base design. It + will contain I/O definitions for GPIO, switches, LEDs or other peripherals of + the board +- MIG configuration file (if needed) - This file can be borrowed for the golden + reference design of the board +- Other constraints files if needed + +You should define the board and its device in the project flow script +:git-hdl:`projects/scripts/adi_project_xilinx.tcl` +by adding the following lines to the beginning of the **adi_project_create** +process: + +.. code:: tcl + + if [regexp "_zcu102$" $project_name] { + set p_device "xczu9eg-ffvb1156-1-i-es1" + set p_board "xilinx.com:zcu102:part0:1.2" + set sys_zynq 2 + } + +.. tip:: + + The valid board parts and parts can be retrieved by running the + following commands in Tcl console: **get_parts** and **get_board_parts**. Run + the commands like **join [get_parts] \\n**, so each part name will be listed on + a separate line. + +The **sys_zynq** constant variable should be set in the following way: + +- 0 - 7 Series FPGA (e.g. Kintex7, Virtex7) +- 1 - Zynq7000 SoC +- 2 - Zynq Ultrascale+ SoC + +Example with an Intel board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To create a new base design for a given Intel FPGA carrier board, the following +steps should be taken (the A10SoC carrier was used as an example). + +The following files should be created or copied into the directory: + +- **a10soc_system_assign.tcl** - global and I/O assignments of the base design +- **a10soc_system_qsys.tcl** - the QSYS base design + +You should define the board and its device in the flow script +:git-hdl:`projects/scripts/adi_project_intel.tcl`, +by adding the following lines to the beginning of the **adi_project_altera** +process: + +.. code:: tcl + + if [regexp "_a10soc$" $project_name] { + set family "Arria 10" + set device 10AS066N3F40E2SG + set system_qip_file system_bd/system_bd.qip + } + +Project files +------------------------------------------------------------------------------- + +Project files for Xilinx boards +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To follow the project framework as much as possible, the easiest way is to copy +all the projects files from an already existing project and modifying those +files to support the new carrier. A project for a Xilinx FPGA board should +contain the following files: + +- **system_project.tcl** - This script is creating the actual Vivado project + and runs the synthesis/implementation of the design. The name of the carrier + from inside the file, must be updated. + +- **system_bd.tcl** - In this file is sourced the *base* design's Tcl script + and the *board* design's Tcl script. Again, the name of the carrier must be + updated. + +- **system_constr.xdc** - Constraint file of the board design. Here are defined + the FMC I/O pins and board specific clock signals. All the I/O definitions + must be updated, with the new pin names. + +- **system_top.v** - Top wrapper file, in which the system_wrapper.v module is + instantiated, and a few I/O macros are defined. The I/O port of this Verilog + module will be connected to actual I/O pads of the FPGA. The simplest way to + update the *system_top* is to let the synthesis fail and the tool will tell + you which ports are missing or which ports are redundant. The first thing to + do after the failure is to verify the instantiation of the system_wrapper.v. + This file is a tool generated file and can be found at + *.srcs/sources_1/bd/system/hdl/system_wrapper.v*. Fixing the + instantiation of the wrapper module in most cases eliminates all the errors. + If you get errors that you cannot fix, ask for support. + +- **Makefile** - This is an auto-generated file, but after updating the carrier + name, should work with the new project without an issue. + +Project files for Intel boards +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To follow the project framework as much as possible the easiest way is to copy +all the projects file from an already existing project and modifying those files +to support the new carrier. A project for an Intel FPGA board should contain the +following files: + +- **system_project.tcl** - This script is creating the actual Quartus project + and runs the synthesis/implementation of the design. It also contains the I/O + definitions for the interfaces between the FMC board and FPGA. The carrier + name and all the I/O pin names inside the file, must be updated. + +- **system_qsys.tcl** - In this file is sourced the *base* design's Tcl script + and the *board* design's Tcl script. Again, the name of the carrier must be + updated. + +- **system_constr.sdc** - Contains clock definitions and other path constraints + +- **system_top.v** - Top wrapper file of the project. The I/O ports of this + Verilog module will be actual I/O pads of the FPGA. You must make sure that + the base design's I/Os are updated (delete nonexistent I/Os or add new ones). + The simplest way to update the *system_top* is to let the synthesis fail and + the tool will you tell which ports are missing or which ports are redundant. + +- **Makefile** - This is an auto-generated file, but after updating the carrier + name, it should work with the new project without an issue. + +Tips +------------------------------------------------------------------------------- + +Generating the FMC I/O constraints +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The easiest way of writing the constraints for FMC I/O pins is making use of the +script :git-hdl:`projects/scripts/adi_fmc_constr_generator.tcl`. + +Required setup: + +- Carrier common FMC connections file + (:git-hdl:`projects/common `//_.txt) +- Project common FMC connections file + (:git-hdl:`projects`//common/_fmc.txt) + +.. tip:: + + In cases where these files don't already exist, you can make your own + by following some existing ones as an example. + For project common files, you can easily make them following :ref:`creating_fmc`. + +Calling the script: + +To use this script you can source it in any tcl shell or simply call the +adi_fmc_constr_generator.tcl with argument(s) . But before sourcing or +calling it, your current directory needs to be +:git-hdl:`projects`// + +For example: + +- :code:`tclsh ../../scripts/adi_fmc_constr_generator.tcl fmc0` + (the project uses only one FMC port at a time) +- :code:`tclsh ../../scripts/adi_fmc_constr_generator.tcl fmc0 fmc1` + (the project uses two FMC ports at a time) + +If sourced without argument(s) then you can simply call gen_fmc_constr +. + +For example: + +- :code:`gen_fmc_constr fmc0` (the project uses only one FMC port at a time) +- :code:`gen_fmc_constr fmc0 fmc1` (the project uses two FMC ports at a time) + +.. note:: + + The fmc port name can be deduced from the common carrier file name + (:git-hdl:`projects/common `//_.txt). + +The generated file will appear in the current directory as **fmc_constr.xdc** +(Xilinx board) or **fmc_constr.tcl** (Intel board). If ran from an open Vivado +project, the generated file will be automatically added to the project. + +.. _creating_fmc: + +Creating carrier common FMC connections +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To create a carrier common FMC connections file: + +#. Open the space divided .txt file corresponding to the desired connector type, + either with a text editor or importing in a spreadsheet editor + (with Excel, export as .prn). + :git-hdl:`docs/user_guide/sources/fmc.txt`, + :git-hdl:`docs/user_guide/sources/fmc_hpc.txt`, + :git-hdl:`docs/user_guide/sources/fmc+.txt`. +#. Fill the table by replacing the **#**'s where it's needed. +#. Save as .txt inside :git-hdl:`projects`//common/. +#. Clean up the file by removing the lines containing **#** for system_top_name. +#. Rearrange the lines following one of the existing examples. +#. To generate empty lines, leave an empty line in the .txt file. + To generate comments, the line should start with **#** sign. +#. Run the script as :code:`tclsh /path/to/script {fmc_conn}` + (e.g. :code:`tclsh ../../scripts/adi_fmc_constr_generator.tcl fmc0`). + + * Current directory needs to be hdl/projects//. + * If used from an open project, the generated file would be added to the project; + otherwise it will appear in the current directory. + * If the carrier has only one FMC port, the script can be called without parameters. + * If the carrier has more FMC ports, the script should be called with: + + * One parameter indicating the FMC port: fmc_lpc/hpc, fmc0/1, fmcp0/1 + (see projects/common//\*.txt). + * Two parameters indicating both FMC ports in the desired order for projects + that use both FMC connectors. diff --git a/docs/user_guide/sources/fmc+.txt b/docs/user_guide/sources/fmc+.txt new file mode 100644 index 000000000..8cb0abba3 --- /dev/null +++ b/docs/user_guide/sources/fmc+.txt @@ -0,0 +1,312 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination +A2 DP1_M2C_P # # # # +A3 DP1_M2C_N # # # # +A6 DP2_M2C_P # # # # +A7 DP2_M2C_N # # # # +A10 DP3_M2C_P # # # # +A11 DP3_M2C_N # # # # +A14 DP4_M2C_P # # # # +A15 DP4_M2C_N # # # # +A18 DP5_M2C_P # # # # +A19 DP5_M2C_N # # # # +A22 DP1_C2M_P # # # # +A23 DP1_C2M_N # # # # +A26 DP2_C2M_P # # # # +A27 DP2_C2M_N # # # # +A30 DP3_C2M_P # # # # +A31 DP3_C2M_N # # # # +A34 DP4_C2M_P # # # # +A35 DP4_C2M_N # # # # +A38 DP5_C2M_P # # # # +A39 DP5_C2M_N # # # # +B1 CLK_DIR # # # # +B4 DP9_M2C_P # # # # +B5 DP9_M2C_N # # # # +B8 DP8_M2C_P # # # # +B9 DP8_M2C_N # # # # +B12 DP7_M2C_P # # # # +B13 DP7_M2C_N # # # # +B16 DP6_M2C_P # # # # +B17 DP6_M2C_N # # # # +B20 GBTCLK1_M2C_P # # # # +B21 GBTCLK1_M2C_N # # # # +B24 DP9_C2M_P # # # # +B25 DP9_C2M_N # # # # +B28 DP8_C2M_P # # # # +B29 DP8_C2M_N # # # # +B32 DP7_C2M_P # # # # +B33 DP7_C2M_N # # # # +B36 DP6_C2M_P # # # # +B37 DP6_C2M_N # # # # +B40 RES0 # # # # +C2 DP0_C2M_P # # # # +C3 DP0_C2M_N # # # # +C6 DP0_M2C_P # # # # +C7 DP0_M2C_N # # # # +C10 LA06_P # # # # +C11 LA06_N # # # # +C14 LA10_P # # # # +C15 LA10_N # # # # +C18 LA14_P # # # # +C19 LA14_N # # # # +C22 LA18_P_CC # # # # +C23 LA18_N_CC # # # # +C26 LA27_P # # # # +C27 LA27_N # # # # +C30 SCL # # # # +C31 SDA # # # # +C34 GA0 # # # # +D1 PG_C2M # # # # +D4 GBTCLK0_M2C_P # # # # +D5 GBTCLK0_M2C_N # # # # +D8 LA01_P_CC # # # # +D9 LA01_N_CC # # # # +D11 LA05_P # # # # +D12 LA05_N # # # # +D14 LA09_P # # # # +D15 LA09_N # # # # +D17 LA13_P # # # # +D18 LA13_N # # # # +D20 LA17_P_CC # # # # +D21 LA17_N_CC # # # # +D23 LA23_P # # # # +D24 LA23_N # # # # +D26 LA26_P # # # # +D27 LA26_N # # # # +D29 TCK # # # # +D30 TDI # # # # +D31 TDO # # # # +D32 3P3VAUX # # # # +D33 TMS # # # # +D34 TRST_L # # # # +D35 GA1 # # # # +E2 HA01_P_CC # # # # +E3 HA01_N_CC # # # # +E6 HA05_P # # # # +E7 HA05_N # # # # +E9 HA09_P # # # # +E10 HA09_N # # # # +E12 HA13_P # # # # +E13 HA13_N # # # # +E15 HA16_P # # # # +E16 HA16_N # # # # +E18 HA20_P # # # # +E19 HA20_N # # # # +E21 HB03_P # # # # +E22 HB03_N # # # # +E24 HB05_P # # # # +E25 HB05_N # # # # +E27 HB09_P # # # # +E28 HB09_N # # # # +E30 HB13_P # # # # +E31 HB13_N # # # # +E33 HB19_P # # # # +E34 HB19_N # # # # +E36 HB21_P # # # # +E37 HB21_N # # # # +E39 VADJ # # # # +F1 PG_M2C # # # # +F4 HA00_P_CC # # # # +F5 HA00_N_CC # # # # +F7 HA04_P # # # # +F8 HA04_N # # # # +F10 HA08_P # # # # +F11 HA08_N # # # # +F13 HA12_P # # # # +F14 HA12_N # # # # +F16 HA15_P # # # # +F17 HA15_N # # # # +F19 HA19_P # # # # +F20 HA19_N # # # # +F22 HB02_P # # # # +F23 HB02_N # # # # +F25 HB04_P # # # # +F26 HB04_N # # # # +F28 HB08_P # # # # +F29 HB08_N # # # # +F31 HB12_P # # # # +F32 HB12_N # # # # +F34 HB16_P # # # # +F35 HB16_N # # # # +F37 HB20_P # # # # +F38 HB20_N # # # # +F40 VADJ # # # # +G2 CLK1_M2C_P # # # # +G3 CLK1_M2C_N # # # # +G6 LA00_P_CC # # # # +G7 LA00_N_CC # # # # +G9 LA03_P # # # # +G10 LA03_N # # # # +G12 LA08_P # # # # +G13 LA08_N # # # # +G15 LA12_P # # # # +G16 LA12_N # # # # +G18 LA16_P # # # # +G19 LA16_N # # # # +G21 LA20_P # # # # +G22 LA20_N # # # # +G24 LA22_P # # # # +G25 LA22_N # # # # +G27 LA25_P # # # # +G28 LA25_N # # # # +G30 LA29_P # # # # +G31 LA29_N # # # # +G33 LA31_P # # # # +G34 LA31_N # # # # +G36 LA33_P # # # # +G37 LA33_N # # # # +G39 VADJ # # # # +H1 VREF_A_M2C # # # # +H2 PRSNT_M2C_L # # # # +H4 CLK0_M2C_P # # # # +H5 CLK0_M2C_N # # # # +H7 LA02_P # # # # +H8 LA02_N # # # # +H10 LA04_P # # # # +H11 LA04_N # # # # +H13 LA07_P # # # # +H14 LA07_N # # # # +H16 LA11_P # # # # +H17 LA11_N # # # # +H19 LA15_P # # # # +H20 LA15_N # # # # +H22 LA19_P # # # # +H23 LA19_N # # # # +H25 LA21_P # # # # +H26 LA21_N # # # # +H28 LA24_P # # # # +H29 LA24_N # # # # +H31 LA28_P # # # # +H32 LA28_N # # # # +H34 LA30_P # # # # +H35 LA30_N # # # # +H37 LA32_P # # # # +H38 LA32_N # # # # +H40 VADJ # # # # +J2 CLK3_BIDIR_P # # # # +J3 CLK3_BIDIR_N # # # # +J6 HA03_P # # # # +J7 HA03_N # # # # +J9 HA07_P # # # # +J10 HA07_N # # # # +J12 HA11_P # # # # +J13 HA11_N # # # # +J15 HA14_P # # # # +J16 HA14_N # # # # +J18 HA18_P # # # # +J19 HA18_N # # # # +J21 HA22_P # # # # +J22 HA22_N # # # # +J24 HB01_P # # # # +J25 HB01_N # # # # +J27 HB07_P # # # # +J28 HB07_N # # # # +J30 HB11_P # # # # +J31 HB11_N # # # # +J33 HB15_P # # # # +J34 HB15_N # # # # +J36 HB18_P # # # # +J37 HB18_N # # # # +J39 VIO_B_M2C # # # # +K1 VREF_B_M2C # # # # +K4 CLK2_BIDIR_P # # # # +K5 CLK2_BIDIR_N # # # # +K7 HA02_P # # # # +K8 HA02_N # # # # +K10 HA06_P # # # # +K11 HA06_N # # # # +K13 HA10_P # # # # +K14 HA10_N # # # # +K16 HA17_P_CC # # # # +K17 HA17_N_CC # # # # +K19 HA21_P # # # # +K20 HA21_N # # # # +K22 HA23_P # # # # +K23 HA23_N # # # # +K25 HB00_P_CC # # # # +K26 HB00_N_CC # # # # +K28 HB06_P_CC # # # # +K29 HB06_N_CC # # # # +K31 HB10_P # # # # +K32 HB10_N # # # # +K34 HB14_P # # # # +K35 HB14_N # # # # +K37 HB17_P_CC # # # # +K38 HB17_N_CC # # # # +K40 VIO_B_M2C # # # # +L1 RES1 # # # # +L4 GBTCLK4_M2C_P # # # # +L5 GBTCLK4_M2C_N # # # # +L8 GBTCLK3_M2C_P # # # # +L9 GBTCLK3_M2C_N # # # # +L12 GBTCLK2_M2C_P # # # # +L13 GBTCLK2_M2C_N # # # # +L16 SYNC_C2M_P # # # # +L17 SYNC_C2M_N # # # # +L20 REFCLK_C2M_P # # # # +L21 REFCLK_C2M_N # # # # +L24 REFCLK_M2C_P # # # # +L25 REFCLK_M2C_N # # # # +L28 SYNC_M2C_P # # # # +L29 SYNC_M2C_N # # # # +L32 RES2 # # # # +L33 RES3 # # # # +M2 DP23_M2C_P # # # # +M3 DP23_M2C_N # # # # +M6 DP22_M2C_P # # # # +M7 DP22_M2C_N # # # # +M10 DP21_M2C_P # # # # +M11 DP21_M2C_N # # # # +M14 DP20_M2C_P # # # # +M15 DP20_M2C_N # # # # +M18 DP14_C2M_P # # # # +M19 DP14_C2M_N # # # # +M22 DP15_C2M_P # # # # +M23 DP15_C2M_N # # # # +M26 DP16_C2M_P # # # # +M27 DP16_C2M_N # # # # +M30 DP17_C2M_P # # # # +M31 DP17_C2M_N # # # # +M34 DP18_C2M_P # # # # +M35 DP18_C2M_N # # # # +M38 DP19_C2M_P # # # # +M39 DP19_C2M_N # # # # +Y2 DP23_C2M_P # # # # +Y3 DP23_C2M_N # # # # +Y6 DP21_C2M_P # # # # +Y7 DP21_C2M_N # # # # +Y10 DP10_M2C_P # # # # +Y11 DP10_M2C_N # # # # +Y14 DP12_M2C_P # # # # +Y15 DP12_M2C_N # # # # +Y18 DP14_M2C_P # # # # +Y19 DP14_M2C_N # # # # +Y22 DP15_M2C_P # # # # +Y23 DP15_M2C_N # # # # +Y26 DP11_C2M_P # # # # +Y27 DP11_C2M_N # # # # +Y30 DP13_C2M_P # # # # +Y31 DP13_C2M_N # # # # +Y34 DP17_M2C_P # # # # +Y35 DP17_M2C_N # # # # +Y38 DP19_M2C_P # # # # +Y39 DP19_M2C_N # # # # +Z1 HSPC_PRSNT_M2C_L# # # # +Z4 DP22_C2M_P # # # # +Z5 DP22_C2M_N # # # # +Z8 DP20_C2M_P # # # # +Z9 DP20_C2M_N # # # # +Z12 DP11_M2C_P # # # # +Z13 DP11_M2C_N # # # # +Z16 DP13_M2C_P # # # # +Z17 DP13_M2C_N # # # # +Z20 GBTCLK5_M2C_P # # # # +Z21 GBTCLK5_M2C_N # # # # +Z24 DP10_C2M_P # # # # +Z25 DP10_C2M_N # # # # +Z28 DP12_C2M_P # # # # +Z29 DP12_C2M_N # # # # +Z32 DP16_M2C_P # # # # +Z33 DP16_M2C_N # # # # +Z36 DP18_M2C_P # # # # +Z37 DP18_M2C_N # # # # diff --git a/docs/user_guide/sources/fmc.txt b/docs/user_guide/sources/fmc.txt new file mode 100644 index 000000000..e4df3a356 --- /dev/null +++ b/docs/user_guide/sources/fmc.txt @@ -0,0 +1,83 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination +C2 DP0_C2M_P # # # # +C3 DP0_C2M_N # # # # +C6 DP0_M2C_P # # # # +C7 DP0_M2C_N # # # # +C10 LA06_P # # # # +C11 LA06_N # # # # +C14 LA10_P # # # # +C15 LA10_N # # # # +C18 LA14_P # # # # +C19 LA14_N # # # # +C22 LA18_CC_P # # # # +C23 LA18_CC_N # # # # +C26 LA27_P # # # # +C27 LA27_N # # # # +C30 SCL # # # # +C31 SDA # # # # +D1 PG_C2M # # # # +D4 GBTCLK0_M2C_P # # # # +D5 GBTCLK0_M2C_N # # # # +D8 LA01_CC_P # # # # +D9 LA01_CC_N # # # # +D11 LA05_P # # # # +D12 LA05_N # # # # +D14 LA09_P # # # # +D15 LA09_N # # # # +D17 LA13_P # # # # +D18 LA13_N # # # # +D20 LA17_CC_P # # # # +D21 LA17_CC_N # # # # +D23 LA23_P # # # # +D24 LA23_N # # # # +D26 LA26_P # # # # +D27 LA26_N # # # # +G2 CLK1_M2C_P # # # # +G3 CLK1_M2C_N # # # # +G6 LA00_CC_P # # # # +G7 LA00_CC_N # # # # +G9 LA03_P # # # # +G10 LA03_N # # # # +G12 LA08_P # # # # +G13 LA08_N # # # # +G15 LA12_P # # # # +G16 LA12_N # # # # +G18 LA16_P # # # # +G19 LA16_N # # # # +G21 LA20_P # # # # +G22 LA20_N # # # # +G24 LA22_P # # # # +G25 LA22_N # # # # +G27 LA25_P # # # # +G28 LA25_N # # # # +G30 LA29_P # # # # +G31 LA29_N # # # # +G33 LA31_P # # # # +G34 LA31_N # # # # +G36 LA33_P # # # # +G37 LA33_N # # # # +H2 PRSNT_M2C_L # # # # +H4 CLK0_M2C_P # # # # +H5 CLK0_M2C_N # # # # +H7 LA02_P # # # # +H8 LA02_N # # # # +H10 LA04_P # # # # +H11 LA04_N # # # # +H13 LA07_P # # # # +H14 LA07_N # # # # +H16 LA11_P # # # # +H17 LA11_N # # # # +H19 LA15_P # # # # +H20 LA15_N # # # # +H22 LA19_P # # # # +H23 LA19_N # # # # +H25 LA21_P # # # # +H26 LA21_N # # # # +H28 LA24_P # # # # +H29 LA24_N # # # # +H31 LA28_P # # # # +H32 LA28_N # # # # +H34 LA30_P # # # # +H35 LA30_N # # # # +H37 LA32_P # # # # +H38 LA32_N # # # # diff --git a/docs/user_guide/sources/fmc_hpc.txt b/docs/user_guide/sources/fmc_hpc.txt new file mode 100644 index 000000000..121ade2de --- /dev/null +++ b/docs/user_guide/sources/fmc_hpc.txt @@ -0,0 +1,219 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination +A2 DP1_M2C_P # # # # +A3 DP1_M2C_N # # # # +A6 DP2_M2C_P # # # # +A7 DP2_M2C_N # # # # +A10 DP3_M2C_P # # # # +A11 DP3_M2C_N # # # # +A14 DP4_M2C_P # # # # +A15 DP4_M2C_N # # # # +A18 DP5_M2C_P # # # # +A19 DP5_M2C_N # # # # +A22 DP1_C2M_P # # # # +A23 DP1_C2M_N # # # # +A26 DP2_C2M_P # # # # +A27 DP2_C2M_N # # # # +A30 DP3_C2M_P # # # # +A31 DP3_C2M_N # # # # +A34 DP4_C2M_P # # # # +A35 DP4_C2M_N # # # # +A38 DP5_C2M_P # # # # +A39 DP5_C2M_N # # # # +B1 CLK_DIR # # # # +B4 DP9_M2C_P # # # # +B5 DP9_M2C_N # # # # +B8 DP8_M2C_P # # # # +B9 DP8_M2C_N # # # # +B12 DP7_M2C_P # # # # +B13 DP7_M2C_N # # # # +B16 DP6_M2C_P # # # # +B17 DP6_M2C_N # # # # +B20 GBTCLK1_M2C_P # # # # +B21 GBTCLK1_M2C_N # # # # +B24 DP9_C2M_P # # # # +B25 DP9_C2M_N # # # # +B28 DP8_C2M_P # # # # +B29 DP8_C2M_N # # # # +B32 DP7_C2M_P # # # # +B33 DP7_C2M_N # # # # +B36 DP6_C2M_P # # # # +B37 DP6_C2M_N # # # # +C2 DP0_C2M_P # # # # +C3 DP0_C2M_N # # # # +C6 DP0_M2C_P # # # # +C7 DP0_M2C_N # # # # +C10 LA06_P # # # # +C11 LA06_N # # # # +C14 LA10_P # # # # +C15 LA10_N # # # # +C18 LA14_P # # # # +C19 LA14_N # # # # +C22 LA18_CC_P # # # # +C23 LA18_CC_N # # # # +C26 LA27_P # # # # +C27 LA27_N # # # # +C30 SCL # # # # +C31 SDA # # # # +D1 PG_C2M # # # # +D4 GBTCLK0_M2C_P # # # # +D5 GBTCLK0_M2C_N # # # # +D8 LA01_CC_P # # # # +D9 LA01_CC_N # # # # +D11 LA05_P # # # # +D12 LA05_N # # # # +D14 LA09_P # # # # +D15 LA09_N # # # # +D17 LA13_P # # # # +D18 LA13_N # # # # +D20 LA17_CC_P # # # # +D21 LA17_CC_N # # # # +D23 LA23_P # # # # +D24 LA23_N # # # # +D26 LA26_P # # # # +D27 LA26_N # # # # +E2 HA01_CC_P # # # # +E3 HA01_CC_N # # # # +E6 HA05_P # # # # +E7 HA05_N # # # # +E9 HA09_P # # # # +E10 HA09_N # # # # +E12 HA13_P # # # # +E13 HA13_N # # # # +E15 HA16_P # # # # +E16 HA16_N # # # # +E18 HA20_P # # # # +E19 HA20_N # # # # +E21 HB03_P # # # # +E22 HB03_N # # # # +E24 HB05_P # # # # +E25 HB05_N # # # # +E27 HB09_P # # # # +E28 HB09_N # # # # +E30 HB13_P # # # # +E31 HB13_N # # # # +E33 HB19_P # # # # +E34 HB19_N # # # # +E36 HB21_P # # # # +E37 HB21_N # # # # +F1 PG_M2C # # # # +F4 HA00_CC_P # # # # +F5 HA00_CC_N # # # # +F7 HA04_P # # # # +F8 HA04_N # # # # +F10 HA08_P # # # # +F11 HA08_N # # # # +F13 HA12_P # # # # +F14 HA12_N # # # # +F16 HA15_P # # # # +F17 HA15_N # # # # +F19 HA19_P # # # # +F20 HA19_N # # # # +F22 HB02_P # # # # +F23 HB02_N # # # # +F25 HB04_P # # # # +F26 HB04_N # # # # +F28 HB08_P # # # # +F29 HB08_N # # # # +F31 HB12_P # # # # +F32 HB12_N # # # # +F34 HB16_P # # # # +F35 HB16_N # # # # +F37 HB20_P # # # # +F38 HB20_N # # # # +G2 CLK1_M2C_P # # # # +G3 CLK1_M2C_N # # # # +G6 LA00_CC_P # # # # +G7 LA00_CC_N # # # # +G9 LA03_P # # # # +G10 LA03_N # # # # +G12 LA08_P # # # # +G13 LA08_N # # # # +G15 LA12_P # # # # +G16 LA12_N # # # # +G18 LA16_P # # # # +G19 LA16_N # # # # +G21 LA20_P # # # # +G22 LA20_N # # # # +G24 LA22_P # # # # +G25 LA22_N # # # # +G27 LA25_P # # # # +G28 LA25_N # # # # +G30 LA29_P # # # # +G31 LA29_N # # # # +G33 LA31_P # # # # +G34 LA31_N # # # # +G36 LA33_P # # # # +G37 LA33_N # # # # +H2 PRSNT_M2C_L # # # # +H4 CLK0_M2C_P # # # # +H5 CLK0_M2C_N # # # # +H7 LA02_P # # # # +H8 LA02_N # # # # +H10 LA04_P # # # # +H11 LA04_N # # # # +H13 LA07_P # # # # +H14 LA07_N # # # # +H16 LA11_P # # # # +H17 LA11_N # # # # +H19 LA15_P # # # # +H20 LA15_N # # # # +H22 LA19_P # # # # +H23 LA19_N # # # # +H25 LA21_P # # # # +H26 LA21_N # # # # +H28 LA24_P # # # # +H29 LA24_N # # # # +H31 LA28_P # # # # +H32 LA28_N # # # # +H34 LA30_P # # # # +H35 LA30_N # # # # +H37 LA32_P # # # # +H38 LA32_N # # # # +J2 CLK3_IO_P # # # # +J3 CLK3_IO_N # # # # +J6 HA03_P # # # # +J7 HA03_N # # # # +J9 HA07_P # # # # +J10 HA07_N # # # # +J12 HA11_P # # # # +J13 HA11_N # # # # +J15 HA14_P # # # # +J16 HA14_N # # # # +J18 HA18_P # # # # +J19 HA18_N # # # # +J21 HA22_P # # # # +J22 HA22_N # # # # +J24 HB01_P # # # # +J25 HB01_N # # # # +J27 HB07_P # # # # +J28 HB07_N # # # # +J30 HB11_P # # # # +J31 HB11_N # # # # +J33 HB15_P # # # # +J34 HB15_N # # # # +J36 HB18_P # # # # +J37 HB18_N # # # # +K4 CLK2_IO_P # # # # +K5 CLK2_IO_N # # # # +K7 HA02_P # # # # +K8 HA02_N # # # # +K10 HA06_P # # # # +K11 HA06_N # # # # +K13 HA10_P # # # # +K14 HA10_N # # # # +K16 HA17_CC_P # # # # +K17 HA17_CC_N # # # # +K19 HA21_P # # # # +K20 HA21_N # # # # +K22 HA23_P # # # # +K23 HA23_N # # # # +K25 HB00_CC_P # # # # +K26 HB00_CC_N # # # # +K28 HB06_CC_P # # # # +K29 HB06_CC_N # # # # +K31 HB10_P # # # # +K32 HB10_N # # # # +K34 HB14_P # # # # +K35 HB14_N # # # # +K37 HB17_CC_P # # # # +K38 HB17_CC_N # # # #