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c5soc: working hdl version

main
Rejeesh Kutty 2014-07-24 20:50:10 -04:00
parent 6346017763
commit 59759a8ab3
5 changed files with 1938 additions and 313 deletions
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8
library/axi_ad9361/axi_ad9361_alt_lvds_tx.v
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@ -73,10 +73,10 @@ module axi_ad9361_alt_lvds_tx (
input tx_clk;
input clk;
input [ 3:0] tx_frame;
input [11:0] tx_data_0;
input [11:0] tx_data_1;
input [11:0] tx_data_2;
input [11:0] tx_data_3;
input [ 5:0] tx_data_0;
input [ 5:0] tx_data_1;
input [ 5:0] tx_data_2;
input [ 5:0] tx_data_3;
output tx_locked;
// internal registers

58
library/axi_ad9361/axi_ad9361_dev_if_alt.v
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@ -174,10 +174,10 @@ module axi_ad9361_dev_if (
reg tx_data_sel = 'd0;
reg [47:0] tx_data = 'd0;
reg [ 3:0] tx_frame = 'd0;
reg [11:0] tx_data_0 = 'd0;
reg [11:0] tx_data_1 = 'd0;
reg [11:0] tx_data_2 = 'd0;
reg [11:0] tx_data_3 = 'd0;
reg [ 5:0] tx_data_0 = 'd0;
reg [ 5:0] tx_data_1 = 'd0;
reg [ 5:0] tx_data_2 = 'd0;
reg [ 5:0] tx_data_3 = 'd0;
// internal signals
@ -190,56 +190,6 @@ module axi_ad9361_dev_if (
wire [ 5:0] rx_data_3_s;
wire rx_locked_s;
// signal tap
wire [255:0] acq_data_s;
wire [ 1:0] acq_trigger_s;
assign acq_data_s[ 3: 0] = rx_frame;
assign acq_data_s[ 9: 4] = rx_data_3;
assign acq_data_s[ 15: 10] = rx_data_2;
assign acq_data_s[ 21: 16] = rx_data_1;
assign acq_data_s[ 27: 22] = rx_data_0;
assign acq_data_s[ 28: 28] = rx_error_r2;
assign acq_data_s[ 29: 29] = rx_valid_r2;
assign acq_data_s[ 53: 30] = rx_data_r2;
assign acq_data_s[ 54: 54] = adc_valid;
assign acq_data_s[102: 55] = adc_data;
assign acq_data_s[103:103] = adc_status;
assign acq_data_s[104:104] = rx_locked_s;
assign acq_data_s[105:105] = dac_valid;
assign acq_data_s[153:106] = dac_data;
assign acq_data_s[154:154] = tx_data_sel;
assign acq_data_s[202:155] = tx_data;
assign acq_data_s[206:203] = tx_frame;
assign acq_data_s[218:207] = tx_data_0;
assign acq_data_s[230:219] = tx_data_1;
assign acq_data_s[242:231] = tx_data_2;
assign acq_data_s[254:243] = tx_data_3;
assign acq_data_s[255:255] = tx_locked_s;
assign acq_trigger_s[1] = tx_locked_s;
assign acq_trigger_s[0] = rx_locked_s;
sld_signaltap #(
.sld_data_bits (256),
.sld_sample_depth (128),
.sld_ram_block_type ("AUTO"),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_level (1),
.sld_trigger_in_enabled (0),
.sld_enable_advanced_trigger (0),
.sld_trigger_level_pipeline (1),
.sld_node_info (1076736),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (17890),
.sld_node_crc_loword (38728))
i_ila_dev_if (
.acq_clk (clk),
.acq_data_in (acq_data_s),
.acq_trigger_in (acq_trigger_s));
// defaults
assign delay_rdata = 5'd0;

2105
projects/fmcomms2/c5soc/fmcomms2_c5soc.stp
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File diff suppressed because one or more lines are too long

24
projects/fmcomms2/c5soc/system_bd.qsys
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@ -73,6 +73,14 @@
type = "String";
}
}
element sys_int_mem.s1
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sys_gpio.s1
{
datum _lockedAddress
@ -86,11 +94,11 @@
type = "String";
}
}
element sys_int_mem.s1
element axi_ad9361.s_axi
{
datum baseAddress
{
value = "0";
value = "131072";
type = "String";
}
}
@ -102,14 +110,6 @@
type = "String";
}
}
element axi_ad9361.s_axi
{
datum baseAddress
{
value = "131072";
type = "String";
}
}
element axi_dmac_adc.s_axi
{
datum baseAddress
@ -611,7 +611,7 @@
<parameter name="dbg_trace_clk_div" value="0" />
<parameter name="desired_l4_mp_clk_mhz" value="100.0" />
<parameter name="desired_l4_sp_clk_mhz" value="100.0" />
<parameter name="desired_cfg_clk_mhz" value="100.0" />
<parameter name="desired_cfg_clk_mhz" value="80.0" />
<parameter name="desired_sdmmc_clk_mhz" value="200.0" />
<parameter name="desired_nand_clk_mhz" value="12.5" />
<parameter name="desired_qspi_clk_mhz" value="400.0" />
@ -737,7 +737,7 @@
<parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100000000" />
<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="80000000" />
<parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />

56
projects/fmcomms2/c5soc/system_constr.sdc
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@ -1,22 +1,54 @@
create_clock -period "20.000 ns" -name clk_50m [get_ports {sys_clk}]
create_clock -period "3.906 ns" -name clk_250m [get_ports {rx_clk_in}]
create_clock -period "10.000 ns" -name clk_100m [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
create_clock -period "4.000 ns" -name clk_250m [get_ports {rx_clk_in}]
create_clock -period "12.500 ns" -name clk_80m [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_64m [get_clocks {i_system_bd|axi_ad9361|i_ad9361|i_dev_if|i_clk|i_gclk|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|axi_ad9361|i_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from clk_250m -to $clk_64m
set_false_path -from $clk_64m -to clk_250m
set_false_path -from clk_50m -to clk_80m
set_false_path -from clk_50m -to $clk_125m
set_false_path -from clk_80m -to clk_50m
set_false_path -from clk_80m -to $clk_125m
set_false_path -from $clk_125m -to clk_50m
set_false_path -from $clk_125m -to clk_80m
set_false_path -from clk_50m -to clk_100m
set_false_path -from clk_50m -to $clk_64m
set_false_path -from clk_100m -to clk_50m
set_false_path -from clk_100m -to $clk_64m
set_false_path -from $clk_64m -to clk_50m
set_false_path -from $clk_64m -to clk_100m
create_clock -period 4.0 -name v_rx_clk
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}]
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}]
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[1]}]
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[2]}]
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[3]}]
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[4]}]
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[5]}]
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_frame_in}] -clock_fall -add_delay
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[0]}] -clock_fall -add_delay
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[1]}] -clock_fall -add_delay
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[2]}] -clock_fall -add_delay
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clock_fall -add_delay
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay
create_generated_clock -source [get_ports {rx_clk_in}] -name v_tx_clk [get_ports {tx_clk_out}] -phase 90
set_false_path -from clk_250m -to v_tx_clk
set_false_path -from v_tx_clk -to clk_250m
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_frame_out}]
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[0]}]
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[1]}]
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[2]}]
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[3]}]
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[4]}]
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[5]}]
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay