zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS
parent
70d7840c2b
commit
5986e87a1f
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@ -43,3 +43,6 @@ set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## XADC_GPIO_2
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set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## XADC_GPIO_3
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# Define SPI clock
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create_clock -name spi0_clk -period 20 [get_pins -hier */EMIOSPI0SCLKO]
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create_clock -name spi1_clk -period 20 [get_pins -hier */EMIOSPI1SCLKO]
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@ -61,3 +61,6 @@ set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[
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set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3
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# Define SPI clock
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create_clock -name spi0_clk -period 20 [get_pins -hier */EMIOSPI0SCLKO]
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create_clock -name spi1_clk -period 20 [get_pins -hier */EMIOSPI1SCLKO]
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@ -25,3 +25,6 @@ set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6
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set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7
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# Define SPI clock
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create_clock -name spi0_clk -period 20 [get_pins -hier */EMIOSPI0SCLKO]
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create_clock -name spi1_clk -period 20 [get_pins -hier */EMIOSPI1SCLKO]
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@ -87,3 +87,6 @@ set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]] ; ## OTG-RESETN
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# Define SPI clock
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create_clock -name spi0_clk -period 20 [get_pins -hier */EMIOSPI0SCLKO]
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create_clock -name spi1_clk -period 20 [get_pins -hier */EMIOSPI1SCLKO]
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