From 5a1819ed6ed0455b725bd758e4210c8654f429af Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Jan 2015 09:34:18 -0500
Subject: [PATCH] fifo2s: qualify last with valid

---
 library/axi_fifo2s/axi_fifo2s_rd.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/axi_fifo2s/axi_fifo2s_rd.v b/library/axi_fifo2s/axi_fifo2s_rd.v
index d5109bc9b..e10fbc519 100644
--- a/library/axi_fifo2s/axi_fifo2s_rd.v
+++ b/library/axi_fifo2s/axi_fifo2s_rd.v
@@ -181,7 +181,7 @@ module axi_fifo2s_rd (
       end
       if (axi_rd_active == 1'b1) begin
         axi_rd <= 1'b0;
-        if (axi_rlast == 1'b1) begin
+        if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
           axi_rd_active <= 1'b0;
         end
       end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
@@ -238,7 +238,7 @@ module axi_fifo2s_rd (
       axi_rready <= 'd0;
     end else begin
       axi_drst <= ~axi_xfer_req_m[1];
-      axi_dvalid <= axi_rvalid & axi_rready;
+      axi_dvalid <= axi_rvalid;
       axi_ddata <= axi_rdata;
       axi_rready <= 1'b1;
     end
@@ -248,7 +248,7 @@ module axi_fifo2s_rd (
     if (axi_resetn == 1'b0) begin
       axi_rerror <= 'd0;
     end else begin
-      axi_rerror <= axi_rvalid & axi_rready & axi_rresp[1];
+      axi_rerror <= axi_rvalid & axi_rresp[1];
     end
   end