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fifo2s: qualify last with valid

main
Rejeesh Kutty 2015-01-15 09:34:18 -05:00
parent 72e89852b6
commit 5a1819ed6e
1 changed files with 3 additions and 3 deletions
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6
library/axi_fifo2s/axi_fifo2s_rd.v
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@ -181,7 +181,7 @@ module axi_fifo2s_rd (
end end
if (axi_rd_active == 1'b1) begin if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0; axi_rd <= 1'b0;
if (axi_rlast == 1'b1) begin if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
axi_rd_active <= 1'b0; axi_rd_active <= 1'b0;
end end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
@ -238,7 +238,7 @@ module axi_fifo2s_rd (
axi_rready <= 'd0; axi_rready <= 'd0;
end else begin end else begin
axi_drst <= ~axi_xfer_req_m[1]; axi_drst <= ~axi_xfer_req_m[1];
axi_dvalid <= axi_rvalid & axi_rready; axi_dvalid <= axi_rvalid;
axi_ddata <= axi_rdata; axi_ddata <= axi_rdata;
axi_rready <= 1'b1; axi_rready <= 1'b1;
end end
@ -248,7 +248,7 @@ module axi_fifo2s_rd (
if (axi_resetn == 1'b0) begin if (axi_resetn == 1'b0) begin
axi_rerror <= 'd0; axi_rerror <= 'd0;
end else begin end else begin
axi_rerror <= axi_rvalid & axi_rready & axi_rresp[1]; axi_rerror <= axi_rvalid & axi_rresp[1];
end end
end end