From 5a3c3c878bd439c6e3b6961031f166fdc967ee6f Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 9 Sep 2019 15:06:06 +0100 Subject: [PATCH] ad9213_dual_ebz: Initial commit Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators ad9213_dual_ebz/s10soc: Redesign the address layout avl_peripheral_mm_bridge 0x0000000 0x0001FFFF * sys_gpio_in 0x00000000 * sys_gpio_out 0x00000020 * sys_spi 0x00000040 * sys_gpio_bd 0x000000D0 * sys_id 0x000000E0 avl_mm_bridge_0 0x00040000 0x0007FFFF * ad9213_rx_0.phy_reconfig_0 0x00000000 * ad9213_rx_0.phy_reconfig_1 0x00002000 * ad9213_rx_0.phy_reconfig_2 0x00004000 * ad9213_rx_0.phy_reconfig_3 0x00006000 * ad9213_rx_0.phy_reconfig_4 0x00008000 * ad9213_rx_0.phy_reconfig_5 0x0000A000 * ad9213_rx_0.phy_reconfig_6 0x0000C000 * ad9213_rx_0.phy_reconfig_7 0x0000E000 * ad9213_rx_0.phy_reconfig_8 0x00010000 * ad9213_rx_0.phy_reconfig_9 0x00012000 * ad9213_rx_0.phy_reconfig_10 0x00014000 * ad9213_rx_0.phy_reconfig_11 0x00016000 * ad9213_rx_0.phy_reconfig_12 0x00018000 * ad9213_rx_0.phy_reconfig_13 0x0001A000 * ad9213_rx_0.phy_reconfig_14 0x0001C000 * ad9213_rx_0.phy_reconfig_15 0x0001E000 * ad9213_rx_0.link_pll_reconfig 0x00020000 avl_mm_bridge_1 0x00080000 0x000BFFFF * ad9213_rx_1.phy_reconfig_0 0x00000000 * ad9213_rx_1.phy_reconfig_1 0x00002000 * ad9213_rx_1.phy_reconfig_2 0x00004000 * ad9213_rx_1.phy_reconfig_3 0x00006000 * ad9213_rx_1.phy_reconfig_4 0x00008000 * ad9213_rx_1.phy_reconfig_5 0x0000A000 * ad9213_rx_1.phy_reconfig_6 0x0000C000 * ad9213_rx_1.phy_reconfig_7 0x0000E000 * ad9213_rx_1.phy_reconfig_8 0x00010000 * ad9213_rx_1.phy_reconfig_9 0x00012000 * ad9213_rx_1.phy_reconfig_10 0x00014000 * ad9213_rx_1.phy_reconfig_11 0x00016000 * ad9213_rx_1.phy_reconfig_12 0x00018000 * ad9213_rx_1.phy_reconfig_13 0x0001A000 * ad9213_rx_1.phy_reconfig_14 0x0001C000 * ad9213_rx_1.phy_reconfig_15 0x0001E000 * ad9213_rx_1.link_pll_reconfig 0x00020000 Connected directly to the h2s_lw_axi_master * ad9213_rx_0.link_reconfig 0x000C0000 * ad9213_rx_0.link_management 0x000C4000 * ad9213_rx_1.link_reconfig 0x000C8000 * ad9213_rx_1.link_management 0x000CC000 * axi_ad9213_0.s_axi 0x000D0000 * axi_ad9213_1.s_axi 0x000D1000 * axi_ad9213_dma_0.s_axi 0x000D2000 * axi_ad9213_dma_1.s_axi 0x000D3800 --- projects/ad9213_dual_ebz/Makefile | 7 + .../common/ad9213_dual_qsys.tcl | 259 ++++++++++++ projects/ad9213_dual_ebz/s10soc/Makefile | 19 + .../ad9213_dual_ebz/s10soc/system_constr.sdc | 25 ++ .../ad9213_dual_ebz/s10soc/system_project.tcl | 163 ++++++++ .../ad9213_dual_ebz/s10soc/system_qsys.tcl | 6 + projects/ad9213_dual_ebz/s10soc/system_top.v | 381 ++++++++++++++++++ projects/common/s10soc/s10soc_system_qsys.tcl | 4 +- 8 files changed, 862 insertions(+), 2 deletions(-) create mode 100644 projects/ad9213_dual_ebz/Makefile create mode 100644 projects/ad9213_dual_ebz/common/ad9213_dual_qsys.tcl create mode 100755 projects/ad9213_dual_ebz/s10soc/Makefile create mode 100755 projects/ad9213_dual_ebz/s10soc/system_constr.sdc create mode 100755 projects/ad9213_dual_ebz/s10soc/system_project.tcl create mode 100755 projects/ad9213_dual_ebz/s10soc/system_qsys.tcl create mode 100755 projects/ad9213_dual_ebz/s10soc/system_top.v diff --git a/projects/ad9213_dual_ebz/Makefile b/projects/ad9213_dual_ebz/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/ad9213_dual_ebz/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9213_dual_ebz/common/ad9213_dual_qsys.tcl b/projects/ad9213_dual_ebz/common/ad9213_dual_qsys.tcl new file mode 100644 index 000000000..60aedd13c --- /dev/null +++ b/projects/ad9213_dual_ebz/common/ad9213_dual_qsys.tcl @@ -0,0 +1,259 @@ + +set adc_data_width 1024 +set adc_dma_data_width 1024 + +# +## IP instantiations and configuration +# + +add_instance device_clk altera_clock_bridge +set_instance_parameter_value device_clk {EXPLICIT_CLOCK_RATE} {312500000} + +# ad9213_rx_0 JESD204B phy-link layer + +add_instance ad9213_rx_0 adi_jesd204 +set_instance_parameter_value ad9213_rx_0 {ID} {0} +set_instance_parameter_value ad9213_rx_0 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9213_rx_0 {SOFT_PCS} {true} +set_instance_parameter_value ad9213_rx_0 {LANE_RATE} {12500.0} +set_instance_parameter_value ad9213_rx_0 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value ad9213_rx_0 {REFCLK_FREQUENCY} {312.5} +set_instance_parameter_value ad9213_rx_0 {INPUT_PIPELINE_STAGES} {2} +set_instance_parameter_value ad9213_rx_0 {NUM_OF_LANES} {16} +set_instance_parameter_value ad9213_rx_0 {EXT_DEVICE_CLK_EN} {1} +set_instance_parameter_value ad9213_rx_0 {LANE_MAP} {0 1 2 7 14 13 15 4 8 3 10 6 12 5 9 11} + +# ad9213_rx_1 JESD204B phy-link layer + +add_instance ad9213_rx_1 adi_jesd204 +set_instance_parameter_value ad9213_rx_1 {ID} {1} +set_instance_parameter_value ad9213_rx_1 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9213_rx_1 {SOFT_PCS} {true} +set_instance_parameter_value ad9213_rx_1 {LANE_RATE} {12500.0} +set_instance_parameter_value ad9213_rx_1 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value ad9213_rx_1 {REFCLK_FREQUENCY} {312.5} +set_instance_parameter_value ad9213_rx_1 {INPUT_PIPELINE_STAGES} {2} +set_instance_parameter_value ad9213_rx_1 {NUM_OF_LANES} {16} +set_instance_parameter_value ad9213_rx_1 {EXT_DEVICE_CLK_EN} {1} +set_instance_parameter_value ad9213_rx_1 {LANE_MAP} {0 1 2 7 14 13 15 4 8 3 10 6 12 5 9 11} + +# ad9213_tpl_0 JESD204B transport layer + +add_instance axi_ad9213_dual_tpl ad_ip_jesd204_tpl_adc +set_instance_parameter_value axi_ad9213_dual_tpl {ID} {0} +set_instance_parameter_value axi_ad9213_dual_tpl {NUM_CHANNELS} {2} +set_instance_parameter_value axi_ad9213_dual_tpl {NUM_LANES} {32} +set_instance_parameter_value axi_ad9213_dual_tpl {BITS_PER_SAMPLE} {16} +set_instance_parameter_value axi_ad9213_dual_tpl {CONVERTER_RESOLUTION} {16} +set_instance_parameter_value axi_ad9213_dual_tpl {TWOS_COMPLEMENT} {1} +set_instance_parameter_value axi_ad9213_dual_tpl {ENABLE_SAMPLES_PER_FRAME_MANUAL} {1} +set_instance_parameter_value axi_ad9213_dual_tpl {SAMPLES_PER_FRAME_MANUAL} {16} + +# ADC FIFO's + +ad_adcfifo_create "ad9213_adcfifo" $adc_data_width $adc_dma_data_width $adc_fifo_address_width + +set_interface_property ad9213_adcfifo_if_adc_wr EXPORT_OF ad9213_adcfifo.if_adc_wr +set_interface_property ad9213_adcfifo_if_adc_wdata EXPORT_OF ad9213_adcfifo.if_adc_wdata + +# DMA instances + +add_instance axi_ad9213_dma axi_dmac +set_instance_parameter_value axi_ad9213_dma {ID} {0} +set_instance_parameter_value axi_ad9213_dma {DMA_DATA_WIDTH_SRC} {1024} +set_instance_parameter_value axi_ad9213_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9213_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9213_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9213_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9213_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9213_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9213_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9213_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9213_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value axi_ad9213_dma {DMA_AXI_PROTOCOL_DEST} {0} +set_instance_parameter_value axi_ad9213_dma {MAX_BYTES_PER_BURST} {256} +set_instance_parameter_value axi_ad9213_dma {FIFO_SIZE} {16} + +# SPI interfaces + +add_instance adf4377_spi altera_avalon_spi +set_instance_parameter_value adf4377_spi {clockPhase} {1} +set_instance_parameter_value adf4377_spi {clockPolarity} {1} +set_instance_parameter_value adf4377_spi {dataWidth} {8} +set_instance_parameter_value adf4377_spi {masterSPI} {1} +set_instance_parameter_value adf4377_spi {numberOfSlaves} {2} +set_instance_parameter_value adf4377_spi {targetClockRate} {10000000.0} + +add_instance ltc_spi altera_avalon_spi +set_instance_parameter_value ltc_spi {clockPhase} {0} +set_instance_parameter_value ltc_spi {clockPolarity} {0} +set_instance_parameter_value ltc_spi {dataWidth} {8} +set_instance_parameter_value ltc_spi {masterSPI} {1} +set_instance_parameter_value ltc_spi {numberOfSlaves} {2} +set_instance_parameter_value ltc_spi {targetClockRate} {10000000.0} + +# ad9213x2 gpio + +add_instance ad9213_dual_pio altera_avalon_pio +set_instance_parameter_value ad9213_dual_pio {direction} {Bidir} +set_instance_parameter_value ad9213_dual_pio {generateIRQ} {1} +set_instance_parameter_value ad9213_dual_pio {width} {10} +set_instance_parameter_value ad9213_dual_pio {edgeType} {RISING} + +# +## clocks and resets +# + +# system clock and reset + +add_connection sys_clk.clk ad9213_rx_0.sys_clk +add_connection sys_clk.clk ad9213_rx_1.sys_clk +add_connection sys_clk.clk axi_ad9213_dual_tpl.s_axi_clock +add_connection sys_clk.clk axi_ad9213_dma.s_axi_clock +add_connection sys_clk.clk adf4377_spi.clk +add_connection sys_clk.clk ltc_spi.clk +add_connection sys_clk.clk ad9213_dual_pio.clk + +add_connection sys_clk.clk_reset ad9213_rx_0.sys_resetn +add_connection sys_clk.clk_reset ad9213_rx_1.sys_resetn +add_connection sys_clk.clk_reset axi_ad9213_dual_tpl.s_axi_reset +add_connection sys_clk.clk_reset axi_ad9213_dma.s_axi_reset +add_connection sys_clk.clk_reset adf4377_spi.reset +add_connection sys_clk.clk_reset ltc_spi.reset +add_connection sys_clk.clk_reset ad9213_dual_pio.reset + +# device clock and reset + +add_connection device_clk.out_clk ad9213_rx_0.device_clk +add_connection device_clk.out_clk ad9213_rx_1.device_clk +add_connection device_clk.out_clk axi_ad9213_dual_tpl.link_clk +add_connection device_clk.out_clk ad9213_adcfifo.if_adc_clk + +add_connection ad9213_rx_0.link_reset ad9213_adcfifo.if_adc_rst + +# dma clock and reset + +add_connection sys_dma_clk.clk ad9213_adcfifo.if_dma_clk +add_connection sys_dma_clk.clk axi_ad9213_dma.if_s_axis_aclk +add_connection sys_dma_clk.clk axi_ad9213_dma.m_dest_axi_clock + +add_connection sys_dma_clk.clk_reset axi_ad9213_dma.m_dest_axi_reset + +# +## exported signals +# + +add_interface rx_ref_clk_0 clock sink +add_interface rx_ref_clk_1 clock sink +add_interface rx_device_clk clock sink +add_interface rx_sysref_0 conduit end +add_interface rx_sysref_1 conduit end +add_interface rx_sync_0 conduit end +add_interface rx_sync_1 conduit end +add_interface ad9213_rx_0_serial_data conduit end +add_interface ad9213_rx_1_serial_data conduit end +add_interface ad9213_dual_pio conduit end +add_interface adf4377_spi conduit end +add_interface ltc_spi conduit end + +set_interface_property rx_ref_clk_0 EXPORT_OF ad9213_rx_0.ref_clk +set_interface_property rx_ref_clk_1 EXPORT_OF ad9213_rx_1.ref_clk +set_interface_property rx_device_clk EXPORT_OF device_clk.in_clk +set_interface_property rx_sysref_0 EXPORT_OF ad9213_rx_0.sysref +set_interface_property rx_sysref_1 EXPORT_OF ad9213_rx_1.sysref +set_interface_property rx_sync_0 EXPORT_OF ad9213_rx_0.sync +set_interface_property rx_sync_1 EXPORT_OF ad9213_rx_1.sync +set_interface_property ad9213_rx_0_serial_data EXPORT_OF ad9213_rx_0.serial_data +set_interface_property ad9213_rx_1_serial_data EXPORT_OF ad9213_rx_1.serial_data +set_interface_property ad9213_dual_pio EXPORT_OF ad9213_dual_pio.external_connection +set_interface_property adf4377_spi EXPORT_OF adf4377_spi.external +set_interface_property ltc_spi EXPORT_OF ltc_spi.external +set_interface_property axi_ad9213_dual_tpl_adc_ch_0 EXPORT_OF axi_ad9213_dual_tpl.adc_ch_0 +set_interface_property axi_ad9213_dual_tpl_adc_ch_1 EXPORT_OF axi_ad9213_dual_tpl.adc_ch_1 +set_interface_property axi_ad9213_dual_tpl_if_adc_dovf EXPORT_OF axi_ad9213_dual_tpl.if_adc_dovf +set_interface_property axi_ad9213_dual_tpl_link_data EXPORT_OF axi_ad9213_dual_tpl.link_data +set_interface_property ad9213_rx_0_link_data EXPORT_OF ad9213_rx_0.link_data +set_interface_property ad9213_rx_1_link_data EXPORT_OF ad9213_rx_1.link_data + +# +## data interfaces / data path +# + +add_connection ad9213_rx_1.link_sof axi_ad9213_dual_tpl.if_link_sof + +# +# ADC buffer to DMA +# + +add_connection ad9213_adcfifo.m_axis axi_ad9213_dma.s_axis +add_connection axi_ad9213_dma.if_s_axis_xfer_req ad9213_adcfifo.if_dma_xfer_req + +# DMA to HPS memory +ad_dma_interconnect axi_ad9213_dma.m_dest_axi + +# +## address Map +# + +## +## NOTE: if bridge is used, the address will be bridge_base_addr + peripheral_base_addr +## + +ad_cpu_interconnect 0x00020000 ad9213_rx_0.link_pll_reconfig "avl_mm_bridge_0" 0x00040000 +ad_cpu_interconnect 0x00000000 ad9213_rx_0.phy_reconfig_0 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00002000 ad9213_rx_0.phy_reconfig_1 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00004000 ad9213_rx_0.phy_reconfig_2 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00006000 ad9213_rx_0.phy_reconfig_3 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00008000 ad9213_rx_0.phy_reconfig_4 "avl_mm_bridge_0" +ad_cpu_interconnect 0x0000A000 ad9213_rx_0.phy_reconfig_5 "avl_mm_bridge_0" +ad_cpu_interconnect 0x0000C000 ad9213_rx_0.phy_reconfig_6 "avl_mm_bridge_0" +ad_cpu_interconnect 0x0000E000 ad9213_rx_0.phy_reconfig_7 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00010000 ad9213_rx_0.phy_reconfig_8 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00012000 ad9213_rx_0.phy_reconfig_9 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00014000 ad9213_rx_0.phy_reconfig_10 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00016000 ad9213_rx_0.phy_reconfig_11 "avl_mm_bridge_0" +ad_cpu_interconnect 0x00018000 ad9213_rx_0.phy_reconfig_12 "avl_mm_bridge_0" +ad_cpu_interconnect 0x0001A000 ad9213_rx_0.phy_reconfig_13 "avl_mm_bridge_0" +ad_cpu_interconnect 0x0001C000 ad9213_rx_0.phy_reconfig_14 "avl_mm_bridge_0" +ad_cpu_interconnect 0x0001E000 ad9213_rx_0.phy_reconfig_15 "avl_mm_bridge_0" + +ad_cpu_interconnect 0x00020000 ad9213_rx_1.link_pll_reconfig "avl_mm_bridge_1" 0x00080000 +ad_cpu_interconnect 0x00000000 ad9213_rx_1.phy_reconfig_0 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00002000 ad9213_rx_1.phy_reconfig_1 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00004000 ad9213_rx_1.phy_reconfig_2 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00006000 ad9213_rx_1.phy_reconfig_3 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00008000 ad9213_rx_1.phy_reconfig_4 "avl_mm_bridge_1" +ad_cpu_interconnect 0x0000A000 ad9213_rx_1.phy_reconfig_5 "avl_mm_bridge_1" +ad_cpu_interconnect 0x0000C000 ad9213_rx_1.phy_reconfig_6 "avl_mm_bridge_1" +ad_cpu_interconnect 0x0000E000 ad9213_rx_1.phy_reconfig_7 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00010000 ad9213_rx_1.phy_reconfig_8 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00012000 ad9213_rx_1.phy_reconfig_9 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00014000 ad9213_rx_1.phy_reconfig_10 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00016000 ad9213_rx_1.phy_reconfig_11 "avl_mm_bridge_1" +ad_cpu_interconnect 0x00018000 ad9213_rx_1.phy_reconfig_12 "avl_mm_bridge_1" +ad_cpu_interconnect 0x0001A000 ad9213_rx_1.phy_reconfig_13 "avl_mm_bridge_1" +ad_cpu_interconnect 0x0001C000 ad9213_rx_1.phy_reconfig_14 "avl_mm_bridge_1" +ad_cpu_interconnect 0x0001E000 ad9213_rx_1.phy_reconfig_15 "avl_mm_bridge_1" + +ad_cpu_interconnect 0x000C0000 ad9213_rx_0.link_reconfig +ad_cpu_interconnect 0x000C4000 ad9213_rx_0.link_management +ad_cpu_interconnect 0x000C8000 ad9213_rx_1.link_reconfig +ad_cpu_interconnect 0x000CC000 ad9213_rx_1.link_management +ad_cpu_interconnect 0x000D0000 axi_ad9213_dual_tpl.s_axi +ad_cpu_interconnect 0x000D2000 axi_ad9213_dma.s_axi + +ad_cpu_interconnect 0x00000200 ltc_spi.spi_control_port "avl_peripheral_mm_bridge" +ad_cpu_interconnect 0x00000400 adf4377_spi.spi_control_port "avl_peripheral_mm_bridge" +ad_cpu_interconnect 0x00000800 ad9213_dual_pio.s1 "avl_peripheral_mm_bridge" + +# +## interrupts +# + +ad_cpu_interrupt 11 ad9213_rx_0.interrupt +ad_cpu_interrupt 12 ad9213_rx_1.interrupt +ad_cpu_interrupt 13 axi_ad9213_dma.interrupt_sender +ad_cpu_interrupt 15 ad9213_dual_pio.irq +ad_cpu_interrupt 16 adf4377_spi.irq +ad_cpu_interrupt 17 ltc_spi.irq + diff --git a/projects/ad9213_dual_ebz/s10soc/Makefile b/projects/ad9213_dual_ebz/s10soc/Makefile new file mode 100755 index 000000000..628a9327e --- /dev/null +++ b/projects/ad9213_dual_ebz/s10soc/Makefile @@ -0,0 +1,19 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9213_dual_ebz_s10soc + +M_DEPS += ../common/ad9213_dual_qsys.tcl +M_DEPS += ../../common/s10soc/s10soc_system_qsys.tcl +M_DEPS += ../../common/s10soc/s10soc_system_assign.tcl +M_DEPS += ../../common/intel/adcfifo_qsys.tcl +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc + +include ../../scripts/project-intel.mk diff --git a/projects/ad9213_dual_ebz/s10soc/system_constr.sdc b/projects/ad9213_dual_ebz/s10soc/system_constr.sdc new file mode 100755 index 000000000..4a6463a83 --- /dev/null +++ b/projects/ad9213_dual_ebz/s10soc/system_constr.sdc @@ -0,0 +1,25 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "3.2 ns" -name ref_a_clk0 [get_ports {rx_ref_a_clk0}] +create_clock -period "3.2 ns" -name ref_a_clk1 [get_ports {rx_ref_a_clk1}] +create_clock -period "3.2 ns" -name ref_b_clk0 [get_ports {rx_ref_b_clk0}] +create_clock -period "3.2 ns" -name ref_b_clk1 [get_ports {rx_ref_b_clk1}] +create_clock -period "3.2 ns" -name device_clk [get_ports {rx_device_clk_0}] + +# Asynchronous GPIOs + +foreach async_input {ad9213_a_gpio[*] ad9213_b_gpio[*]} { + set_false_path -to [get_ports $async_input] +} + +foreach async_output {ad9213_a_rst ad9213_b_rst ad9213_a_gpio[*] ad9213_b_gpio[*]} { + set_false_path -to [get_ports $async_output] +} + +derive_pll_clocks +derive_clock_uncertainty + +# set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] +# set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] +# +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/ad9213_dual_ebz/s10soc/system_project.tcl b/projects/ad9213_dual_ebz/s10soc/system_project.tcl new file mode 100755 index 000000000..8c54ff95b --- /dev/null +++ b/projects/ad9213_dual_ebz/s10soc/system_project.tcl @@ -0,0 +1,163 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project ad9213_dual_ebz_s10soc + +source $ad_hdl_dir/projects/common/s10soc/s10soc_system_assign.tcl + +# verilog file for top instantiations + +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_3w_spi.v + +################################################################################ +## FMCB+ location assignments (connector P1 on the FMC board) +################################################################################ + +## ad9213_a high speed lanes + +set_location_assignment PIN_AC43 -to rx_serial_data_a[0] ; ## C06 FBD0_M2C_P +set_location_assignment PIN_AD45 -to rx_serial_data_a[1] ; ## A02 FBD1_M2C_P +set_location_assignment PIN_AA43 -to rx_serial_data_a[2] ; ## A06 FBD2_M2C_P +set_location_assignment PIN_AB45 -to rx_serial_data_a[3] ; ## A10 FBD3_M2C_P +set_location_assignment PIN_W43 -to rx_serial_data_a[4] ; ## A15 FBD4_M2C_P +set_location_assignment PIN_Y45 -to rx_serial_data_a[5] ; ## A19 FBD5_M2C_P +set_location_assignment PIN_V45 -to rx_serial_data_a[6] ; ## B16 FBD6_M2C_P +set_location_assignment PIN_U43 -to rx_serial_data_a[7] ; ## B12 FBD7_M2C_P +set_location_assignment PIN_T45 -to rx_serial_data_a[8] ; ## B08 FBD8_M2C_P +set_location_assignment PIN_P45 -to rx_serial_data_a[9] ; ## B04 FBD9_M2C_P +set_location_assignment PIN_R43 -to rx_serial_data_a[10] ; ## Y10 FBD10_M2C_P +set_location_assignment PIN_M45 -to rx_serial_data_a[11] ; ## Z12 FBD11_M2C_P +set_location_assignment PIN_N43 -to rx_serial_data_a[12] ; ## Y14 FBD12_M2C_P +set_location_assignment PIN_K45 -to rx_serial_data_a[13] ; ## Z16 FBD13_M2C_P +set_location_assignment PIN_L43 -to rx_serial_data_a[14] ; ## Y18 FBD14_M2C_P +set_location_assignment PIN_H45 -to rx_serial_data_a[15] ; ## Y22 FBD15_M2C_P + +## clocks and synchronization signals + +set_location_assignment PIN_AB41 -to rx_ref_a_clk0 ; ## B20 FBGBT_CLK1_M2C_P +set_location_assignment PIN_P41 -to rx_ref_a_clk1 ; ## L08 FBGBT_CLK3_M2C_P +set_location_assignment PIN_BE39 -to rx_sync_a ; ## H10 FBLA_04_P +set_location_assignment PIN_BH36 -to rx_device_clk_0 ; ## G06 FBLA_00_P_CC +set_location_assignment PIN_BG37 -to rx_sysref_a ; ## H07 FBLA_02_P + +set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_a_clk0 +set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_a_clk1 +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_a +set_instance_assignment -name IO_STANDARD LVDS -to rx_device_clk_0 +set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref_a + +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sync_a +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref_a + +## ad9213 SPI interface + +set_location_assignment PIN_AT38 -to ad9213_dual_sdio ; ## C10 FBLA_06_P +set_location_assignment PIN_AR37 -to ad9213_dual_sclk ; ## C11 FBLA_06_N +set_location_assignment PIN_BF40 -to ad9213_dual_csn[0] ; ## H13 FBLA_07_P +set_location_assignment PIN_BF39 -to ad9213_dual_csn[1] ; ## H14 FBLA_07_N + +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_dual_sdio +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_dual_sclk +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_dual_csn[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_dual_csn[1] + +## ad9213_a & ad9213_b GPIO lines + +set_location_assignment PIN_BE40 -to ad9213_a_gpio[0] ; ## G12 FBLA_08_P +set_location_assignment PIN_BD40 -to ad9213_a_gpio[1] ; ## G13 FBLA_08_N +set_location_assignment PIN_AW40 -to ad9213_a_gpio[2] ; ## D14 FBLA_09_P +set_location_assignment PIN_AV40 -to ad9213_a_gpio[3] ; ## D15 FBLA_09_N +set_location_assignment PIN_AN33 -to ad9213_a_gpio[4] ; ## C14 FBLA_10_P +set_location_assignment PIN_AP33 -to ad9213_b_gpio[0] ; ## C15 FBLA_10_N +set_location_assignment PIN_BC40 -to ad9213_b_gpio[1] ; ## H16 FBLA_11_P +set_location_assignment PIN_BB40 -to ad9213_b_gpio[2] ; ## H17 FBLA_11_N +set_location_assignment PIN_BD39 -to ad9213_b_gpio[3] ; ## G15 FBLA_12_P +set_location_assignment PIN_BD38 -to ad9213_b_gpio[4] ; ## G16 FBLA_12_N + +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_a_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_a_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_a_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_a_gpio[3] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_a_gpio[4] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_b_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_b_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_b_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_b_gpio[3] +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_b_gpio[4] + +## ad9213 reset lines + +set_location_assignment PIN_AT37 -to ad9213_a_rst ; ## D17 FBLA_13_P +set_location_assignment PIN_AT36 -to ad9213_b_rst ; ## D18 FBLA_13_N + +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_a_rst +set_instance_assignment -name IO_STANDARD "1.8V" -to ad9213_b_rst + +## ltc SPI interface + +set_location_assignment PIN_BB39 -to ltc6952_csn ; ## G21 FBLA_20_P +set_location_assignment PIN_AY40 -to ltc6946_csn ; ## G10 FBLA_03_N +set_location_assignment PIN_AP31 -to ltc_sclk ; ## C19 FBLA_14_N +set_location_assignment PIN_BB38 -to ltc_sdi ; ## H19 FBLA_15_P +set_location_assignment PIN_BA40 -to ltc6946_sdo ; ## G09 FBLA_03_P +set_location_assignment PIN_BA39 -to ltc6952_sdo ; ## G22 FBLA_20_N + +set_instance_assignment -name IO_STANDARD "1.8V" -to ltc_sdi +set_instance_assignment -name IO_STANDARD "1.8V" -to ltc_0_sdo +set_instance_assignment -name IO_STANDARD "1.8V" -to ltc_1_sdo +set_instance_assignment -name IO_STANDARD "1.8V" -to ltc_sclk +set_instance_assignment -name IO_STANDARD "1.8V" -to ltc_csn[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to ltc_csn[1] + +## ADF4377 SPI interface + +set_location_assignment PIN_BF37 -to adf4377_sclk ; ## G18 FBLA_16_P +set_location_assignment PIN_BE37 -to adf4377_sdio ; ## G19 FBLA_16_N +set_location_assignment PIN_AY38 -to adf4377_csn[0] ; ## H22 FBLA_19_P +set_location_assignment PIN_AY39 -to adf4377_csn[1] ; ## H23 FBLA_19_N + +set_instance_assignment -name IO_STANDARD "1.8V" -to adf4377_sdio +set_instance_assignment -name IO_STANDARD "1.8V" -to adf4377_sclk +set_instance_assignment -name IO_STANDARD "1.8V" -to adf4377_csn[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to adf4377_csn[1] + +################################################################################ +## FMCA+ location assignments (connector P2 on the FMC board) +################################################################################ + +## ad9213_1 + +set_location_assignment PIN_BH41 -to rx_serial_data_b[0] ; ## C06 FAD0M2CP +set_location_assignment PIN_BJ43 -to rx_serial_data_b[1] ; ## A02 FAD1M2CP +set_location_assignment PIN_BG43 -to rx_serial_data_b[2] ; ## A06 FAD2M2CP +set_location_assignment PIN_BE43 -to rx_serial_data_b[3] ; ## A10 FAD3M2CP +set_location_assignment PIN_BC43 -to rx_serial_data_b[4] ; ## A14 FAD4M2CP +set_location_assignment PIN_BD45 -to rx_serial_data_b[5] ; ## A18 FAD5M2CP +set_location_assignment PIN_BA43 -to rx_serial_data_b[6] ; ## B16 FAD6M2CP +set_location_assignment PIN_BB45 -to rx_serial_data_b[7] ; ## B12 FAD7M2CP +set_location_assignment PIN_AW43 -to rx_serial_data_b[8] ; ## B08 FAD8M2CP +set_location_assignment PIN_AY45 -to rx_serial_data_b[9] ; ## B04 FAD9M2CP +set_location_assignment PIN_AU43 -to rx_serial_data_b[10] ; ## Y10 FAD10M2CP +set_location_assignment PIN_AV45 -to rx_serial_data_b[11] ; ## Z12 FAD11M2CP +set_location_assignment PIN_AR43 -to rx_serial_data_b[12] ; ## Y14 FAD12M2CP +set_location_assignment PIN_AT45 -to rx_serial_data_b[13] ; ## Z16 FAD13M2CP +set_location_assignment PIN_AP45 -to rx_serial_data_b[14] ; ## Y18 FAD14M2CP +set_location_assignment PIN_AN43 -to rx_serial_data_b[15] ; ## Y22 FAD15M2CP + + +## clocks and synchronization signals + +set_location_assignment PIN_AK41 -to rx_ref_b_clk0 ; ## B20 FAGBTCLK1M2CP +set_location_assignment PIN_AM41 -to rx_ref_b_clk1 ; ## L08 FAGBTCLK3M2CP +set_location_assignment PIN_BC30 -to rx_sync_b ; ## H10 FALA04P + +set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_b_clk0 +set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_b_clk1 +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_b +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sync_b + +# set optimization to get a better timing closure +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +execute_flow -compile diff --git a/projects/ad9213_dual_ebz/s10soc/system_qsys.tcl b/projects/ad9213_dual_ebz/s10soc/system_qsys.tcl new file mode 100755 index 000000000..e6f358058 --- /dev/null +++ b/projects/ad9213_dual_ebz/s10soc/system_qsys.tcl @@ -0,0 +1,6 @@ + +set adc_fifo_address_width 14 + +source $ad_hdl_dir/projects/common/s10soc/s10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl +source ../common/ad9213_dual_qsys.tcl diff --git a/projects/ad9213_dual_ebz/s10soc/system_top.v b/projects/ad9213_dual_ebz/s10soc/system_top.v new file mode 100755 index 000000000..1f683a367 --- /dev/null +++ b/projects/ad9213_dual_ebz/s10soc/system_top.v @@ -0,0 +1,381 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input fpga_resetn, + input hps_ref_clk, + + // hps-ddr4 (72) + + input hps_ddr_ref_clk, + input hps_ddr_rzq, + output [ 16:0] hps_ddr_a, + output [ 0:0] hps_ddr_act_n, + input [ 0:0] hps_ddr_alert_n, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_ck, + output [ 0:0] hps_ddr_ck_n, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_par, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_reset_n, + inout [ 8:0] hps_ddr_dqs_p, + inout [ 8:0] hps_ddr_dqs_n, + inout [ 8:0] hps_ddr_dbi_n, + inout [ 71:0] hps_ddr_dq, + + // hps-ethernet + + input [ 0:0] hps_emac_rx_clk, + input [ 0:0] hps_emac_rx_ctl, + input [ 3:0] hps_emac_rx, + output [ 0:0] hps_emac_tx_clk, + output [ 0:0] hps_emac_tx_ctl, + output [ 3:0] hps_emac_tx, + output [ 0:0] hps_emac_mdc, + inout [ 0:0] hps_emac_mdio, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_data, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // fpga-gpio motherboard (led/dpsw/button) + + input [ 3:0] fpga_gpio_dpsw, + input [ 3:0] fpga_gpio_btn, + output [ 3:0] fpga_gpio_led, + + // sdmmc-interface + + output hps_sdmmc_clk, + inout hps_sdmmc_cmd, + inout [ 3:0] hps_sdmmc_data, + + // jtag-interface + + input hps_jtag_tck, + input hps_jtag_tms, + output hps_jtag_tdo, + input hps_jtag_tdi, + + // hps-OOBE daughter card peripherals + + inout hps_gpio_eth_irq, + inout hps_gpio_usb_oci, + inout [ 1:0] hps_gpio_btn, + inout [ 2:0] hps_gpio_led, + + // ad9213_a JESD204B high-speed interface + + input rx_ref_a_clk0, + input rx_ref_a_clk1, + input rx_device_clk_0, + input [ 15:0] rx_serial_data_a, + output rx_sync_a, + input rx_sysref_a, + + // ad9213_b JESD204B high-speed interface + + input rx_ref_b_clk0, + input rx_ref_b_clk1, + input [ 15:0] rx_serial_data_b, + output rx_sync_b, + + // configuration interfaces + + inout ad9213_dual_sdio, + output ad9213_dual_sclk, + output [ 1:0] ad9213_dual_csn, + + inout [ 4:0] ad9213_a_gpio, + inout [ 4:0] ad9213_b_gpio, + + output ad9213_a_rst, + output ad9213_b_rst, + + output ltc6952_csn, + output ltc6946_csn, + output ltc_sclk, + output ltc_sdi, + input ltc6952_sdo, + input ltc6946_sdo, + + output adf4377_sclk, + inout adf4377_sdio, + output [ 1:0] adf4377_csn + +); + + // internal signals + + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire spi_mosi_s; + wire spi_miso_s; + wire ninit_done_s; + wire h2f_reset_s; + wire sys_resetn_s; + wire ltc_sdo_s; + wire adf4377_sdi_s; + wire adf4377_sdo_s; + wire [511:0] adc_data_0; + wire [511:0] adc_data_1; + wire [511:0] link_data_0; + wire [511:0] link_data_1; + wire [1023:0] adc_data; + wire adc_enable_0; + wire adc_enable_1; + wire adc_valid; + reg adc_valid_d1; + reg [1023:0] adc_data_d1; + reg [511:0] adc_data_0_d1; + reg [511:0] adc_data_1_d1; + wire [ 1:0] ltc_csn; + + // motherboard-gpio + + assign gpio_i[3:0] = fpga_gpio_dpsw; + assign gpio_i[7:4] = fpga_gpio_btn; + assign gpio_i[31:8] = gpio_o[31:8]; + assign fpga_gpio_led = gpio_o[11:8]; + + // assignments + + assign ad9213_a_rst = gpio_o[32]; + assign ad9213_b_rst = gpio_o[33]; + assign gpio_i[63:32] = gpio_o[63:32]; + assign ltc6952_csn = ltc_csn[0]; + assign ltc6946_csn = ltc_csn[1]; + + // instantiations + + ad_3w_spi #( + .NUM_OF_SLAVES(2)) + i_ad_3w_spi_ad9213_dual ( + .spi_csn (ad9213_dual_csn), + .spi_clk (ad9213_dual_sclk), + .spi_mosi (spi_mosi_s), + .spi_miso (spi_miso_s), + .spi_sdio (ad9213_dual_sdio), + .spi_dir ()); + + ad_3w_spi #( + .NUM_OF_SLAVES(2)) + i_ad_3w_spi_adf4377 ( + .spi_csn (adf4377_csn), + .spi_clk (adf4377_sclk), + .spi_mosi (adf4377_sdi_s), + .spi_miso (adf4377_sdo_s), + .spi_sdio (adf4377_sdio), + .spi_dir ()); + + // SDO line (MISO) switching for the two ltc + assign ltc_sdo_s = (ltc_csn == 2'b10) ? ltc6952_sdo : + (ltc_csn == 2'b01) ? ltc6946_sdo : 1'b0; + + // system reset is a combination of external reset, HPS reset and S10 init + // done reset + assign sys_resetn_s = fpga_resetn & ~h2f_reset_s & ~ninit_done_s; + + genvar i; + for (i = 0; i < 512; i = i + 16) begin + assign adc_data[(2*i)+31:(2*i)] ={adc_data_1[i+15:i],adc_data_0[i+15:i]}; + end + + always @(posedge rx_device_clk_0) begin + adc_data_0_d1 <= adc_data_0; + adc_data_1_d1 <= adc_data_1; + + case ({adc_enable_1,adc_enable_0}) + 2'b01: adc_data_d1 <= {adc_data_0,adc_data_0_d1}; + 2'b10: adc_data_d1 <= {adc_data_1,adc_data_1_d1}; + 2'b11: adc_data_d1 <= adc_data; + default: adc_data_d1 <= adc_data_d1; + endcase + case ({adc_enable_1,adc_enable_0}) + 2'b01: adc_valid_d1 <= ~adc_valid_d1; + 2'b10: adc_valid_d1 <= ~adc_valid_d1; + 2'b11: adc_valid_d1<= adc_valid; + default: adc_valid_d1 <= adc_valid; + endcase + end + + system_bd i_system_bd ( + .sys_clk_clk ( sys_clk ), + .sys_rst_reset_n ( sys_resetn_s ), + .h2f_reset_reset ( h2f_reset_s ), + .rst_ninit_done_ninit_done ( ninit_done_s ), + .sys_gpio_bd_in_port ( gpio_i[31: 0] ), + .sys_gpio_bd_out_port ( gpio_o[31: 0] ), + .sys_gpio_in_export ( gpio_i[63:32] ), + .sys_gpio_out_export ( gpio_o[63:32] ), + .sys_hps_io_hps_io_phery_emac0_TX_CLK ( hps_emac_tx_clk ), + .sys_hps_io_hps_io_phery_emac0_TXD0 ( hps_emac_tx[0] ), + .sys_hps_io_hps_io_phery_emac0_TXD1 ( hps_emac_tx[1] ), + .sys_hps_io_hps_io_phery_emac0_TXD2 ( hps_emac_tx[2] ), + .sys_hps_io_hps_io_phery_emac0_TXD3 ( hps_emac_tx[3] ), + .sys_hps_io_hps_io_phery_emac0_RX_CTL ( hps_emac_rx_ctl ), + .sys_hps_io_hps_io_phery_emac0_TX_CTL ( hps_emac_tx_ctl ), + .sys_hps_io_hps_io_phery_emac0_RX_CLK ( hps_emac_rx_clk ), + .sys_hps_io_hps_io_phery_emac0_RXD0 ( hps_emac_rx[0] ), + .sys_hps_io_hps_io_phery_emac0_RXD1 ( hps_emac_rx[1] ), + .sys_hps_io_hps_io_phery_emac0_RXD2 ( hps_emac_rx[2] ), + .sys_hps_io_hps_io_phery_emac0_RXD3 ( hps_emac_rx[3] ), + .sys_hps_io_hps_io_phery_emac0_MDIO ( hps_emac_mdio ), + .sys_hps_io_hps_io_phery_emac0_MDC ( hps_emac_mdc ), + .sys_hps_io_hps_io_phery_sdmmc_CMD ( hps_sdmmc_cmd ), + .sys_hps_io_hps_io_phery_sdmmc_D0 ( hps_sdmmc_data[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 ( hps_sdmmc_data[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 ( hps_sdmmc_data[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 ( hps_sdmmc_data[3]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK ( hps_sdmmc_clk ), + .sys_hps_io_hps_io_phery_usb0_DATA0 ( hps_usb_data[0] ), + .sys_hps_io_hps_io_phery_usb0_DATA1 ( hps_usb_data[1] ), + .sys_hps_io_hps_io_phery_usb0_DATA2 ( hps_usb_data[2] ), + .sys_hps_io_hps_io_phery_usb0_DATA3 ( hps_usb_data[3] ), + .sys_hps_io_hps_io_phery_usb0_DATA4 ( hps_usb_data[4] ), + .sys_hps_io_hps_io_phery_usb0_DATA5 ( hps_usb_data[5] ), + .sys_hps_io_hps_io_phery_usb0_DATA6 ( hps_usb_data[6] ), + .sys_hps_io_hps_io_phery_usb0_DATA7 ( hps_usb_data[7] ), + .sys_hps_io_hps_io_phery_usb0_CLK ( hps_usb_clk ), + .sys_hps_io_hps_io_phery_usb0_STP ( hps_usb_stp ), + .sys_hps_io_hps_io_phery_usb0_DIR ( hps_usb_dir ), + .sys_hps_io_hps_io_phery_usb0_NXT ( hps_usb_nxt ), + .sys_hps_io_hps_io_phery_uart0_RX ( hps_uart_rx ), + .sys_hps_io_hps_io_phery_uart0_TX ( hps_uart_tx ), + .sys_hps_io_hps_io_phery_i2c1_SDA ( hps_i2c_sda ), + .sys_hps_io_hps_io_phery_i2c1_SCL ( hps_i2c_scl ), + .sys_hps_io_hps_io_gpio_gpio1_io0 ( hps_gpio_eth_irq ), + .sys_hps_io_hps_io_gpio_gpio1_io1 ( hps_gpio_usb_oci ), + .sys_hps_io_hps_io_gpio_gpio1_io4 ( hps_gpio_btn[0] ), + .sys_hps_io_hps_io_gpio_gpio1_io5 ( hps_gpio_btn[1] ), + .sys_hps_io_hps_io_jtag_tck ( hps_jtag_tck ), + .sys_hps_io_hps_io_jtag_tms ( hps_jtag_tms ), + .sys_hps_io_hps_io_jtag_tdo ( hps_jtag_tdo ), + .sys_hps_io_hps_io_jtag_tdi ( hps_jtag_tdi ), + .sys_hps_io_hps_io_hps_ocs_clk ( hps_ref_clk ), + .sys_hps_io_hps_io_gpio_gpio1_io19 ( hps_gpio_led[1] ), + .sys_hps_io_hps_io_gpio_gpio1_io20 ( hps_gpio_led[0] ), + .sys_hps_io_hps_io_gpio_gpio1_io21 ( hps_gpio_led[2] ), + .sys_hps_ddr_ref_clk_clk ( hps_ddr_ref_clk ), + .sys_hps_ddr_oct_oct_rzqin ( hps_ddr_rzq ), + .sys_hps_ddr_mem_ck ( hps_ddr_ck ), + .sys_hps_ddr_mem_ck_n ( hps_ddr_ck_n ), + .sys_hps_ddr_mem_a ( hps_ddr_a ), + .sys_hps_ddr_mem_act_n ( hps_ddr_act_n ), + .sys_hps_ddr_mem_ba ( hps_ddr_ba ), + .sys_hps_ddr_mem_bg ( hps_ddr_bg ), + .sys_hps_ddr_mem_cke ( hps_ddr_cke ), + .sys_hps_ddr_mem_cs_n ( hps_ddr_cs_n ), + .sys_hps_ddr_mem_odt ( hps_ddr_odt ), + .sys_hps_ddr_mem_reset_n ( hps_ddr_reset_n ), + .sys_hps_ddr_mem_par ( hps_ddr_par ), + .sys_hps_ddr_mem_alert_n ( hps_ddr_alert_n ), + .sys_hps_ddr_mem_dqs ( hps_ddr_dqs_p ), + .sys_hps_ddr_mem_dqs_n ( hps_ddr_dqs_n ), + .sys_hps_ddr_mem_dq ( hps_ddr_dq ), + .sys_hps_ddr_mem_dbi_n ( hps_ddr_dbi_n ), + // Link to TPL connections + .ad9213_rx_0_link_data_data ( link_data_0 ), + .ad9213_rx_0_link_data_valid ( link_valid_0 ), + .ad9213_rx_1_link_data_data ( link_data_1 ), + .ad9213_rx_1_link_data_valid ( link_valid_1 ), + .axi_ad9213_dual_tpl_link_data_data ( {link_data_1,link_data_0} ), + .axi_ad9213_dual_tpl_link_data_valid ( link_valid_1&link_valid_0 ), + .axi_ad9213_dual_tpl_link_data_ready (), + // TPL connections to PACK + .axi_ad9213_dual_tpl_adc_ch_0_enable ( adc_enable_0 ), + .axi_ad9213_dual_tpl_adc_ch_0_valid ( adc_valid ), + .axi_ad9213_dual_tpl_adc_ch_0_data ( adc_data_0 ), + .axi_ad9213_dual_tpl_adc_ch_1_enable ( adc_enable_1 ), + .axi_ad9213_dual_tpl_adc_ch_1_valid (), + .axi_ad9213_dual_tpl_adc_ch_1_data ( adc_data_1 ), + // PACK to ADC FIFO + .ad9213_adcfifo_if_adc_wr_valid ( adc_valid_d1 ), + .ad9213_adcfifo_if_adc_wdata_data ( adc_data_d1 ), + // SPI interface for the two ad9213 + .sys_spi_MISO ( spi_miso_s ), + .sys_spi_MOSI ( spi_mosi_s ), + .sys_spi_SCLK ( ad9213_dual_sclk ), + .sys_spi_SS_n ( ad9213_dual_csn ), + // SPI interface for the ltc + .ltc_spi_MISO ( ltc_sdo_s ), + .ltc_spi_MOSI ( ltc_sdi ), + .ltc_spi_SCLK ( ltc_sclk ), + .ltc_spi_SS_n ( ltc_csn ), + // SPI interface for the ADF4377 + .adf4377_spi_MISO ( adf4377_sdo_s ), + .adf4377_spi_MOSI ( adf4377_sdi_s ), + .adf4377_spi_SCLK ( adf4377_sclk ), + .adf4377_spi_SS_n ( adf4377_csn ), + // JESD204B high-speed interface + .rx_ref_clk_0_clk ( rx_ref_a_clk0 ), + .ad9213_rx_0_serial_data_rx_serial_data ( rx_serial_data_a ), + .rx_sysref_0_export ( rx_sysref_a ), + .rx_sync_0_export ( rx_sync_a ), + .rx_ref_clk_1_clk ( rx_ref_b_clk0 ), + .ad9213_rx_1_serial_data_rx_serial_data ( rx_serial_data_b ), + .rx_sysref_1_export ( rx_sysref_a ), + .rx_sync_1_export ( rx_sync_b ), + .rx_device_clk_clk ( rx_device_clk_0 ), + // ad9213_a|b gpio + .ad9213_dual_pio_export ( {ad9213_b_gpio, ad9213_a_gpio} )); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/common/s10soc/s10soc_system_qsys.tcl b/projects/common/s10soc/s10soc_system_qsys.tcl index 317d75390..01438d61b 100644 --- a/projects/common/s10soc/s10soc_system_qsys.tcl +++ b/projects/common/s10soc/s10soc_system_qsys.tcl @@ -103,7 +103,7 @@ set_instance_parameter_value sys_hps {EMAC_PTP_REF_CLK} {100} set_instance_parameter_value sys_hps {EMIF_BYPASS_CHECK} {0} set_instance_parameter_value sys_hps {EMIF_CONDUIT_Enable} {1} set_instance_parameter_value sys_hps {F2SDRAM0_Width} {3} -set_instance_parameter_value sys_hps {F2SDRAM0_ready_latency} {0} +set_instance_parameter_value sys_hps {F2SDRAM0_ready_latency} {2} set_instance_parameter_value sys_hps {F2SDRAM_ADDRESS_WIDTH} {32} set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1} set_instance_parameter_value sys_hps {GPIO_REF_CLK} {4} @@ -111,7 +111,7 @@ set_instance_parameter_value sys_hps {GPIO_REF_CLK2} {200} set_instance_parameter_value sys_hps {H2F_COLD_RST_Enable} {1} set_instance_parameter_value sys_hps {H2F_PENDING_RST_Enable} {1} set_instance_parameter_value sys_hps {H2F_USER0_CLK_Enable} {1} -set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {200} +set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {250} set_instance_parameter_value sys_hps {HPS_BOOT} {1} set_instance_parameter_value sys_hps {HPS_IO_Enable} $hps_io_list set_instance_parameter_value sys_hps {IO_OUTPUT_DELAY12} {17}