From 5a8f277253dc57ac9a386393f8b201af6c30e2ed Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 31 Mar 2020 10:18:59 +0100 Subject: [PATCH] adrv9009/s10soc: Add support for Stratix10 SOC --- projects/adrv9009/s10soc/Makefile | 19 ++ projects/adrv9009/s10soc/system_constr.sdc | 9 + projects/adrv9009/s10soc/system_project.tcl | 140 +++++++++ projects/adrv9009/s10soc/system_qsys.tcl | 7 + projects/adrv9009/s10soc/system_top.v | 297 ++++++++++++++++++++ 5 files changed, 472 insertions(+) create mode 100755 projects/adrv9009/s10soc/Makefile create mode 100755 projects/adrv9009/s10soc/system_constr.sdc create mode 100755 projects/adrv9009/s10soc/system_project.tcl create mode 100755 projects/adrv9009/s10soc/system_qsys.tcl create mode 100755 projects/adrv9009/s10soc/system_top.v diff --git a/projects/adrv9009/s10soc/Makefile b/projects/adrv9009/s10soc/Makefile new file mode 100755 index 000000000..8491313e1 --- /dev/null +++ b/projects/adrv9009/s10soc/Makefile @@ -0,0 +1,19 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9009_s10soc + +# M_DEPS += ../common/adrv9009_qsys.tcl +#M_DEPS += ../../common/altera/dacfifo_qsys.tcl +M_DEPS += ../../common/s10soc/s10soc_system_qsys.tcl +M_DEPS += ../../common/s10soc/s10soc_system_assign.tcl + +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += axi_adrv9009 +LIB_DEPS += axi_dmac +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-intel.mk diff --git a/projects/adrv9009/s10soc/system_constr.sdc b/projects/adrv9009/s10soc/system_constr.sdc new file mode 100755 index 000000000..ad8c4a210 --- /dev/null +++ b/projects/adrv9009/s10soc/system_constr.sdc @@ -0,0 +1,9 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.069 ns" -name ref_clk0 [get_ports {ref_clk0}] +create_clock -period "4.069 ns" -name ref_clk1 [get_ports {ref_clk1}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/adrv9009/s10soc/system_project.tcl b/projects/adrv9009/s10soc/system_project.tcl new file mode 100755 index 000000000..645ac71c9 --- /dev/null +++ b/projects/adrv9009/s10soc/system_project.tcl @@ -0,0 +1,140 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project adrv9009_s10soc + +source $ad_hdl_dir/projects/common/s10soc/s10soc_system_assign.tcl + +## adrv9009 + +set_location_assignment PIN_AP41 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC) +set_location_assignment PIN_AP40 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC) +set_location_assignment PIN_AK41 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_location_assignment PIN_AK40 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_location_assignment PIN_BJ43 -to rx_serial_data[0] ; ## A02 FMC_HPC_DP1_M2C_P +set_location_assignment PIN_BJ42 -to "rx_serial_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N +set_location_assignment PIN_BG43 -to rx_serial_data[1] ; ## A06 FMC_HPC_DP2_M2C_P +set_location_assignment PIN_BG42 -to "rx_serial_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N +set_location_assignment PIN_BH41 -to rx_serial_data[2] ; ## C06 FMC_HPC_DP0_M2C_P +set_location_assignment PIN_BH40 -to "rx_serial_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N +set_location_assignment PIN_BE43 -to rx_serial_data[3] ; ## A10 FMC_HPC_DP3_M2C_P +set_location_assignment PIN_BE42 -to "rx_serial_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N +set_location_assignment PIN_BF45 -to tx_serial_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_serial_data_p[0]) +set_location_assignment PIN_BF44 -to "tx_serial_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_serial_data_n[0]) +set_location_assignment PIN_BG47 -to tx_serial_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_serial_data_p[3]) +set_location_assignment PIN_BG46 -to "tx_serial_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_serial_data_n[3]) +set_location_assignment PIN_BJ46 -to tx_serial_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_serial_data_p[2]) +set_location_assignment PIN_BJ45 -to "tx_serial_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_serial_data_n[2]) +set_location_assignment PIN_BE47 -to tx_serial_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_serial_data_p[1]) +set_location_assignment PIN_BE46 -to "tx_serial_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_serial_data_n[1]) + +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data + +# Merge RX and TX into single transceiver +for {set i 0} {$i < 4} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] +} + +set_location_assignment PIN_BC31 -to rx_sync ; ## G09 FMC_HPC_LA03_P +set_location_assignment PIN_BC32 -to rx_sync(n) ; ## G10 FMC_HPC_LA03_N +set_location_assignment PIN_BF20 -to rx_os_sync ; ## G27 FMC_HPC_LA25_P (Sniffer) +set_location_assignment PIN_BG20 -to rx_os_sync(n) ; ## G28 FMC_HPC_LA25_N (Sniffer) +set_location_assignment PIN_AN20 -to tx_sync ; ## H07 FMC_HPC_LA02_P +set_location_assignment PIN_AP20 -to tx_sync(n) ; ## H08 FMC_HPC_LA02_N +set_location_assignment PIN_AW30 -to sysref ; ## G06 FMC_HPC_LA00_CC_P +set_location_assignment PIN_AW31 -to sysref(n) ; ## G07 FMC_HPC_LA00_CC_N +set_location_assignment PIN_BH20 -to tx_sync_1 ; ## H28 FMC_HPC_LA24_P +set_location_assignment PIN_BH21 -to tx_sync_1(n) ; ## H29 FMC_HPC_LA24_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync +set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_1 +set_instance_assignment -name IO_STANDARD LVDS -to sysref +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_1 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref + +set_location_assignment PIN_BA30 -to spi_csn_ad9528 ; ## D15 FMC_HPC_LA09_N +set_location_assignment PIN_BA31 -to spi_csn_adrv9009 ; ## D14 FMC_HPC_LA09_P +set_location_assignment PIN_BE32 -to spi_clk ; ## H13 FMC_HPC_LA07_P +set_location_assignment PIN_BF32 -to spi_mosi ; ## H14 FMC_HPC_LA07_N +set_location_assignment PIN_BH32 -to spi_miso ; ## G12 FMC_HPC_LA08_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adrv9009 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso + +set_location_assignment PIN_BH18 -to ad9528_reset_b ; ## D26 FMC_HPC_LA26_P +set_location_assignment PIN_BJ18 -to ad9528_sysref_req ; ## D27 FMC_HPC_LA26_N +set_location_assignment PIN_AT21 -to adrv9009_tx1_enable ; ## D17 FMC_HPC_LA13_P +set_location_assignment PIN_AU32 -to adrv9009_tx2_enable ; ## C18 FMC_HPC_LA14_P +set_location_assignment PIN_AR21 -to adrv9009_rx1_enable ; ## D18 FMC_HPC_LA13_N +set_location_assignment PIN_AT32 -to adrv9009_rx2_enable ; ## C19 FMC_HPC_LA14_N +set_location_assignment PIN_AT15 -to adrv9009_test ; ## H16 FMC_HPC_LA11_P +set_location_assignment PIN_BC30 -to adrv9009_reset_b ; ## H10 FMC_HPC_LA04_P +set_location_assignment PIN_BD30 -to adrv9009_gpint ; ## H11 FMC_HPC_LA04_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_test +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpint + +# single ended default + +set_location_assignment PIN_AN17 -to adrv9009_gpio[0] ; ## H19 FMC_HPC_LA15_P +set_location_assignment PIN_AN18 -to adrv9009_gpio[1] ; ## H20 FMC_HPC_LA15_N +set_location_assignment PIN_BA20 -to adrv9009_gpio[2] ; ## G18 FMC_HPC_LA16_P +set_location_assignment PIN_BA21 -to adrv9009_gpio[3] ; ## G19 FMC_HPC_LA16_N +set_location_assignment PIN_BG18 -to adrv9009_gpio[4] ; ## H25 FMC_HPC_LA21_P +set_location_assignment PIN_BG19 -to adrv9009_gpio[5] ; ## H26 FMC_HPC_LA21_N +set_location_assignment PIN_BG17 -to adrv9009_gpio[6] ; ## C22 FMC_HPC_LA18_CC_P +set_location_assignment PIN_BH17 -to adrv9009_gpio[7] ; ## C23 FMC_HPC_LA18_CC_N +set_location_assignment PIN_BJ36 -to adrv9009_gpio[8] ; ## G25 FMC_HPC_LA22_N (LVDS_1N) +set_location_assignment PIN_BE18 -to adrv9009_gpio[9] ; ## H22 FMC_HPC_LA19_P (LVDS_2P) +set_location_assignment PIN_BD18 -to adrv9009_gpio[10] ; ## H23 FMC_HPC_LA19_N (LVDS_2N) +set_location_assignment PIN_AN21 -to adrv9009_gpio[11] ; ## G21 FMC_HPC_LA20_P (LVDS_3P) +set_location_assignment PIN_AP21 -to adrv9009_gpio[12] ; ## G22 FMC_HPC_LA20_N (LVDS_3N) +set_location_assignment PIN_AU28 -to adrv9009_gpio[13] ; ## G16 FMC_HPC_LA12_N (LVDS_4N) +set_location_assignment PIN_AU29 -to adrv9009_gpio[14] ; ## G15 FMC_HPC_LA12_P (LVDS_4P) +set_location_assignment PIN_BJ35 -to adrv9009_gpio[15] ; ## G24 FMC_HPC_LA22_P (LVDS_1P) +set_location_assignment PIN_BF30 -to adrv9009_gpio[16] ; ## C11 FMC_HPC_LA06_N (LVDS_5N) +set_location_assignment PIN_BF31 -to adrv9009_gpio[17] ; ## C10 FMC_HPC_LA06_P (LVDS_5P) +set_location_assignment PIN_BH30 -to adrv9009_gpio[18] ; ## D12 FMC_HPC_LA05_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[18] + +# set optimization to get a better timing closure +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +execute_flow -compile diff --git a/projects/adrv9009/s10soc/system_qsys.tcl b/projects/adrv9009/s10soc/system_qsys.tcl new file mode 100755 index 000000000..5a51a8dfb --- /dev/null +++ b/projects/adrv9009/s10soc/system_qsys.tcl @@ -0,0 +1,7 @@ + +set dac_fifo_address_width 10 +set xcvr_reconfig_addr_width 11 + +source $ad_hdl_dir/projects/common/s10soc/s10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl +source ../common/adrv9009_qsys.tcl diff --git a/projects/adrv9009/s10soc/system_top.v b/projects/adrv9009/s10soc/system_top.v new file mode 100755 index 000000000..3b1a68671 --- /dev/null +++ b/projects/adrv9009/s10soc/system_top.v @@ -0,0 +1,297 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input fpga_resetn, + input hps_ref_clk, + + // hps-ddr4 (72) + + input hps_ddr_ref_clk, + input hps_ddr_rzq, + output [ 16:0] hps_ddr_a, + output [ 0:0] hps_ddr_act_n, + input [ 0:0] hps_ddr_alert_n, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_ck, + output [ 0:0] hps_ddr_ck_n, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_par, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_reset_n, + inout [ 8:0] hps_ddr_dqs_p, + inout [ 8:0] hps_ddr_dqs_n, + inout [ 8:0] hps_ddr_dbi_n, + inout [ 71:0] hps_ddr_dq, + + // hps-ethernet + + input [ 0:0] hps_emac_rx_clk, + input [ 0:0] hps_emac_rx_ctl, + input [ 3:0] hps_emac_rx, + output [ 0:0] hps_emac_tx_clk, + output [ 0:0] hps_emac_tx_ctl, + output [ 3:0] hps_emac_tx, + output [ 0:0] hps_emac_mdc, + inout [ 0:0] hps_emac_mdio, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_data, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // fpga-gpio motherboard (led/dpsw/button) + + input [ 3:0] fpga_gpio_dpsw, + input [ 3:0] fpga_gpio_btn, + output [ 3:0] fpga_gpio_led, + + // sdmmc-interface + + output hps_sdmmc_clk, + inout hps_sdmmc_cmd, + inout [ 3:0] hps_sdmmc_data, + + // jtag-interface + + input hps_jtag_tck, + input hps_jtag_tms, + output hps_jtag_tdo, + input hps_jtag_tdi, + + // hps-OOBE daughter card peripherals + + inout hps_gpio_eth_irq, + inout hps_gpio_usb_oci, + inout [ 1:0] hps_gpio_btn, + inout [ 2:0] hps_gpio_led, + + // adrv9009-interface + + input ref_clk0, + input ref_clk1, + input [ 3:0] rx_serial_data, + output [ 3:0] tx_serial_data, + output rx_sync, + output rx_os_sync, + input tx_sync, + input tx_sync_1, + input sysref, + + output ad9528_reset_b, + output ad9528_sysref_req, + output adrv9009_tx1_enable, + output adrv9009_tx2_enable, + output adrv9009_rx1_enable, + output adrv9009_rx2_enable, + output adrv9009_test, + output adrv9009_reset_b, + input adrv9009_gpint, + + inout [ 18:0] adrv9009_gpio, + + output spi_csn_ad9528, + output spi_csn_adrv9009, + output spi_clk, + output spi_mosi, + input spi_miso + +); + + // internal signals + + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire [ 7:0] spi_csn_s; + wire dac_fifo_bypass; + wire ninit_done_s; + wire h2f_reset_s; + wire sys_resetn_s; + + // motherboard-gpio + + assign gpio_i[3:0] = fpga_gpio_dpsw; + assign gpio_i[7:4] = fpga_gpio_btn; + assign gpio_i[31:11] = gpio_o[31:11]; + assign fpga_gpio_led = gpio_o[10:8]; + + // assignments + + assign spi_csn_ad9528 = spi_csn_s[0]; + assign spi_csn_adrv9009 = spi_csn_s[1]; + + // gpio (adrv9009) + + assign gpio_i[50:32] = gpio_o[50:32]; + assign gpio_i[51:51] = adrv9009_gpint; + assign gpio_i[59:52] = gpio_o[59:52]; + assign gpio_i[63:60] = gpio_o[63:60]; + + assign dac_fifo_bypass = gpio_o[60]; + assign ad9528_reset_b = gpio_o[59]; + assign ad9528_sysref_req = gpio_o[58]; + assign adrv9009_tx1_enable = gpio_o[57]; + assign adrv9009_tx2_enable = gpio_o[56]; + assign adrv9009_rx1_enable = gpio_o[55]; + assign adrv9009_rx2_enable = gpio_o[54]; + assign adrv9009_test = gpio_o[53]; + assign adrv9009_reset_b = gpio_o[52]; + + // system reset is a combination of external reset, HPS reset and S10 init + // done reset + assign sys_resetn_s = fpga_resetn & ~h2f_reset_s & ~ninit_done_s; + + // instantiations + + system_bd i_system_bd ( + .sys_clk_clk ( sys_clk ), + .sys_rst_reset_n ( sys_resetn_s ), + .h2f_reset_reset ( h2f_reset_s ), + .rst_ninit_done_ninit_done ( ninit_done_s ), + .sys_gpio_bd_in_port ( gpio_i[31: 0] ), + .sys_gpio_bd_out_port ( gpio_o[31: 0] ), + .sys_gpio_in_export ( gpio_i[63:32] ), + .sys_gpio_out_export ( gpio_o[63:32] ), + .sys_hps_io_hps_io_phery_emac0_TX_CLK ( hps_emac_tx_clk ), + .sys_hps_io_hps_io_phery_emac0_TXD0 ( hps_emac_tx[0] ), + .sys_hps_io_hps_io_phery_emac0_TXD1 ( hps_emac_tx[1] ), + .sys_hps_io_hps_io_phery_emac0_TXD2 ( hps_emac_tx[2] ), + .sys_hps_io_hps_io_phery_emac0_TXD3 ( hps_emac_tx[3] ), + .sys_hps_io_hps_io_phery_emac0_RX_CTL ( hps_emac_rx_ctl ), + .sys_hps_io_hps_io_phery_emac0_TX_CTL ( hps_emac_tx_ctl ), + .sys_hps_io_hps_io_phery_emac0_RX_CLK ( hps_emac_rx_clk ), + .sys_hps_io_hps_io_phery_emac0_RXD0 ( hps_emac_rx[0] ), + .sys_hps_io_hps_io_phery_emac0_RXD1 ( hps_emac_rx[1] ), + .sys_hps_io_hps_io_phery_emac0_RXD2 ( hps_emac_rx[2] ), + .sys_hps_io_hps_io_phery_emac0_RXD3 ( hps_emac_rx[3] ), + .sys_hps_io_hps_io_phery_emac0_MDIO ( hps_emac_mdio ), + .sys_hps_io_hps_io_phery_emac0_MDC ( hps_emac_mdc ), + .sys_hps_io_hps_io_phery_sdmmc_CMD ( hps_sdmmc_cmd ), + .sys_hps_io_hps_io_phery_sdmmc_D0 ( hps_sdmmc_data[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 ( hps_sdmmc_data[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 ( hps_sdmmc_data[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 ( hps_sdmmc_data[3]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK ( hps_sdmmc_clk ), + .sys_hps_io_hps_io_phery_usb0_DATA0 ( hps_usb_data[0] ), + .sys_hps_io_hps_io_phery_usb0_DATA1 ( hps_usb_data[1] ), + .sys_hps_io_hps_io_phery_usb0_DATA2 ( hps_usb_data[2] ), + .sys_hps_io_hps_io_phery_usb0_DATA3 ( hps_usb_data[3] ), + .sys_hps_io_hps_io_phery_usb0_DATA4 ( hps_usb_data[4] ), + .sys_hps_io_hps_io_phery_usb0_DATA5 ( hps_usb_data[5] ), + .sys_hps_io_hps_io_phery_usb0_DATA6 ( hps_usb_data[6] ), + .sys_hps_io_hps_io_phery_usb0_DATA7 ( hps_usb_data[7] ), + .sys_hps_io_hps_io_phery_usb0_CLK ( hps_usb_clk ), + .sys_hps_io_hps_io_phery_usb0_STP ( hps_usb_stp ), + .sys_hps_io_hps_io_phery_usb0_DIR ( hps_usb_dir ), + .sys_hps_io_hps_io_phery_usb0_NXT ( hps_usb_nxt ), + .sys_hps_io_hps_io_phery_uart0_RX ( hps_uart_rx ), + .sys_hps_io_hps_io_phery_uart0_TX ( hps_uart_tx ), + .sys_hps_io_hps_io_phery_i2c1_SDA ( hps_i2c_sda ), + .sys_hps_io_hps_io_phery_i2c1_SCL ( hps_i2c_scl ), + .sys_hps_io_hps_io_gpio_gpio1_io0 ( hps_gpio_eth_irq ), + .sys_hps_io_hps_io_gpio_gpio1_io1 ( hps_gpio_usb_oci ), + .sys_hps_io_hps_io_gpio_gpio1_io4 ( hps_gpio_btn[0] ), + .sys_hps_io_hps_io_gpio_gpio1_io5 ( hps_gpio_btn[1] ), + .sys_hps_io_hps_io_jtag_tck ( hps_jtag_tck ), + .sys_hps_io_hps_io_jtag_tms ( hps_jtag_tms ), + .sys_hps_io_hps_io_jtag_tdo ( hps_jtag_tdo ), + .sys_hps_io_hps_io_jtag_tdi ( hps_jtag_tdi ), + .sys_hps_io_hps_io_hps_ocs_clk ( hps_ref_clk ), + .sys_hps_io_hps_io_gpio_gpio1_io19 ( hps_gpio_led[1] ), + .sys_hps_io_hps_io_gpio_gpio1_io20 ( hps_gpio_led[0] ), + .sys_hps_io_hps_io_gpio_gpio1_io21 ( hps_gpio_led[2] ), + .sys_hps_ddr_ref_clk_clk ( hps_ddr_ref_clk ), + .sys_hps_ddr_oct_oct_rzqin ( hps_ddr_rzq ), + .sys_hps_ddr_mem_ck ( hps_ddr_ck ), + .sys_hps_ddr_mem_ck_n ( hps_ddr_ck_n ), + .sys_hps_ddr_mem_a ( hps_ddr_a ), + .sys_hps_ddr_mem_act_n ( hps_ddr_act_n ), + .sys_hps_ddr_mem_ba ( hps_ddr_ba ), + .sys_hps_ddr_mem_bg ( hps_ddr_bg ), + .sys_hps_ddr_mem_cke ( hps_ddr_cke ), + .sys_hps_ddr_mem_cs_n ( hps_ddr_cs_n ), + .sys_hps_ddr_mem_odt ( hps_ddr_odt ), + .sys_hps_ddr_mem_reset_n ( hps_ddr_reset_n ), + .sys_hps_ddr_mem_par ( hps_ddr_par ), + .sys_hps_ddr_mem_alert_n ( hps_ddr_alert_n ), + .sys_hps_ddr_mem_dqs ( hps_ddr_dqs_p ), + .sys_hps_ddr_mem_dqs_n ( hps_ddr_dqs_n ), + .sys_hps_ddr_mem_dq ( hps_ddr_dq ), + .sys_hps_ddr_mem_dbi_n ( hps_ddr_dbi_n ), + .sys_spi_MISO ( spi_miso ), + .sys_spi_MOSI ( spi_mosi ), + .sys_spi_SCLK ( spi_clk ), + .sys_spi_SS_n ( spi_csn_s ), + .adrv9009_gpio_export ( adrv9009_gpio ), + .tx_serial_data_tx_serial_data ( tx_serial_data ), + .tx_fifo_bypass_bypass ( dac_fifo_bypass ), + .tx_ref_clk_clk ( ref_clk1 ), + .tx_sync_export ( tx_sync ), + .tx_sysref_export ( sysref ), + .rx_serial_data_rx_serial_data ( rx_serial_data[1:0] ), + .rx_os_serial_data_rx_serial_data ( rx_serial_data[3:2] ), + .rx_os_ref_clk_clk ( ref_clk1 ), + .rx_os_sync_export ( rx_os_sync ), + .rx_os_sysref_export ( sysref ), + .rx_ref_clk_clk ( ref_clk1 ), + .rx_sync_export ( rx_sync ), + .rx_sysref_export ( sysref ) + ); + +endmodule + +// *************************************************************************** +// ***************************************************************************