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ad9081_fmca_ebz: Integrate the new TDD in project

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Ionut Podgoreanu 2022-08-30 11:40:26 +01:00 committed by podgori
parent ef278e1c88
commit 5b95b6ce1f
10 changed files with 58 additions and 40 deletions
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43
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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@ -17,6 +17,7 @@ if {![info exists ADI_PHY_SEL]} {
source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
# Common parameter for TX and RX
set JESD_MODE $ad_project_params(JESD_MODE)
@ -508,27 +509,39 @@ ad_connect upack_reset_sources/dout upack_rst_logic/op1
ad_connect upack_rst_logic/res util_mxfe_upack/reset
if {$TDD_SUPPORT} {
ad_ip_instance util_tdd_sync tdd_sync_0
ad_connect tx_device_clk tdd_sync_0/clk
ad_connect tx_device_clk_rstgen/peripheral_aresetn tdd_sync_0/rstn
ad_connect tdd_sync_0/sync_in GND
ad_connect tdd_sync_0/sync_mode GND
ad_ip_parameter tdd_sync_0 CONFIG.TDD_SYNC_PERIOD 250000000; # More or less 1 PPS ;)
set TDD_CHANNEL_CNT $ad_project_params(TDD_CHANNEL_CNT)
set TDD_DEFAULT_POL [ expr { [info exists ad_project_params(TDD_DEFAULT_POL)] \
? $ad_project_params(TDD_DEFAULT_POL) : 0 } ]
set TDD_REG_WIDTH [ expr { [info exists ad_project_params(TDD_REG_WIDTH)] \
? $ad_project_params(TDD_REG_WIDTH) : 32 } ]
set TDD_BURST_WIDTH [ expr { [info exists ad_project_params(TDD_BURST_WIDTH)] \
? $ad_project_params(TDD_BURST_WIDTH) : 32 } ]
set TDD_SYNC_WIDTH [ expr { [info exists ad_project_params(TDD_SYNC_WIDTH)] \
? $ad_project_params(TDD_SYNC_WIDTH) : 64 } ]
set TDD_SYNC_INT $ad_project_params(TDD_SYNC_INT)
set TDD_SYNC_EXT $ad_project_params(TDD_SYNC_EXT)
set TDD_SYNC_EXT_CDC $ad_project_params(TDD_SYNC_EXT_CDC)
ad_tdd_gen_create axi_tdd_0 $TDD_CHANNEL_CNT \
$TDD_DEFAULT_POL \
$TDD_REG_WIDTH \
$TDD_BURST_WIDTH \
$TDD_SYNC_WIDTH \
$TDD_SYNC_INT \
$TDD_SYNC_EXT \
$TDD_SYNC_EXT_CDC
ad_ip_instance axi_tdd axi_tdd_0 [list ASYNC_TDD_SYNC 0]
ad_connect tx_device_clk axi_tdd_0/clk
ad_connect tx_device_clk_rstgen/peripheral_reset axi_tdd_0/rst
ad_connect tx_device_clk_rstgen/peripheral_aresetn axi_tdd_0/resetn
ad_connect $sys_cpu_clk axi_tdd_0/s_axi_aclk
ad_connect $sys_cpu_resetn axi_tdd_0/s_axi_aresetn
ad_connect axi_tdd_0/sync_in GND
ad_cpu_interconnect 0x7c460000 axi_tdd_0
ad_connect tdd_sync_0/sync_out axi_tdd_0/tdd_sync
delete_bd_objs [get_bd_nets mxfe_adc_fifo_dma_wr]
ad_connect axi_tdd_0/tdd_tx_valid $dac_data_offload_name/sync_ext
ad_connect axi_tdd_0/tdd_rx_valid $adc_data_offload_name/sync_ext
ad_connect axi_tdd_0/tdd_channel_0 $dac_data_offload_name/sync_ext
ad_connect axi_tdd_0/tdd_channel_1 $adc_data_offload_name/sync_ext
} else {
ad_connect GND $dac_data_offload_name/sync_ext

2
projects/ad9081_fmca_ebz/vck190/Makefile
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@ -20,6 +20,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
@ -40,7 +41,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad9081_fmca_ebz/vcu118/Makefile
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@ -19,6 +19,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
@ -39,7 +40,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad9081_fmca_ebz/vcu128/Makefile
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@ -17,6 +17,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
@ -35,7 +36,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad9081_fmca_ebz/zc706/Makefile
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@ -19,6 +19,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
@ -42,7 +43,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad9081_fmca_ebz/zcu102/Makefile
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@ -19,6 +19,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
@ -39,7 +40,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

5
projects/ad9081_fmca_ebz/zcu102/system_project.tcl
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@ -44,6 +44,11 @@ adi_project ad9081_fmca_ebz_zcu102 0 [list \
TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \
TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \
SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \
TDD_CHANNEL_CNT [get_env_param TDD_CHANNEL_CNT 2 ] \
TDD_SYNC_WIDTH [get_env_param TDD_SYNC_WIDTH 32 ] \
TDD_SYNC_INT [get_env_param TDD_SYNC_INT 1 ] \
TDD_SYNC_EXT [get_env_param TDD_SYNC_EXT 0 ] \
TDD_SYNC_EXT_CDC [get_env_param TDD_SYNC_EXT_CDC 0 ] \
]
adi_project_files ad9081_fmca_ebz_zcu102 [list \

2
projects/ad9082_fmca_ebz/vcu118/Makefile
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@ -22,6 +22,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
@ -42,7 +43,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad9082_fmca_ebz/zc706/Makefile
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@ -22,6 +22,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
@ -45,7 +46,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad9082_fmca_ebz/zcu102/Makefile
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@ -22,6 +22,7 @@ M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
@ -42,7 +43,6 @@ LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr