common/ad_mux: Pipelined mux, rtl and TB
Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter Use EN_REG to add a register at the output of the small muxes to help timing closure.main
Laszlo Nagy
Laszlo Nagy
parent
1c71815bd7
commit
5c561665b0
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@ -0,0 +1,118 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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||||
//
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||||
// The user should read each of these license terms, and understand the
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||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
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||||
// of this file, are permitted under one of the following two license terms:
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||||
//
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||||
// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// Constraints : CH_CNT must be power of 2
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// Build a large mux from smaller ones defined by the MUX_SZ parameter
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// Use EN_REG to add a register at the output of the small muxes to help
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// timing closure.
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module ad_mux #(
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parameter CH_W = 16, // Width of input channel
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parameter CH_CNT = 64, // Number of input channels
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parameter REQ_MUX_SZ = 8, // Size of mux which acts as a building block
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parameter EN_REG = 1, // Enable register at output of each mux
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parameter DW = CH_W*CH_CNT
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) (
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input clk,
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input [DW-1:0] data_in,
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input [$clog2(CH_CNT)-1:0] ch_sel,
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output [CH_W-1:0] data_out
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);
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localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
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localparam CLOG2_CH_CNT = $clog2(CH_CNT);
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localparam CLOG2_MUX_SZ = $clog2(MUX_SZ);
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localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ);
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wire [NUM_STAGES*DW+CH_W-1:0] mux_in;
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wire [NUM_STAGES*CLOG2_CH_CNT-1:0] ch_sel_pln;
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assign mux_in[DW-1:0] = data_in;
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assign ch_sel_pln[CLOG2_CH_CNT-1:0] = ch_sel;
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genvar i;
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genvar j;
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generate
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for (i = 0; i < NUM_STAGES; i = i + 1) begin: g_stage
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wire [CLOG2_CH_CNT-1:0] ch_sel_cur;
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assign ch_sel_cur = ch_sel_pln[i*CLOG2_CH_CNT+:CLOG2_CH_CNT];
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wire [CLOG2_MUX_SZ-1:0] ch_sel_w;
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assign ch_sel_w = ch_sel_cur >> i*CLOG2_MUX_SZ;
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if (EN_REG) begin
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reg [CLOG2_CH_CNT-1:0] ch_sel_d;
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always @(posedge clk) begin
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ch_sel_d <= ch_sel_cur;
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end
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if (i<NUM_STAGES-1) begin
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assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_d;
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end
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end else begin
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if (i<NUM_STAGES-1) begin
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assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_cur;
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end
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end
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for (j = 0; j < MUX_SZ**(NUM_STAGES-i); j = j + MUX_SZ) begin: g_mux
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ad_mux_core #(
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.CH_W (CH_W),
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.CH_CNT (MUX_SZ),
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.EN_REG (EN_REG)
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) i_mux (
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.clk (clk),
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.data_in (mux_in[i*DW+j*CH_W+:MUX_SZ*CH_W]),
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.ch_sel (ch_sel_w),
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.data_out (mux_in[(i+1)*DW+(j/MUX_SZ)*CH_W+:CH_W])
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);
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end
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end
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endgenerate
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assign data_out = mux_in[NUM_STAGES*DW+:CH_W];
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endmodule
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@ -0,0 +1,66 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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||||
// A PARTICULAR PURPOSE.
|
||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_mux_core #(
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parameter CH_W = 16,
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parameter CH_CNT = 8,
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parameter EN_REG = 0
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) (
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input clk,
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input [CH_W*CH_CNT-1:0] data_in,
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input [$clog2(CH_CNT)-1:0] ch_sel,
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output [CH_W-1:0] data_out
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);
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wire [CH_W-1:0] data_out_loc;
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assign data_out_loc = data_in >> CH_W*ch_sel;
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generate if (EN_REG) begin
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reg [CH_W-1:0] data_out_reg;
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always @(posedge clk) begin
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data_out_reg <= data_out_loc;
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end
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assign data_out = data_out_reg;
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end else begin
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assign data_out = data_out_loc;
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end
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endgenerate
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endmodule
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#!/bin/bash
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SOURCE="ad_mux_tb.v"
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SOURCE+=" ../ad_mux.v"
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SOURCE+=" ../ad_mux_core.v"
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cd `dirname $0`
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source run_tb.sh
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@ -0,0 +1,71 @@
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`timescale 1ns/100ps
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module ad_mux_tb;
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parameter VCD_FILE = "ad_mux_tb.vcd";
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parameter CH_W = 16; // Width of input channel
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parameter CH_CNT = 64; // Number of input channels
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parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block
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parameter EN_REG = 1; // Enable register at output of each mux
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localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
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localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ);
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localparam DW = CH_W*CH_CNT;
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`include "tb_base.v"
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reg [CH_W*CH_CNT-1:0] data_in = 'h0;
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reg [$clog2(CH_CNT)-1:0] ch_sel = 'h0;
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wire [CH_W-1:0] data_out;
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ad_mux #(
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.CH_W(CH_W),
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.CH_CNT(CH_CNT),
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.REQ_MUX_SZ(REQ_MUX_SZ),
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.EN_REG(EN_REG)
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) DUT (
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.clk(clk),
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.data_in(data_in),
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.ch_sel(ch_sel),
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.data_out(data_out)
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);
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wire [CH_W-1:0] ref_data;
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generate
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if (EN_REG) begin
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integer ii;
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reg [CH_W*CH_CNT-1:0] mux_pln [1:NUM_STAGES];
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always @(posedge clk) begin
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mux_pln[1] <= data_in >> ch_sel*CH_W;
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for (ii=2; ii<=NUM_STAGES; ii=ii+1) begin
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mux_pln[ii] <= mux_pln[ii-1];
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end
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end
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assign ref_data = mux_pln[NUM_STAGES];
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end else begin
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assign ref_data = data_in >> ch_sel*CH_W;
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end
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endgenerate
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integer i;
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initial begin
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for (i=0; i<CH_W*CH_CNT/8; i=i+1) begin
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data_in[i*8+:8] = i[7:0];
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end
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for (i=0; i<CH_CNT; i=i+1) begin
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@(posedge clk);
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ch_sel <= ch_sel + 1;
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end
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end
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wire mismatch;
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assign mismatch = ref_data !== data_out;
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always @(posedge clk) begin
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if (mismatch) begin
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failed <= 1'b1;
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end
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end
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endmodule
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@ -0,0 +1,24 @@
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NAME=`basename $0`
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case "$SIMULATOR" in
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modelsim)
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# ModelSim flow
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vlib work
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vlog ${SOURCE} || exit 1
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vsim ${NAME} -do "add log /* -r; run -a" -gui || exit 1
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;;
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xsim)
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# xsim flow
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xvlog -log ${NAME}_xvlog.log --sourcelibdir . ${SOURCE}
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xelab -log ${NAME}_xelab.log -debug all ${NAME}
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xsim work.${NAME} -R
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;;
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*)
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mkdir -p run
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mkdir -p vcd
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iverilog ${SOURCE} -o run/run_${NAME} $1 || exit 1
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cd vcd
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../run/run_${NAME}
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;;
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esac
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@ -0,0 +1,86 @@
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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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reg clk = 1'b0;
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reg [3:0] reset_shift = 4'b1111;
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reg trigger_reset = 1'b0;
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wire reset;
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reg failed = 1'b0;
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initial
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begin
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$dumpfile (VCD_FILE);
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$dumpvars;
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`ifdef TIMEOUT
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#`TIMEOUT
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`else
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#100000
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`endif
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if (failed == 1'b0)
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$display("SUCCESS");
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else
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$display("FAILED");
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$finish;
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end
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always @(*) #10 clk <= ~clk;
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always @(posedge clk) begin
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if (trigger_reset == 1'b1) begin
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reset_shift <= 3'b111;
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end else begin
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reset_shift <= {reset_shift[2:0],1'b0};
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end
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end
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assign reset = reset_shift[3];
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task do_trigger_reset;
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begin
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@(posedge clk) trigger_reset <= 1'b1;
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@(posedge clk) trigger_reset <= 1'b0;
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end
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endtask
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