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library/jesd204: Add support for a gearbox ratio in which the TPL width is smaller than the PHY interface

main
Ionut Podgoreanu 2022-08-17 09:23:44 +01:00 committed by Laszlo Nagy
parent 567be16bf6
commit 5c86c15ff3
9 changed files with 201 additions and 87 deletions
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1
library/jesd204/jesd204_rx/Makefile
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@ -7,6 +7,7 @@
LIBRARY_NAME := jesd204_rx
GENERIC_DEPS += ../../common/ad_pack.v
GENERIC_DEPS += ../../common/ad_upack.v
GENERIC_DEPS += align_mux.v
GENERIC_DEPS += elastic_buffer.v
GENERIC_DEPS += jesd204_ilas_monitor.v

124
library/jesd204/jesd204_rx/elastic_buffer.v
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@ -58,7 +58,7 @@ module elastic_buffer #(
input [IWIDTH-1:0] wr_data,
output reg [OWIDTH-1:0] rd_data,
output [OWIDTH-1:0] rd_data,
input ready_n,
input do_release_n
@ -77,45 +77,103 @@ module elastic_buffer #(
reg [ADDR_WIDTH:0] wr_addr = 'h00;
reg [ADDR_WIDTH:0] rd_addr = 'h00;
(* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:SIZE - 1];
reg mem_rd_valid = 'b0;
reg [WIDTH-1:0] mem_rd_data;
wire mem_wr;
wire [WIDTH-1:0] mem_wr_data;
wire unpacker_ready;
generate if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin
ad_pack #(
generate if ((OWIDTH < IWIDTH) && ASYNC_CLK) begin
assign mem_wr = 1'b1;
always @(posedge clk) begin
if (ready_n) begin
wr_addr <= 'h00;
end else if (mem_wr) begin
wr_addr <= wr_addr + 1;
end
end
always @(posedge clk) begin
if (mem_wr) begin
mem[wr_addr] <= wr_data;
end
end
assign mem_rd_en = ~do_release_n & unpacker_ready;
always @(posedge device_clk) begin
if (mem_rd_en) begin
mem_rd_data <= mem[rd_addr];
end
mem_rd_valid <= mem_rd_en;
end
always @(posedge device_clk) begin
if (do_release_n) begin
rd_addr <= 'b0;
end else if (mem_rd_en) begin
rd_addr <= rd_addr + 1;
end
end
ad_upack #(
.I_W(IWIDTH/8),
.O_W(OWIDTH/8),
.UNIT_W(8)
) i_ad_pack (
.clk(clk),
.reset(ready_n),
.idata(wr_data),
.ivalid(1'b1),
.UNIT_W(8),
.O_REG(0)
) i_ad_upack (
.clk(device_clk),
.reset(do_release_n),
.idata(mem_rd_data),
.ivalid(mem_rd_valid),
.iready(unpacker_ready),
.odata(mem_wr_data),
.ovalid(mem_wr));
end else begin
assign mem_wr = 1'b1;
assign mem_wr_data = wr_data;
end
.odata(rd_data),
.ovalid());
end else begin
if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin
ad_pack #(
.I_W(IWIDTH/8),
.O_W(OWIDTH/8),
.UNIT_W(8)
) i_ad_pack (
.clk(clk),
.reset(ready_n),
.idata(wr_data),
.ivalid(1'b1),
.odata(mem_wr_data),
.ovalid(mem_wr));
end else begin
assign mem_wr = 1'b1;
assign mem_wr_data = wr_data;
end
always @(posedge clk) begin
if (ready_n == 1'b1) begin
wr_addr <= 'h00;
end else if (mem_wr) begin
mem[wr_addr] <= mem_wr_data;
wr_addr <= wr_addr + 1'b1;
end
end
always @(posedge device_clk) begin
if (do_release_n == 1'b1) begin
rd_addr <= 'h00;
end else begin
rd_addr <= rd_addr + 1'b1;
mem_rd_data <= mem[rd_addr];
end
end
assign rd_data = mem_rd_data;
end
endgenerate
always @(posedge clk) begin
if (ready_n == 1'b1) begin
wr_addr <= 'h00;
end else if (mem_wr) begin
mem[wr_addr] <= mem_wr_data;
wr_addr <= wr_addr + 1'b1;
end
end
always @(posedge device_clk) begin
if (do_release_n == 1'b1) begin
rd_addr <= 'h00;
end else begin
rd_addr <= rd_addr + 1'b1;
rd_data <= mem[rd_addr];
end
end
endmodule

1
library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
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@ -75,6 +75,7 @@ ad_ip_files jesd204_rx [list \
$ad_hdl_dir/library/util_cdc/sync_event.v \
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
../../common/ad_pack.v \
../../common/ad_upack.v \
]
# parameters

1
library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
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@ -65,6 +65,7 @@ adi_ip_files jesd204_rx [list \
"jesd204_rx_ooc.ttcl" \
"jesd204_rx.v" \
"../../common/ad_pack.v" \
"../../common/ad_upack.v" \
"bd/bd.tcl"
]

1
library/jesd204/jesd204_tx/Makefile
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@ -6,6 +6,7 @@
LIBRARY_NAME := jesd204_tx
GENERIC_DEPS += ../../common/ad_pack.v
GENERIC_DEPS += ../../common/ad_upack.v
GENERIC_DEPS += jesd204_tx.v
GENERIC_DEPS += jesd204_tx_ctrl.v

7
library/jesd204/jesd204_tx/jesd204_tx.v
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@ -208,7 +208,6 @@ module jesd204_tx #(
if (ASYNC_CLK) begin : dual_lmfc_mode
reg link_lmfc_reset = 1'b1;
reg device_lmfc_edge_d1 = 1'b0;
reg device_tx_ready = 1'b0;
jesd204_lmfc #(
@ -272,14 +271,10 @@ module jesd204_tx #(
.device_clk(device_clk),
.device_reset(device_reset),
.device_data(tx_data),
.device_lmfc_edge(device_lmfc_edge_d1),
.device_lmfc_edge(device_lmfc_edge),
.link_data(gearbox_data),
.output_ready(tx_ready_nx));
always @(posedge device_clk) begin
device_lmfc_edge_d1 <= device_lmfc_edge;
end
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK(ASYNC_CLK)

151
library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
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@ -64,21 +64,26 @@ module jesd204_tx_gearbox #(
input output_ready
);
localparam MEM_W = IN_DATA_PATH_WIDTH*8*NUM_LANES;
localparam MEM_W = (OUT_DATA_PATH_WIDTH <= IN_DATA_PATH_WIDTH) ?
IN_DATA_PATH_WIDTH*8*NUM_LANES :
OUT_DATA_PATH_WIDTH*8*NUM_LANES;
localparam D_LOG2 = $clog2(DEPTH);
reg [MEM_W-1:0] mem [0:DEPTH-1];
reg [D_LOG2-1:0] in_addr ='h00;
reg [D_LOG2-1:0] out_addr = 'b0;
reg mem_rd_valid = 'b0;
reg [MEM_W-1:0] mem_rd_data;
reg [MEM_W-1:0] mem_rd_data = 'b0;
wire mem_wr_en = 1'b1;
wire mem_rd_en;
wire mem_wr_en;
wire [D_LOG2-1:0] in_out_addr;
wire [D_LOG2-1:0] out_in_addr;
wire [NUM_LANES-1:0] unpacker_ready;
wire [MEM_W-1:0] mem_wr_data;
wire [NUM_LANES-1:0] data_ready;
wire output_ready_sync;
wire addr_reset;
wire packer_reset;
sync_bits i_sync_ready (
.in_bits(output_ready),
@ -86,54 +91,104 @@ module jesd204_tx_gearbox #(
.out_clk(device_clk),
.out_bits(output_ready_sync));
always @(posedge device_clk) begin
if (device_lmfc_edge & ~output_ready_sync) begin
in_addr <= 'h01;
end else if (mem_wr_en) begin
in_addr <= in_addr + 1;
end
end
always @(posedge device_clk) begin
if (mem_wr_en) begin
mem[in_addr] <= device_data;
end
end
assign mem_rd_en = output_ready&unpacker_ready[0];
always @(posedge link_clk) begin
if (mem_rd_en) begin
mem_rd_data <= mem[out_addr];
end
mem_rd_valid <= mem_rd_en;
end
always @(posedge link_clk) begin
if (reset) begin
out_addr <= 'b0;
end else if (mem_rd_en) begin
out_addr <= out_addr + 1;
end
end
assign addr_reset = device_lmfc_edge & ~output_ready_sync;
assign packer_reset = device_reset | addr_reset;
genvar i;
generate for (i = 0; i < NUM_LANES; i=i+1) begin: unpacker
generate if (OUT_DATA_PATH_WIDTH < IN_DATA_PATH_WIDTH) begin
ad_upack #(
.I_W(IN_DATA_PATH_WIDTH),
.O_W(OUT_DATA_PATH_WIDTH),
.UNIT_W(8),
.O_REG(0)
) i_ad_upack (
.clk(link_clk),
.reset(reset),
.idata(mem_rd_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]),
.ivalid(mem_rd_valid),
.iready(unpacker_ready[i]),
assign mem_wr_en = 1'b1;
.odata(link_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]),
.ovalid());
always @(posedge device_clk) begin
if (addr_reset) begin
in_addr <= 'h00;
end else if (mem_wr_en) begin
in_addr <= in_addr + 1;
end
end
always @(posedge device_clk) begin
if (mem_wr_en) begin
mem[in_addr] <= device_data;
end
end
assign mem_rd_en = output_ready&data_ready[0];
always @(posedge link_clk) begin
if (mem_rd_en) begin
mem_rd_data <= mem[out_addr];
end
mem_rd_valid <= mem_rd_en;
end
always @(posedge link_clk) begin
if (reset) begin
out_addr <= 'b0;
end else if (mem_rd_en) begin
out_addr <= out_addr + 1;
end
end
for (i = 0; i < NUM_LANES; i=i+1) begin: unpacker
ad_upack #(
.I_W(IN_DATA_PATH_WIDTH),
.O_W(OUT_DATA_PATH_WIDTH),
.UNIT_W(8),
.O_REG(0)
) i_ad_upack (
.clk(link_clk),
.reset(reset),
.idata(mem_rd_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]),
.ivalid(mem_rd_valid),
.iready(data_ready[i]),
.odata(link_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]),
.ovalid());
end
end else begin
if (OUT_DATA_PATH_WIDTH > IN_DATA_PATH_WIDTH) begin
for (i = 0; i < NUM_LANES; i=i+1) begin: packer
ad_pack #(
.I_W(IN_DATA_PATH_WIDTH),
.O_W(OUT_DATA_PATH_WIDTH),
.UNIT_W(8),
.O_REG(0)
) i_ad_pack (
.clk(device_clk),
.reset(packer_reset),
.idata(device_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]),
.ivalid(1'b1),
.odata(mem_wr_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]),
.ovalid(data_ready[i]));
end
assign mem_wr_en = data_ready[0];
end else begin
assign mem_wr_en = 1'b1;
assign mem_wr_data = device_data;
end
always @(posedge device_clk) begin
if (addr_reset) begin
in_addr <= 'h00;
end else if (mem_wr_en) begin
mem[in_addr] <= mem_wr_data;
in_addr <= in_addr + 1'b1;
end
end
always @(posedge link_clk) begin
if (output_ready == 1'b0) begin
out_addr <= 'h00;
end else begin
out_addr <= out_addr + 1'b1;
mem_rd_data <= mem[out_addr];
end
end
assign link_data = mem_rd_data;
end
endgenerate

1
library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
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@ -68,6 +68,7 @@ ad_ip_files jesd204_tx [list \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/sync_event.v \
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
$ad_hdl_dir/library/common/ad_pack.v \
$ad_hdl_dir/library/common/ad_upack.v \
]

1
library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
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@ -56,6 +56,7 @@ adi_ip_files jesd204_tx [list \
"jesd204_tx_ctrl.v" \
"jesd204_tx_constr.ttcl" \
"jesd204_tx_ooc.ttcl" \
"../../common/ad_pack.v" \
"../../common/ad_upack.v" \
"jesd204_tx.v" \
"bd/bd.tcl"