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version_upgrade: Common ZC702 get an upgrade to 2016.2 

Xilinx IP Clock Wizard updated to version 5.3
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Istvan Csomortani 2016-08-26 10:20:04 +03:00
parent cd0c981b50
commit 5cc2ab37a5
1 changed files with 1 additions and 1 deletions
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projects/common/zc702/zc702_system_bd.tcl
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@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
# audio peripherals # audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen