axi_clkgen: Added phase related parameters
parent
6e549171f0
commit
5cf45b2978
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@ -76,7 +76,9 @@ module axi_clkgen (
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parameter VCO_DIV = 11;
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parameter VCO_MUL = 49;
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parameter CLK0_DIV = 6;
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parameter CLK0_PHASE = 0.000;
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parameter CLK1_DIV = 6;
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parameter CLK1_PHASE = 0.000;
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// clocks
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@ -200,7 +202,9 @@ module axi_clkgen (
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.MMCM_VCO_DIV (VCO_DIV),
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.MMCM_VCO_MUL (VCO_MUL),
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.MMCM_CLK0_DIV (CLK0_DIV),
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.MMCM_CLK1_DIV (CLK1_DIV))
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.MMCM_CLK0_PHASE (CLK0_PHASE),
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.MMCM_CLK1_DIV (CLK1_DIV),
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.MMCM_CLK1_PHASE (CLK1_PHASE))
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i_mmcm_drp (
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.clk (clk),
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.clk2 (clk2),
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@ -72,7 +72,9 @@ module ad_mmcm_drp (
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parameter MMCM_VCO_DIV = 6;
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parameter MMCM_VCO_MUL = 12.000;
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parameter MMCM_CLK0_DIV = 2.000;
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parameter MMCM_CLK0_PHASE = 0.000 ;
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parameter MMCM_CLK1_DIV = 6;
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parameter MMCM_CLK1_PHASE = 0.000;
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// clocks
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@ -143,11 +145,11 @@ module ad_mmcm_drp (
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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@ -200,11 +202,11 @@ module ad_mmcm_drp (
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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