From 5d0e08d92e41eb7e2cc8062364b17513c62ce290 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 17 Aug 2016 10:36:19 -0400 Subject: [PATCH] common/vc707- 2016.2 version --- projects/common/vc707/vc707_system_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 37c94841f..113d45541 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -49,7 +49,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] # instance: microblaze - processor -set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb] +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb] set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb @@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl