jesd204_tx: Remove duplicated file
The ilas_cfg_static.v is part of the jesd204_tx_static_config module. Somehow a copy of that file made it into the jesd204_tx module where it is completely unused. Remove the duplicated file. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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module jesd204_ilas_config_static #(
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parameter DID = 8'h00,
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parameter BID = 4'h0,
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parameter L = 5'h3,
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parameter SCR = 1'b1,
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parameter F = 8'h01,
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parameter K = 5'h1f,
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parameter M = 8'h3,
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parameter N = 5'h0f,
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parameter CS = 2'h0,
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parameter NP = 5'h0f,
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parameter SUBCLASSV = 3'h1,
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parameter S = 5'h00,
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parameter JESDV = 3'h1,
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parameter CF = 5'h00,
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parameter HD = 1'b1,
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parameter NUM_LANES = 1
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) (
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input clk,
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input [1:0] ilas_config_addr,
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input ilas_config_rd,
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output reg [32*NUM_LANES-1:0] ilas_config_data
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);
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wire [31:0] ilas_mem[0:3];
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assign ilas_mem[0][15:0] = 8'h00;
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assign ilas_mem[0][23:16] = DID; // DID
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assign ilas_mem[0][27:24] = BID; // BID
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assign ilas_mem[0][31:28] = 4'h0; // ADJCNT
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assign ilas_mem[1][4:0] = 5'h00; // LID
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assign ilas_mem[1][5] = 1'b0; // PHADJ
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assign ilas_mem[1][6] = 1'b0; // ADJDIR
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assign ilas_mem[1][7] = 1'b0; // X
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assign ilas_mem[1][12:8] = L; // L
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assign ilas_mem[1][14:13] = 2'b00; // X
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assign ilas_mem[1][15] = SCR; // SCR
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assign ilas_mem[1][23:16] = F; // F
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assign ilas_mem[1][28:24] = K; // K
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assign ilas_mem[1][31:29] = 3'b000; // X
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assign ilas_mem[2][7:0] = M; // M
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assign ilas_mem[2][12:8] = N; // N
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assign ilas_mem[2][13] = 1'b0; // X
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assign ilas_mem[2][15:14] = CS; // CS
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assign ilas_mem[2][20:16] = NP; // N'
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assign ilas_mem[2][23:21] = SUBCLASSV; // SUBCLASSV
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assign ilas_mem[2][28:24] = S; // S
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assign ilas_mem[2][31:29] = JESDV; // JESDV
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assign ilas_mem[3][4:0] = CF; // CF
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assign ilas_mem[3][6:5] = 2'b00; // X
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assign ilas_mem[3][7] = HD; // HD
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assign ilas_mem[3][23:8] = 16'h0000; // X
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assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] +
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ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] +
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ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] +
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ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] +
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ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] +
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ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7];
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generate
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genvar i;
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for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
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always @(posedge clk) begin
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if (ilas_config_rd == 1'b1) begin
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ilas_config_data[i*32+31:i*32] <= ilas_mem[ilas_config_addr];
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/* Overwrite special cases */
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case (ilas_config_addr)
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'h1: ilas_config_data[i*32+4:i*32] <= i;
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'h3: ilas_config_data[i*32+31:i*32+24] <= ilas_mem[ilas_config_addr][31:24] + i;
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endcase
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end
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end
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end
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endgenerate
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endmodule
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