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axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0'

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Nicola Corna 2021-10-20 13:50:37 +02:00 committed by Laszlo Nagy
parent 18ab43b5a1
commit 5d7f4672f5
2 changed files with 2 additions and 2 deletions
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2
library/axi_i2s_adi/fifo_synchronizer.vhd
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@ -63,7 +63,7 @@ architecture impl of fifo_synchronizer is
signal rd_addr : natural range 0 to DEPTH - 1; signal rd_addr : natural range 0 to DEPTH - 1;
signal wr_addr : natural range 0 to DEPTH - 1; signal wr_addr : natural range 0 to DEPTH - 1;
signal cdc_sync_stage0_tick : std_logic; signal cdc_sync_stage0_tick : std_logic := '0';
signal cdc_sync_stage1_tick : std_logic; signal cdc_sync_stage1_tick : std_logic;
signal cdc_sync_stage2_tick : std_logic; signal cdc_sync_stage2_tick : std_logic;
signal cdc_sync_stage3_tick : std_logic; signal cdc_sync_stage3_tick : std_logic;

2
library/axi_i2s_adi/i2s_controller.vhd
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@ -83,7 +83,7 @@ constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
signal enable : Boolean; signal enable : Boolean;
signal cdc_sync_stage0_tick : std_logic; signal cdc_sync_stage0_tick : std_logic := '0';
signal cdc_sync_stage1_tick : std_logic; signal cdc_sync_stage1_tick : std_logic;
signal cdc_sync_stage2_tick : std_logic; signal cdc_sync_stage2_tick : std_logic;
signal cdc_sync_stage3_tick : std_logic; signal cdc_sync_stage3_tick : std_logic;